Logical Effort

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 Question #1

❑ How to best combine logic and drive for a big

capacitive load?

CL CL

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 Question #2
❑ All of these are “decoders”
▪ Which one is “best”?

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 Method to answer both of these questions

❑ Extension of buffer sizing problem

❑ Logical effort

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 Complex Gate Sizing

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Complex Gate Sizing: NAND-2 Example

2 2
Cgnand = 4CG = (4/3) Cginv
Cdnand = 6CD = 6γCG =2γCginv 2
f = CL/Cgnand = (3/4) CL/Cginv 2

tpNAND = kRN(Cdnand+ CL)

= kRN(2γCginv+ CL)
= kRNCginv (2γ + CL/Cginv)
= tinv (2γ + (4/3)f)

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 Logical Effort

❑ Defines ease of gate to drive external capacitance

❑ Inverter has the smallest logical effort and intrinsic delay
of all static CMOS gates
❑ Logical effort LE is defined as:
▪ (Req,gateCin,gate)/(Req,invCin,inv)
▪ Easiest way to calculate (usually):
– Size gate to deliver same current as an inverter, take ratio of gate
input capacitance to inverter capacitance
❑ LE increases with gate complexity

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 Logical Effort

tpgate = tinv (p + LEf)

Measure everything in units of tinv (divide by tinv):

p – intrinsic delay - gate parameter ≠ f(W)

LE – logical effort – gate parameter ≠ f(W)
f – electrical fanout = CL/Cin = f (W)

Normalize everything to an inverter:

LEinv =1, pinv = γ

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 Delay of a Logic Gate

Gate delay:
Delay = EF + p (measured in units of tinv)
effective fanout intrinsic delay

Effective fanout:
EF = LE f

logical effort electrical fanout = CL/Cin

Logical effort is a function of topology, independent of sizing
Effective fanout is a function of load/gate size

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 Logical Effort of Gates

Normalized delay (d)

t pNAND-2 tpINV
LE=
p=
d= LE=
p=
d=

p = γ·Fan-in
(for top input) 1 2 3 4 5 6 7
Fan-out (f)

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 Delay Of NOR-2 Gate

1. Size for same resistance as

inverter
2. LE = ratio of input cap of gate
versus inverter

Intrinsic capacitance (Cdnor) =

tpint (NOR) =

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 Question

Any logic function can be implemented using

NOR gates only or NAND gates only!

Which of the two approaches is preferable in

CMOS (from a performance perspective)?

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 Logical Effort

[From Sutherland, Sproull, Harris]

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 Optimizing Complex
Combinational Logic

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 Multistage Networks

Effective fanout: EFi = LEifi Only for tree networks

Path delay D = Σdi = Σpi + ΣEFi
Path electrical fanout: F = CL/Cin = Πfi
Path logical effort: ΠLE = LE1LE2…LEN
Path effort: PE = ΠLE F

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 Adding branching

path of interest
CL,on_path

CL,off_path

CL ,on − path + CL ,off − path

Branching effort: b=
CL ,on − path

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 Multistage Networks

Effective fanout: EFi = LEifi

Path delay D = Σdi = Σpi + ΣEFi
Path electrical fanout: F = CL/Cin
Branching effort: ΠB = b1b2…bN
Πfi = ΠΒ F (assuming all paths in the tree are important)
Path logical effort: ΠLE = LE1LE2…LEN
Path effort: PE = ΠLE ΠΒ F

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 Optimum Effort per Stage

When each stage bears the same effort (effective fanout):

EF N = PE
N
EF = PE
Effective fanouts: LE1f1 = LE2f2 = … = LENfN
Minimum path delay
ˆ N
D = ∑ i =1 (LEi f i + pi ) = N ⋅ PE 1/ N N
+ ∑ i =1 pi

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 Optimal Number of Stages

For a given load,

and given input capacitance of the first gate
Find optimal number of stages and optimal sizing
D = N ⋅ PE1/ N + ∑ pi

Remember: we can always add inverters to the end of the chain

ˆ
The ‘best effective fanout’ EF = PE1/ N is still around 4
(3.6 with γ=1)

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 Method of Logical Effort: Summary

❑ Compute the path effort: PE = (ΠLE)BF

❑ Find the best number of stages N ~ log4PE
❑ Compute the effective fanout/stage EF = PE1/N
❑ Sketch the path with this number of stages
❑ Work either from either end, find sizes:
Cin = Cout*LE/EF

Reference: Sutherland, Sproull, Harris, “Logical Effort”, Morgan-Kaufmann 1999.

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 Optimizing Complex
Combinational Logic:
Examples

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 Example 1: No branching

LE = 1 LE = 5/3 LE = 5/3 LE = 1
f=a f = b/a f = c/b f = 5/c

Electrical fanout, F =
Π LE =
PE =
EF/stage =
a=
b=
c=

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 Example 1: No branching
a, b, c are input
capacitances
normalized to
the unit inverter
LE = 1 LE = 5/3 LE = 5/3 LE = 1
f=a f = b/a f = c/b f = 5/c

Electrical fanout, F = 5
Π LE = 25/9
PE = 125/9 From the back
EF/stage = 1.93
a = 1.93 5/c = 1.93
b = 2.23 (5/3)c/b = 1.93
c = 2.59 (5/3)b/a = 1.93

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Our old problem: which one is better?

LE=10/3 1 LE=2 5/3 LE=4/3 5/3 4/3 1

ΠLE = 10/3 ΠLE = 10/3 ΠLE = 80/27
P= 8 + 1 P=4 + 2 P= 2 + 2 + 2 + 1

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 Adding Branching

15 LE = 1
90 F = 90/5 = 18
5 PE = 18 (wrong!)
15 90
EF1 = (15+15)/5 = 6
EF2 = 90/15 = 6
PE = 36, not 18!

Better: PE = F·LE·B = 18·1·2 = 36

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Example 2 with Branching

Select gate sizes y and z to minimize delay from A to B

Logical Effort: LE =
Electrical Fanout: F=
Branching Effort: B=
Path Effort: PE =

Best Effective Fanout: EF =

Delay: D=

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Example 2 with Branching

Select gate sizes y and z to minimize delay from A to B

Logical Effort: LE = (4/3)3
Electrical Fanout: F = Cout/Cin = 9
Branching Effort: B = 2•3 = 6
Path Effort: PE = ∏LE·F·B= 128
Work backward for sizes:
PE1/3 ≈ 5 9C•(4/3)
Best Effective Fanout: EF = z= 5
= 2.4C
Delay: D = 3•5 + 3•2 = 21 3z•(4/3)
y= = 1.9C
5

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