UNIT - VI VHDL PROGRAMMING

Introduction to VHDL - Library, Package, Entity,

Architecture, Data Objects (Variable, signal &
constant), Data Types (scalar, composite array type &
predefined data types, Attributes (necessity and use. ‘event
attribute). VHDL Modeling styles – Dataflow, behavioral &
structural ,VHDL statements - Concurrent Statements
(With. Select, When..Else), Sequential Statements (if..else,
case) VHDL design Examples - Multiplexer, binary adder,
counter, shift register.
IT Syllabus
 Introduction
• Hardware description languages (HDL)
– Language to describe hardware
– Two popular languages
• VHDL: Very High Speed Integrated Circuits Hardware
Description Language
– Developed by DOD from 1983
– IEEE Standard 1076-1987/1993/200x
– Based on the ADA language
• Verilog
– IEEE Standard 1364-1995/2001/2005
– Based on the C language

Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated) 3

 Applications of HDL
• Model and document digital systems
– Different levels of abstraction
• Behavioral, structural, etc.
• Verify design
• Synthesize circuits
– Convert from higher abstraction levels to lower
abstraction levels

Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated) 4

 VHDL
VHDL = V + H.D.L.

V.H.S.I.C. means
Very High Speed Integrated Circuit

Hardware Description Language

Thus…..
V.H.D.L. = Very High Speed Integrated Circuit Hardware Description Language
 VHDL Benefits
1. Public Standard
2. Technology and Process Independent
– Include technology via libraries
3. Supports a variety of design methodologies
1. Behavioral modeling
2. Dataflow or RTL (Register Transfer Language) Modeling
3. Structural or gate level modeling
 VHDL Benefits (cont)
4. Supports Design Exchange
– VHDL Code can run on a variety of systems
5. Supports Design Reuse
– Code “objects” can be used in multiple designs
6. Supports Design Hierarchy
– Design can be implemented as interconnected
submodules
 VHDL Design Units

• Entity Declaration
– Describes external view of the design (e.g. I/O)
• Architecture Body (AB)
– Describes internal view of the design
• Configuration Declaration
• Package Declaration
– Library Declaration
• Package Body
 VHDL Statement Terminator
Each VHDL Statements is terminated using a
semicolon

;
 VHDL Comment Operator
To include a comment in VHDL, use the
comment operator

-- This is a comment
-- This is an example of a comment
y <= 0; -- can occur at any point
VHDL Program Format

Library
Declarations

Entity Basic VHDL Code

Architecture
 Library Declaration
• It is collection of commonly used pieces of
code.
• Allow them to be reused or shared by other
designs. Library

Package

Functions
Procedures
Components
Typical structure of library: Constants
Types
 Library Declaration…..
• To declare library two lines of code required:
1) Containing name of library
2) Use clause

LIBRARY Library_name;
USE Library_name_package_name.pacakage_parts;
 Library Declaration…..
• At least Three packages , from three different libraries are usually
needed in design that are :
1) ieee.std_logic_1164(from the IEEE library)
2) Standard (from std)
3) Work (from work)

Their declaration are as follows:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY std;
USE std.standard.all;
LIBRARY work
USE work.all
 Library Declaration…..
• The libraries std and work are visible by default, so there is
no need to declare them.
• Only ieee libraqry must be explicitly written. And this is only
necessary when the STD_LOGIC(or STD_ULOGIC) data type is
employed in the design.

• The purpose of std_logic_1164: specifies a multilevel logic

system;
• Std is resource library (data type,text i/o etc.)for the VHDL
environment.
• Work library where we save our design ( the .vhd file, Plus all
the files by created by the complier , simulator etc)
 Library Declaration…..
• Ieee library contains following packages:
• Std_logic_1164:Specifies the STD_LOGIC(8 level) and
STD_ULOGIC(9 levels) multivalve logic system.
• Std_logic_arith:specifies the SIGNED and UNSIGNED
data types and related arithmetic and comparison
operation.
• Std_logic_signed:Contains functions that allow
operations with STD_LOGIC_VECTOR data to be
performed as if the data were of type SIGNED
• Std_logic_unsigned:Contains functions that allow
operations with STD_LOGIC_VECTOR data to be
performed as if the data were of type UNSIGNED
 Entity
• An entity defines the input and output ports of a
design.
• A design can contain more than one entity.
• Each entity has its own architecture statement.
 Syntax For Entity Declaration
ENTITY entity_name IS

PORT

(
Port_name : [ MODE ] [ DATATYPE ] ;
port_name : [ MODE ] [ DATATYPE ] ; NO Semi-colon
Port_name : [ MODE ] [ DATATYPE ] ; after Last Signal
.
.
port_name : [ MODE ] [ DATATYPE ]
);

END entity_name ;

IN / OUT / INOUT
1) BIT ( 2-Valued Logic )
2) STD_LOGIC ( 9-Valued LOGIC ) --Preferred
 Input-Output specification of circuit

 Example: my_ckt
 Inputs: A, B, C
 Outputs: X, Y
A  VHDL description:
X
B my_ckt entity my_ckt is
Y port (
S A: in bit;
B: in bit;
S: in bit;
X: out bit;
Y: out bit);
end my_ckt ;
Example of ED For an AND Gate
A
Y
and_gate
B

ENTITY and_gate IS

PORT

(
A : IN STD_LOGIC ;
B : IN STD_LOGIC ;
Y : OUT STD_LOGIC
);

END and_gate ;
 Architecture

– Describe the underlying functionality

or internal organization or operation
of the entity and contains the
statement that model the behavior
of the entity.
– Architecture body is used to describe
the behavior, data flow or structure
of a design.
 Syntax For ARCHITECTURE BODY

ARCHITECTURE arch_name OF entity_name IS

{ block _declarative_item }
BEGIN
{Concurrent _statement}
 Example of AB For AND Gate
ARCHITECTURE andgate_arch OF and_gate IS

BEGIN

Y < = A and B ;

END arch_name ;
The Complete VHDL Program For AND Gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY and_gate IS
PORT

(
A : IN STD_LOGIC ;
B : IN STD_LOGIC ;
Y : OUT STD_LOGIC
);
END and_gate ;

ARCHITECTURE andgate_arch OF and_gate IS

BEGIN
Y < = A and B ;
END arch_name ;
 Architecture Modeling Style

1. Behavioral modeling
2. Dataflow or RTL (Register Transfer
Language) Modeling
3. Structural or gate level modeling
4. Mixed Style of Modeling
 Modeling styles:

1. Structural Modeling: As a set of interconnected

components (to represent structure),
2. Dataflow Modeling: As a set of concurrent assignment
statements (to represent dataflow),
3. Behavioral Modeling: As a set of sequential
assignment statements (to represent behavior),
4. Mixed Modeling: Any combination of the above three.
 Behavioral Style of Modeling

• The behavioral style of modeling specifies the behavior

of an entity as a set of statements that are executed
sequentially in the specified order.
• This set of sequential statements, that are specified
inside a process statement, do not explicitly specify the
structure of the entity but merely specifies its
functionality.
• A process statement is a concurrent statement that can
appear within an architecture.
• Describe behavior (functionality and performances)
• All language features can be used
 Behavioral modeling

• Behavioral descriptions, define responses to signals

• A process statement, too, has a declarative part
(between the keywords process and begin), and a
statement part (between the keywords begin and end
process).

• The statements appearing within the statement part are

sequential statements and are executed sequentially.

• The list of signals specified within the parenthesis after

the keyword process constitutes a sensitivity list and the
process statement is invoked whenever there is an
event on any signal in this list.

• In the example, when an event occurs on signals A, B,

the statements appearing within the process statement
are executed sequentially.
 The sensitivity list

• List of all signals that the process is sensitive to.

Sensitive means that a change in the value of
these signals will cause the process to be
invoked.

30
 Data Flow Style
• It describe how information is passed between
in the circuit.
• View of data as flowing through a design, from
input to output.
• Used Concurrent signal assignment statement.
• Concurrent signal assignment statements are
concurrent statements,
• therefore, the ordering of these statements is
not important in an architecture body
 Example of data flow For AND Gate
ARCHITECTURE dataflow OF and_gate IS

BEGIN

Y < = A and B ;

END dataflow;

Example of data flow For andgate:

 Structural Style
• It has a set of Interconnected component .
• The arrangement and interconnection of
components
• The component declaration declares the
interface of the component to the architecture
 Structural Style
• In the structural style of modeling, an entity is
described as a set of interconnected
components.

entity HALF_ADDER is
port (A, B: in BIT; SUM, CARRY: out BIT);
end HALF_ADDER;
-- This is a comment line.
 model for the HALF_ADDER entity
architecture HA_STRUCTURE of HALF_ADDER is
component XOR2
port (X, Y: in BIT; Z: out BIT);
end component;
component AND2
port (L, M: in BIT; N: out BIT);
end component;
begin
X1: XOR2 port map (A, B, SUM);
A1: AND2 port map (A, B, CARRY);
end HA_STRUCTURE;
 Mixed Style of Modeling
• It is possible to mix the three modeling styles that we
have seen so far in a single architecture body.

• That is, within an architecture body, we could use

component instantiation statements (that represent
structure), concurrent signal assignment statements
(that represent dataflow), and process statements
(that represent behavior).
•Terminology
 Predefined data types

• bit: ‘0’ , ‘1’

• Bit_Vector (MSB downto LSB)
• Std_logic_vector (MSB downto LSB)
• Integer
• Real
• boolean: false, true
• integer: from negative 231-1 to positive 231-1
• std_ulogic: ‘1’,’0’,’H’,’L’,’X’,’U’,’Z’,’-’,’W’
• std_logic: ‘1’,’0’,’H’,’L’,’X’,’U’,’Z’,’-’,’W’
38
 std_logic, and std_ulogic
• ‘1’, ’0’, ’X’  logic 1, logic 0, unknown
• ‘H’, ’L’, ’W’  weak 1,
weak 0,
weak unknown
• ‘U’, ‘Z’, ‘-’  uninitialized,
high impedance,
don’t care

39
 VHDL Object Types

• Constants
• Signals
• Variables
• Files

40
 Constant
• You can think of it just as a name for a value
reset_c := ‘0’; bus_width_c := 32;
• The value assigned to a constant cannot be changed
(the location of memory that stores the value cannot be
modified)

• Benefits:
– a better documented design.
– it is easier to update the design.
– But do not exaggerate !!!

41
 Signals
• It is a physical signal (you can think of it like a piece
of wire)
• A signal is a sequence of time-value pairs
• A signal assignment takes effect only after a certain
delay (the smallest possible delay is called a “delta
time”).
• It is possible to define global signals (signals that can
be shared among entities)
• But more often signals are just locally defined for a
given architecture
42
 Signals
• Syntax :
signal_name <= expression;
• Signal assignment
– new values take effect after some delay (delta if
not specified)
signal LOGIC_A : BIT;
LOGIC_A <= ‘0’;
LOGIC_A <= ‘0’ after 1 sec;
LOGIC_A <= ‘0’ after 1 sec, ‘1’ after 3.5 sec;
 Variables
• Assignment to variables are scheduled immediately (the
assignment takes effect immediately)

• If a variable is assigned a value, the corresponding

location in memory is written with the new value while
destroying the old value.
– This effectively happen immediately so if the next
executing statement in the program uses the value of
the variable, it is the new value that is used.

• Typically, variables are used as a local storage

mechanism, visible only inside a process
44
 Variable Assignment
• Syntax:
• variable_name := expression;
• Variable assignment
– new values take effect immediately after
execution
– Used in processes, procedures and functions
variable LOGIC_A, LOGIC_B : BIT;
LOGIC_A := ‘1’;
LOGIC_B := LOGIC_A;
45
 Selected concurrent Assignment
With expression select
target <= options expression;
{
expression_1 when choices,
Expression_2 when choices,
Expression_n when choices;
}
IF vs CASE – statement Syntax
 Practical

• 4:1 Mux using data flow and structural

modeling
 4:1 Multiplexer
• one output and four inputs, where one of the four inputs
must be selected for output through 2 selection lines.

MUX
I0 S1 S0 y
I1 0 0 I0
y
I2 0 1 I1
I3 1 0 I2
S1 S0 1 1 I3
 4:1 Mux using Data flow
• library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux_41_dataflow is
Port ( i : in STD_LOGIC_VECTOR (3 DOWNTO 0); S1 S0 y
sel : in STD_LOGIC_VECTOR (1 DOWNTO 0);
y : out STD_LOGIC); 0 0 I0
end Mux_41_dataflow;
architecture Dataflow of Mux_41_dataflow is 0 1 I1
begin 1 0 I2
with sel select
y<= i(0) when "00", 1 1 I3
i(1) when "01",
i(2) when "10",
i(3) when others;
end Dataflow;
 4:1 mux Structural Model
• library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux_41_structual is
• port( D0, D1, D2, D3: in std_logic; -- the data lines
• S0, S1 : in std_logic; -- the selector switches
• F : out std_logic);-- the output
end Mux_41_structual;
architecture Behavioral of Mux_41_structual is
component and_3
Port ( a,b,c : in STD_LOGIC;
y : out STD_LOGIC);
end component;
•
• component or_2
Port ( a,b : in STD_LOGIC;
y : out STD_LOGIC);
end component;

• component notGate is --import NOT Gate entity

• port( inPort : in std_logic;
• outPort : out std_logic);
• end component;
•
• signal invOut0, invOut1 : std_logic;
• signal andOut1, andOut2, andOut3, andOut4 : std_logic;
• signal orTop, orBot, orOut : std_logic;
•
• begin
• -- Just like the real circuit, there are
• -- four components: G1 to G4
• GI1: notGate port map(S0, invOut0);
• GI2: notGate port map(S1, invOut1);
•
• GA1: and_3 port map(invOut1, invOut0, D0, andOut1);
• GA2: and_3 port map(invOut1, S0, D1, andOut2);
• GA3: and_3 port map(S1, invOut0, D2, andOut3);
• GA4: and_3 port map(S1, S0, D3, andOut4);
•
• GO1: or_2 port map(andOut1, andOut2, orTop);
• GO2: or_2 port map(andOut3, andOut4, orBot);
• GO3: or_2 port map(orTop, orBot, F);
end Behavioral;
 Practical

• Full adder using behavioral and structural

 Full Adder:

o In a full adder, three bits can be added at a time. The third

bit is a carry from a less significant column.
Alternate Representation of Full-Adder:
 Full adder using behavioral
• library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FA_beh is
Port ( abc : in STD_LOGIC_VECTOR (2 DOWNTO 0);
ca_sum : out STD_LOGIC_VECTOR (1 DOWNTO 0));
end FA_beh;
architecture Behavioral of FA_beh is
begin
process( abc)
begin
case abc is
when "000"=> ca_sum <= "00";
when "001"=> ca_sum <= "01";
when "010"=> ca_sum <= "01";
when "011"=> ca_sum <= "10";
when "100"=> ca_sum <= "01";
when "101"=> ca_sum <= "10";
when "110"=> ca_sum <= "10";
when "111"=> ca_sum <= "11";
when others => ca_sum <= "--";
end case;
end process;
end Behavioral;
•
Full adder using Structural Modeling
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FA_structural is
Port ( a,b,c : in STD_LOGIC;
sum,carry : out STD_LOGIC);
end FA_structural;
architecture Structural of FA_structural is
component and_2
Port ( a,b : in STD_LOGIC;
y : out STD_LOGIC);
end component;
component xor_2
Port ( a,b : in STD_LOGIC;
y : out STD_LOGIC);
end component;
component or_2
Port ( a,b : in STD_LOGIC;
y : out STD_LOGIC);
end component;
signal s1,s2,s3: std_logic;
begin
x1: xor_2 port map (a,b,s1);
a1: and_2 port map (a,b,s2);
x2: xor_2 port map (s1,c,sum);
a2: and_2 port map (s1,c,s3);
r1: or_2 port map (s2,s3,carry);
end Structural;
 Extra practical :Full adder using data
flow
• library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FA_Data is
Port ( a,b,c : in STD_LOGIC;
sum,ca : out STD_LOGIC);
end FA_Data;
architecture Dataflow of FA_Data is
begin
sum<= a xor b xor c;
ca<= (a and b) or (b and c) or (a and c);
end Dataflow;
 Practical

• 3 bit controlled up/down synchronous

counter with preset and clear
3 bit Synchronous Up/Down Counter
Counter has 8 states i.e N=8
2n >= N
n = no. of Flip Flop= 3
Control Input for Flip-flop
input M QC QB QA QC+1 QB+1 QA+1 JC KC J B KB JA KA
0 0 0 0 0 0 1 0 X 0 X 1 X
0 0 0 1 0 1 0 0 X 1 X X 1
0 0 1 0 0 1 1 0 X X 0 1 X
0 0 1 1 1 0 0 1 X X 1 X 1
0 1 0 0 1 0 1 X 0 0 X 1 X
0 1 0 1 1 1 0 X 0 1 X X 1
0 1 1 0 1 1 1 X 0 X 0 1 X
0 1 1 1 0 0 0 X 1 X 1 X 1
1 1 1 1 1 1 0 X 0 1 X 1 X
1 1 1 0 1 0 1 X 0 X 0 X 1
1 1 0 1 1 0 0 X 0 X 1 1 X
1 1 0 0 0 1 1 X 1 0 X X 1
1 0 1 1 0 1 0 0 X 1 X 1 X
1 0 1 0 0 0 1 0 X X 0 X 1
1 0 0 1 0 0 0 0 X X 1 1 X
1 0 0 0 1 1 1 1 X 1 X X 1
 VHDL Program For 3-Bit Up-DOWN COUNTER

• library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter is
Port ( output : out STD_LOGIC_VECTOR (2
downto 0);
preset,clear,clk,up_dwn,rst : in
STD_LOGIC);
end Counter;
 architecture Behavioral of Counter is
begin
process(clk)
variable temp: STD_LOGIC_VECTOR (2 downto 0);
begin
if (clk' event and clk='1') then
if (preset = '1') then
temp := "111";
elsif (clear = '1') then
temp := "000";
elsif (up_dwn = '1' ) then
temp := temp + '1';
else
temp := temp - '1';
end if;
end if;
output<= temp;
end process;
end Behavioral;
 steps to Run VHDL codes:-
1. double click on xiling icon
2. go to file
3. new project
4. give project name ->next
5. select product category
6. select family ->spartan 2
7. select device ->xc25200
8. select package ->PQ208
9. select speed -> -5Q
10. verify simulator ->ISE simulator (VHDL / verylog)
11 .Select preffereed languageVHDL
12.Next->next->next->finish
13.double clink on create new source
14.select VHDL module
15.give same file name->next
16.enter required entity i.e. i/p & o/p
17.next->next->finish
18.program window will open.
19.write VHDL code properly & save it using ctr+s.
20.go to synthesis ->check syntax.
21.check view RDL schematics
 STEPS FOR STIMULATION

1. double click on create new source

2. select test give another file name bench wave form
3. next -> next -> finish
4. it will open initial timing & clock wired
5. select appopriate clock -> finish
6.select desired i/p signal->save.
7.change implementation to behaviovral simulation in source.
8.click on Tbw file then click on xilings
simulator......."simulate behavioural module"

9.it will show simulation result.

END………….