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Why To Do Timing Simulations

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36 views9 pages

Why To Do Timing Simulations

Uploaded by

srikanthmanchidft
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Timing simulations

Need to do timing simulations


• Validating the constraints given by DFT team to STA
• Basically,we are checking if any constraint is not honoured by STA
• Finding out any unconstrained paths
• Missing timing arcs (PT doesn’t see some X -> Y arc but your timing
model does )
• ATPG tool is honouring the exceptions from STA or not
Impact of not doing timing simulations
• Longer post silicon debug times
• Things that would have been caught in timing simulations would
come up in silicon
• Effects time to market
• Coverage loss ? ( we expected some coverage number initially that
effectively has reduced post silicon since we found all paths are not
timed / new exceptions )
Common mismatches in timing simulations –
environment related
• Annotation issues – SDF not annotated properly
• SDF not applied to hard macros
• Wrong hierarchy given for applying SDF
• Blocks for which SDF not available – forgot to disable timing
• SDF generated on different database – silly but happens 
• First flop of OCC synchronizers and MBIST synchronizers not disabled
for timing
Debug strategy when timing simulations are
failing
• First ensure notiming simulations on post-layout are passing
• Check annotation logs are as expected . (Analog blocks will not have
annotation which is expected )
• Check for any $setup/$hold violations in case of X mismatches
• Compare notiming pass waveform with timing failing one
• We can check decompressor/compressor related signals and see
where mismatch is happening
• Its important to confirm if its hold or setup violation loading both
launch and capture flops waveforms
Timing mismatches – X mismatches and 1/0
mismatches – when we will get which type of
mismatches
• If there us data change in the setup/hold window,notifier will toggle
and model will print message with $setup hold and there will be a X
mismatch
• Please note if completely incorrect data is latching,we will get binary
(1/0) mismatches
• Note that setup and hold violations can occur in any corner
• Not necessary that setup only in max and hold only in min
Timing simulations – scenarios when timing
failed
• Waveform not matching for TCK . (STA using one waveform and DFT
using one –caused issue in one IN -> Reg path )
• False path not honoured by Tetramax – set_false_path –setup –from
[get pins LOCKUP/EN]
• Set_false_path –setup –through LOCKUP/Q -> this was honoured
• Not disabling first flop of OCC and MBIST synchronizers
• Missing scan clock definitions in STA sessions
Questions for you 
• There is a scan chain with 10 flops (no compression).Let us assume
there is exactly one hold violation in stuck at capture mode.How
many failures can be expected at the scan out ?
• Can there be hold and setup violation at the same time ?
• What are negative setup and negative hold times ?
• What is negative delay of a gate ?
• What is inertial delay and transport delay ?
• There is a scan chain with 10 flops.If there is exactly one setup
violation in shift,how many failures can be expected at the scan out ?
Questions contd …
• There is a hold violation in scan path ( scan ck1,scan ck2,lockup is
missed ) which was found after tapeout,what can be done now on
silicon ? ( Assume there is no compression in the design )

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