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ECC 3rd IA

This document outlines the internal assessment test for the M.Tech program in Error Control Coding at Veerappa Nisty Engineering College. It includes details such as the date, time, maximum marks, and a list of questions covering topics like Galois fields, BCH codes, and the Viterbi Algorithm. Students are required to answer five questions, selecting one from each part.

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Shrishail Hiremath
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15 views1 page

ECC 3rd IA

This document outlines the internal assessment test for the M.Tech program in Error Control Coding at Veerappa Nisty Engineering College. It includes details such as the date, time, maximum marks, and a list of questions covering topics like Galois fields, BCH codes, and the Viterbi Algorithm. Students are required to answer five questions, selecting one from each part.

Uploaded by

Shrishail Hiremath
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VEERAPPA NISTY ENGINEERING COLLEGE SHORAPUR

Department of Electronics & Communication Engineering (LDC)

M.Tech-INTERNAL ASSESSMENT TEST-III 2024-25(ODD Semester)

STAFF NAME:-Prof. SEM:- IIIrd

SUBJECT NAME:- ERROR CONTROL CODING SUBJECT CODE:-22LDC325

DATE:- -04-2025 TIME:-02.00 to 3.30pm MAXIMUM MARKS:-20

Note: - 1. Answer any FIVE full questions, choosing anyone full question from each part.

Q No QUESTIONS Marks
4 4
Construct a circuit for addition and multiplication in GF (2 ). Use P(x) = 1 + x + x to
Q1 04
generate GF(24).
OR
Give the circuit for Galois field (2 ) multiplier for multiplying GF(24) by α3 and explain multiplication of
4
Q2 04
two arbitrary field elements.

Q3 Draw a decoder circuit for q-ary BCH code and explain the working. 04

OR
04
Q4 With an appropriate diagram, explain the general type – II one step majority logic decoder.

Q5
VN/ME/15ME753&17ME754
Explain with suitable diagram type – I one step majority logic decoder error correction procedure. 04

OR
Consider the (3, 1, 2) non systematic feed forward encoder with g(0) = (1 1 0), g(1) = (1 0
1), g(2) = (1 1 1)
i)Draw the encoder block diagram 04
Q6
ii)Find the time domain generator matrix G
iii)Find the code word ‘V’ corresponding to the information sequence x = (11101) &
(11100) using time domain and transform domain approach
Q7 Explain the steps involved in Viterbi Algorithm with example. 04

OR

With a flow chart explain ZJ or stack Algorithm. 04


Q8

Consider the (3, 1, 2) non systematic feed forward encoder with g(0) = (1 1 0), g(1) = (1 0 04
1), g(2) = (1 1 1),
Q9
i)Draw the encoder block diagram ii)Draw state table iii)Draw state transition table
iv)Draw the state diagram
OR
Consider the convolution encoder with g(x) = (1 + x, 1 + x2, 1 + x + x2). If the received
Q10 sequence ν = [110, 110, 110, 111, 010, 101, 101]. Using Viterbi algorithms find the 04
transmitted sequence. Assume that the codeword is transmitted over BSC channel.

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