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DF University Paper 2022

The document is an examination paper for the Fundamentals of Digital course at Mandal University, covering various topics in digital electronics and Boolean algebra. It includes multiple questions on binary conversions, De Morgan's Laws, adder circuits, decoders, flip-flops, and sequential circuits. The exam is scheduled for December 19, 2022, with a total of 60 marks and a duration of 2.5 hours.

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hiro142sweethome
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10 views2 pages

DF University Paper 2022

The document is an examination paper for the Fundamentals of Digital course at Mandal University, covering various topics in digital electronics and Boolean algebra. It includes multiple questions on binary conversions, De Morgan's Laws, adder circuits, decoders, flip-flops, and sequential circuits. The exam is scheduled for December 19, 2022, with a total of 60 marks and a duration of 2.5 hours.

Uploaded by

hiro142sweethome
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Enrollment No. .

Seat No.

MANDAL UNIVERSITY
THE CHARUTAR VIDYA
B.E./B.TECH. -SEMESTER3
DECEMBER 2022 (REGULAR)EXAMINATION

FUNDAMENTALS
Course Title: DIGITAL
Course Code: 102040303

Total Printed Pages:02 Maximum Marks: 60


Time: 10.00 am to 12.30 pm
Date: 19/12/2022
Instructions:
Attempt all questions.
marks for each question.
Numbers to the right indicate full
M a k e suitable assumption if required, do specify the same.

Q:1 (A) Answer the Following. (Each question


carries one marks). 10
(i) Convert (01110110101) 2= s
(ii) Convert (197.25) 10 2
(1011 0111)2.
(iii) Find the l's complement ofthe 8-bit binary representation
(iv) Define Propagation delay.
number 8 is_
(v) The Excess -3 code for decimal
(vi) A.(B +C)= as per the Distributive law of Boolean Algebra.
Sum bits and Carry bits.
(vii) A4bit binary parallel adder has
2m(0) + d(l,2,3,4,5,6,7,8,9,10,I 1,12,13,14,15) is
(vii)f(A, B, C, D) =

(ix) Define Sequential Circuit.


(x) How many cells are there on a 4 -variable K map?.
-

Q:2 (A) State and Prove De Morgan's Laws [041


(B) Reduce the following to the minimum terms and variables using Boolean [06
laws.
1) (X®Y) OXY
2) (A+C) (AD+AD) +AC+C"

: 3 (A) Draw and explain the working ofa Half Adder cireuit and implement a Full [05]
Adder circuit using Half Adders with combinational circuits.
(B) Minimize folowing Boolean function using K-map & design the simplified [05]
function using logic gates: fA, B, C, D) = Z m(0, 2, 4, 6, 8, 10, 12, 14)

OR
(B) Minimize following Boolean function using tabulation method (Quine [05)
MeClusky method) & simplify f{A, B, C, D) =m(1,2,4,6,7,11,15).

Q: 4 (A) Explain 3 to 8 decoder with basic logic gates and truth table. [05
(B) Design a combinational circuit for Binary to Gray code conversion. [0S]
OR
(B) Design a comparator using basic logic gates.
[05)
Q:5 (A) Draw the diagram of a clocked D flip-flop and explain its characteristic table [05]
and equation.

Page 1 of 2
counter using JK flip-flops. [05]
(B) Design a 4-bit ripple up
OR
registers and explain any one in detail. 05
(B) List types ofshift
[05]
Write a short note on Mealy model.
Q:6 (A) A and B and input X and output Y
is [05]
(B) A sequential circuit with 2 D flip flops
and output equations.
specified by the following next state
+1) = AX + BX
A(t
B(t +1) = AX
Y = (A + B)X'

1) Draw the logic diagram of the circuit.


2) Derive the state table.
3) Draw the state diagram.
OR
between synchronous and asynchronous sequential circuits. [05]
(B) Distinguish
********

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