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DLD - Question Paper - Mid-Sem - March 2025

This document outlines the mid-semester examination details for the B.Tech.-M.Tech. Computer Science and Engineering (Cyber Security) course at the National Forensic Sciences University. It includes the exam date, subject code, maximum marks, and a breakdown of sections with various questions related to digital logic design. The exam covers topics such as number systems, combinational and sequential circuits, Boolean functions, and logic gate implementations.

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509 views1 page

DLD - Question Paper - Mid-Sem - March 2025

This document outlines the mid-semester examination details for the B.Tech.-M.Tech. Computer Science and Engineering (Cyber Security) course at the National Forensic Sciences University. It includes the exam date, subject code, maximum marks, and a breakdown of sections with various questions related to digital logic design. The exam covers topics such as number systems, combinational and sequential circuits, Boolean functions, and logic gate implementations.

Uploaded by

Srijita
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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National Forensic Sciences University

School of Cyber Security and Digital Forensics


Course Name: B.Tech.-M.Tech. Computer Science and Engineering (Cyber Security)
(Batch: 2024-29)
Semester - II
Mid Sem Examination (March 2025)
Subject Code: CTBT-ESC-201 Time: 10:30 AM – 12:00 PM
Subject Name: Digital Logic Design Date: 25-03-2025
Maximum Marks: 50

Section A
Attempt all in this question: 16=6
1) Convert the following numbers as directed:
i) Convert (234)8 into binary form.
ii) Represent 29C16 in octal.
iii) Represent (110111011101111011)2 in hexadecimal.
iv) Write the BCD code of decimal 15.
v) What is Demultiplexer?
vi) Define radix complement.
Section B
Attempt any four from the following: 5  4 = 20
2) Differentiate
i) Combinational and Sequential circuit. 2
ii) Latch and Flip -Flop 3
3) Construct a 4-to-16-line decoder with 2-to-4-line decoders. 5
4) Discuss prime implicant and its types. 5
5) Minimize the following Boolean function using K-map: 5
i) F(A,B,C,D) = Σ m(1, 3, 7, 11, 15) + d(0, 2, 5)
ii) Y(A,B,C,D) = Σ m(0, 1, 2, 3, 5, 7, 8, 9, 11, 14)
6) Find the complement function for the following: 5
i) F = X’Z’ + YZ
ii) F = (A+B)(B’+C’)(A’+C)
iii) F= ABCD
iv) F = A+B+C+D
v) F = A + AB + ABC + ABCD
7) Explain the Ex-OR gate. How Ex-OR can be used for Parity generation and checking? 5

Section C
Attempt all in this section: 8  3 = 24
8) Explain the number systems (any four) in detail. 8
OR
Consider the function: Y =(AB)+ (A C)’ B’
i) Draw a combinational logic circuit that implements this function.
ii) Draw a truth table for this function.
iii) Write a sum-of-products representation of Y.
iv) Write a product-of-sum representation of Y.

9) Design a 2-bit magnitude comparator. 8


OR
Design a logic circuit that has three inputs, A, B, and C, and whose output will be HIGH only when a
majority of the inputs are HIGH.

10) Discuss the NAND gate as a universal gate (implement NOT, AND, OR & NOR gate using NAND gate).
8

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