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MOSFET
In Metal Oxide Semiconductor Field Effect Transistor (MOSFET), role of MOS capacitor
structure is very important. We first discuss in brief about this capacitor and associated band
diagram. For MOS capacitor, two extremely important physical parameters are the electron
affinity and the work function, which can be best explained with the help of band diagrams,
as shown in the figure. Similar band diagram and definition of affinity, work function etc.
were discussed in context of MS Schottky junction earlier.
Values of work functions of some metals are
given in the Table below.
Metal Values of Work
function (eV)
Al 4.06-4.44
Cu 4.48-4.98
Ag 4.52-4.74
Au 5.31-5.47
W 4.47-5.25

If we see the basic structure of MOS capacitor, we start with an n-type (or p-type) Si
substrate, and grow a layer of silicon dioxide (SiO2) on top of it by thermal oxidation. Then, a
layer of metal or Si is deposited on top of the oxide by chemical vapour deposition (CVD).

MOSFET Contd…

Since SiO2 is amorphous, hence, Si deposited on it cannot be perfectly crystalline, and,

instead, forms several small crystalline regions, with no symmetry between these regions.
Thus, the resulting structure becomes polycrystalline, and, hence, the name poly-Si or simply
poly is assigned to this layer. Generally, poly layers have much higher resistivity than a
perfectly crystalline silicon, due to the presence of a high concentration of scattering centres
in terms of the grain boundaries (i.e., the interface between two adjacent crystalline regions).
These scattering centres reduce the scattering time, and, thus, the carrier mobility,
considerably. Hence, the poly layer is doped very heavily in order to increase its conductivity,
so that it can behave somewhat like a metal (nevertheless, its resistivity still remains way
higher than a perfect metal).
An Ohmic contact is also provided at the backside of the wafer to contact the substrate. The
resulting structure fabricated on a p-type substrate is shown in figure below.

Band Diagram of an Ideal MOS Structure: Let us

assume that the metal and the semiconductor have
same work functions and there is no charge in the
oxide, i.e., we are considering an ideal MOS
structure. The band diagram (along the y-axis), for
any x, is shown in the next slide.

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MOSFET Contd…

Since there cannot be any current perpendicular to the Si-SiO2,

interface (due presence of the dielectric SiO2, in between the gate
and the semiconductor) the metal and the semiconductor side Fermi
levels are aligned. The vacuum level Evac which is equidistant from
both EFm and EFs, since we have assumed that the metal a
semiconductor have identical work functions.
y
Now, we are in a position to draw the band diagram of
SiO2, with its conduction band lying below the vacuum
level by an amount equal to the electron affinity of SiO2,
qc(SiO2), which happens to be equal to 0.9 eV, and the
valence band lying below the conduction band by an
amount equal to the band gap energy of SiO2, Eg(SiO2),
which is roughly equal to 9 eV.
Then, depending on the type and magnitude of the
substrate doping, we can draw the intrinsic level Ei.

For this case, since we are considering a p-type substrate, hence, Ei, will lie above EF by an
amount equal to qF, where F is referred to as the bulk potential or Fermi potential, and is an
extremely important parameter for MOS device analysis. For uniformly doped p-type
substrate, with doping concentration NA cm-3, it is given by
NA
F  VT ln ------ (145)
ni

MOSFET Contd…

For an ideal MOS structure, all the energy bands are flat y

everywhere, which implies that there is no charge and electric

field anywhere within the device (recall that presence of electric
field in any region would necessitate a gradient or energy bands
in that region). We also define two very important energy
barriers for electrons and holes, which prevent transport of these
carriers from the semiconductor to the oxide layer. This Si-SiO2,
barrier height for electrons can approximately computed as
follows.

Since the electron affinity for SiO2, is about 0.9 eV, and that for Si is about 4.1 eV, hence, this
barrier height for electrons roughly equal to 3.2 eV. Under normal operation of the device,
almost negligible, number of electrons in the conduction band of Si would have this amount
of energy. So, direct transport of electrons from Si to SiO2, is almost impossible under
operating condition. The Si-SiO2, barrier height for holes can similarly be found as equal to
the difference between the band gap energy of SiO2 and the sum of the band gap energy of Si
and the Si-SiO2 barrier height for electrons, i.e., [9-(1.12+3.2)]eV, which comes out to be 4.68
eV. Thus, the holes have a greater barrier height to surmount than the electrons, and transport
of holes from the semiconductor to the oxide is far more improbable than electron transport
across the barrier.

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MOSFET Contd…

Non-idealities: Flat
Band Voltage: In a real
MOS capacitor structure, the
metal work function and the
semiconductor work function
are not necessarily equal to
each other. Let us consider
the case where the metal
work function is greater than
that of the semiconductor,
i.e., m> s. The resulting
band diagram of the structure
at equilibrium is shown in
the Fig.(a). right side

Fermi levels of the metal and the semiconductor are aligned to be consistent with the situation that no
current flows perpendicular to the surface. Here, we make an important point that there cannot be any
discontinuity in the vacuum level Evac for a homo-structure (i.e., devices fabricated on the same material,
e.g., Si). While the vacuum level continuous, several interesting observations are there. First, we see that
the oxide conduction band has a gradient, which implies that there is an electric field present across the
oxide. Also, in the semiconductor, the bands are bent near the Si-SiO2, interface, which implies that there is
an electric field in the semiconductor as well. The way the bands are bent in the semiconductor, the valence
band has come closer to the Fermi level at the surface than that in the bulk, which implies that the
concentration of holes is more near the surface than that in the bulk.

MOSFET Contd…

This essentially means that there is a build-up of

positive charges (which can only be due to holes in
a p-type semiconductor) on the Si side of the Si-
SiO2 interface. Hence, the resulting electric field is
directed from the semiconductor side to the metal
side, both in the semiconductor as well as across
the oxide level as shown in Fig. (a). In order to
make the semiconductor neutral, metal side needs
to be lowered by an amount that is equal to the
difference between the work functions of the metal
and the semiconductor.
Remembering the fact that these energy bands are drawn for electrons, it is obvious that a
positive voltage VFB1 (say), must be applied in order to lower the electron energy in the metal
side. Magnitude of this voltage would be = (m-s) is known as the first component of the flat-
band voltage of the device. So, it is given by

VFB1= m - s=ms -------- (146)

Since m has been assumed to be greater than s, the VFBI is a positive quantity. However, if a
metal-semiconductor system has m < s , obviously, VFB1 would be negative, which is the case
for Al-SiO2,-Si system.

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MOSFET Contd…

Problem: Consider a two-terminal MIS structure on p-type substrate (doping concentration =

1016 cm-3). Assuming that there are no charges present in the oxide. Calculate the flat-band
voltage of the structure, if it employs (a) Al gate and b) p+-poly gate (assume that the Fermi
level is coincident with the valence band). Data: affinity (qc) of Si = 4.05 eV and Eg(Si) = 1.12
eV.
Solution First, we need to find the Fermi/bulk potential of the semiconductor, given by

Eg
 qs  qc   qF  4.05  0.56  0.35  4.96eV
2q
In the absence of any oxide charge, the flatband voltage VFB of the device is same as VFB1 given
as: for Al gate

VFB  m  s  4.1  4.96  0.86 V

for p+Poly-Si gate Eg

VFB  c   s  4.05  1.12  4.96  0.21 V
q
Since m for this case is equal to (c+Eg/q)

MOSFET Contd…

The second component of the flat-

band voltage originates from the
charges present in the oxide layer.
These charges form a delta function
(i.e., a sheet of charges, having
negligible thickness) on the SiO2 side
right at the Si-SiO2, interface.
Obviously, these charges would
immediately induce mirror charges of
opposite type on the other side of the
interface, i.e., on the Si side.
This would be achieved by repelling holes from the surface towards deep into the bulk, uncovering
negatively charged acceptor ions near the surface. Thus, a depletion region would form on the Si side near
the interface and the bands would bend down wards (assuming, of course, that the substrate is p-type). This
Situation is shown in figure above, (a). In order to eliminate this effect of oxide charges on the
semiconductor surface charge states, they need to be compensated totally by the charges put in the metal.
Note that the structure behaves like a parallel plate capacitor with the dielectric between the two plates (i.e.,
the metal and the particular location of the oxide charges within the oxide) having a thickness equal to tox
(i.e., the oxide thickness), if all the charges are located right at the Si-SiO2, interface. The oxide capacitance
per unit area C'ox is defined by C'ox =εox /tox where εox is the permittivity of the oxide layer, given by εox =
[εr(SiO2) × ε0], where εr(SiO2) is the relative dielectric permittivity of the SiO2, layer (=3.9), and ε0 is the
permittivity of free space (=8.854 × 10-14 F/cm). The oxide charges per unit area are denoted by Q'ox (in
C/cm2) with Q'ox = qN'ox, where N'ox is the number density (numbers/cm2) of the oxide charges. For Si/SiO2
this charge is +ve type

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MOSFET Contd…

If it is assumed that the location of these

charges are right at the Si-SiO2, interface (on
the SiO2 side), i.e., they form a sheet charge of
negligible thickness, then, application of a
voltage VFB2 = - Q′ox/ C′ox at the gate would
compensate these charges completely, and,
consequently, no mirror charges would appear
in the semiconductor side, thus creating
flatband condition within the semiconductor,
as shown in Fig. (b). This is the second
component of the flatband voltage and is
given by VFB2 = - Q′ox / C′ox ------- (147)

Thus net flatband voltage can be expressed as

Problem: Repeat the previous problem, i.e. calculate Flatband voltage but now assume 4.5 × 1011 cm-2
oxide charges are present right at the Si-SiO2 interface on the SiO2 side. Assume tox is 10 nm.
Solution: Q′ox = q N′ ox=7.2 × 10-8 C/cm2, C′ox= 3.45 × 10-7 F/cm2, VFB2 = - Q′ox / C′ox = -0.21 V
For Al Gate: VFB= (-0.86-0.21)V= -1.07 V
For p+ Poly Si Gate: VFB=(0.21-0.21) V=0 V.

MOSFET Contd…

An extremely important parameter in MOS device analysis is known

as the surface potential, and is denoted by the symbol ѱs. It is defined
by the relation:

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MOSFET Contd…

Assume an MOS
structure fabricated on
p-type Si, with zero flat-
band voltage, i.e.,
when the applied gate-
to body voltage VGB is
zero, ѱs =0, as shown
in Figure (a)

Now, if a negative VGB were applied, then it would attract positive charges
towards the Si surface due to the parallel-plate capacitor action. Positive
charges in p-type Si are obviously holes, and, thus, holes would accumulate
near the surface, and from the basic carrier concentration relations, the
valence band in the semiconductor would move towards the Fermi level near
the surface, as shown in Figure (b). This mode of operation is known as
accumulation, and based on the definition of ѱs, it is negative under this
mode.

MOSFET Contd…

Now, assume a positive

VGB is applied. This
would repel holes from
the surface and
uncover negatively
charged acceptor ions
near the surface, and a
depletion region would
start to form as shown
in Figure (c).

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MOSFET Contd…

Any further increase in VGB

would move Ei below EFs, at the
surface. This has tremendous
physical implication, since now
the Fermi level at the surface is
closer to the conduction band.
This implies that the
concentration of electrons at the
surface is more than that of the
holes.

MOSFET Contd…

Surface Potential Ѱs Mode of operation

Accumulation
Flatband
Depletion
Intrinsic
Weak Inversion
Moderate Inversion
Strong Inversion

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MOSFET Contd…

Note: The big question is: where do there electrons come from in a p-type
Substrate? The answer to this question is: the substrate. Some of the
equilibrium minority carriers (electronics) in the substrate would get
attracted to the surface because of the large electric field, directed from the
gate to the substrate, under these circumstances. As VGB keeps on
increasing, this field would also keep on increasing, the bands would bend
further, and the strength of the electron concentration at the surface would
keep on increasing. Thus, the surface inversion becomes stronger and
stronger.

The most important parameter is total semiconductor charge density per

unit area. After a detail calculation, expression of this charge density can be
derived as,

MOSFET Contd…

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MOSFET Contd…

MOSFET Contd…

Threshold Voltage: The voltage

applied to gate w.r.t. body (VGB) to
make starting of strong inversion
is called threshold voltage. Now
the applied voltage to gate drops
in three distinct regions namely, a)
across the oxide, (ѱox), b) across
the semiconductor (ѱs) and c) one
accounting for work function
difference.

So, VGB= ѱox+ ѱs+ ϕms ----------- (153).

This drops are shown in the figure above. The charge balance
equation tells that the sum of charge densities per unit area is zero.
Q′G+Q′ox+Q′s=0 ------------- (154) where, G stands for gate charge,
ox stands for oxide charge and s stands for semiconductor.

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MOSFET Contd…

Now, the charge density in the semiconductor (Q′s) is composed of

depletion charge density (Q′B) and inversion charge density (Q′I). As
the oxide charge density remains almost constant but other
components changes with changing VGB. So,
Q′G= C′ox ѱox ------ (155), where, C′ox is oxide capacitance per unit
area.

Thus potential balance equation tells that,

MOSFET Contd…

A new parameter , denoted as the body effect coefficient, and is

given by

This is a technology parameter, since it is a function of the substrate

doping concentration (NA) and the oxide thickness (tox). Equation
(157) carries a lot of physical implications. First, for a given ѱs, VGB
can be easily found analytically, however the reverse is not true, i.e.,
for a given VGB, analytical solution of ѱs does not exist, since Eq.
(157) is transcendental in nature. Thus, the only option left is to resort
to numerical techniques, i.e., iterations. However, the presence of the
exponential term in Eq. (157) would make the iterations converge
rapidly; nevertheless, the need of a numerical analysis in order to
solve Eq. (157) (to obtain ѱs, for a given VGB) is a big computational
bottleneck for MOS and MOSFET structure analysis.

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MOSFET Contd…

The other interesting observation from Eq. (157) is that for ѱs<2ϕF, the
exponential term under the square root sign can be neglected, with the
resulting expression given by

Since ѱs, show a tendency to flat out for values beyond 2ϕF, hence,
earlier researchers found that assuming ѱs to get pinned to a value of
2ϕF is an excellent assumption for the onset of strong inversion and
beyond. Based on this, the standard expression for the threshold
voltage VTH (i.e. the gate-to- body voltage needed to create strong
inversion at the surface of the structure) is found as

MOSFET Contd…

Problem: Determine the threshold voltage of a two-terminal

MOS structure fabricated on a p-type substrate (doping
concentration = 1016 cm-3), having an oxide thickness of 10
nm. Assume that the flatband voltage of the structure is -1 V.
Soluion: For 10 nm thick oxide layer, the oxide capacitance
per unit area C’ox is equal to 3.45 × 10-7 F/cm2. Thus, we
obtain the body effect coefficient  as

For a substrate doping concentration of 1016 cm-3, the bulk potential is

equal to 0.35 V. Now, based on the conventional definition, we apply
Eq. (160) in order to evaluate the threshold voltage:

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MOSFET Contd…

Thus, the difference in the threshold voltage for these two cases comes out to be only about 110 mV. Note
that instead of 4VT, if we had chosen 6VT it would have produced a different VTH, however, the order of
difference between the values would still be around hundreds of mV. In earlier days, when the power supply
voltages typically ranged between 15-30 V, this small change of 110 mV in VTH was completely
inconsequential. However of late, with the power supply hovering around 3 V or below, this small change in
VTH can cause a large change in the predicted device performance. Thus, one has to be careful while
defining an exact value of the threshold voltage, which can only be done by matching it with experimental
data.

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MOSFET Contd…

from the incremental charge balance expression

C-V Characteristics contd.. MOSFET Contd…

The first term on the right-hand-side of the CV-1 Eq. can be easily identified as 1/C′ox from
Gauss' law, whereas the second term on the right-hand- side of Eq. (CV-1) actually expresses
the rate of change of the total semiconductor charge density with respect to the surface
potential, and is representative of a capacitance. We define this component as the
semiconductor capacitance (per unit area) with its expression given by

The negative sign in this equation is used to yield a positive value of the capacitance.
Combining these results, Eq. (CV-1) can now be expressed as

This implies that the total gate-to- body capacitance (per

unit area) of the structure is actually a series combination
of two capacitors (per unit area): one due to the oxide
(C′ox) and the other due to the semiconductor (C′s). This
gives us the first glimpse of the small-signal equivalent
circuit of a two terminal MOS structure, as shown in
Figure right side.

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C-V Characteristics contd.. MOSFET Contd…

Now, obviously, the behavior of the gate-to-body capacitance with respect to the applied gate-
to-body voltage should be a function of the region of operation, since different patterns of
charge changes with respect to the applied voltage, are observed in different regions. As an
example, consider the accumulation region. Recall that in this region, the total semiconductor
charge density Q′s changes exponentially with respect to ѱs , which yields an extremely large
value of the semiconductor capacitance C′s. Under this condition, the total gate-to-body
capacitance C′gb is simply that of the oxide (C′ox) Thus, in the accumulation region, the device
behaves like a perfect parallel-plate capacitor, with almost no voltage dependence (except at
the lower part of accumulation, i.e., near the flatband condition). The behaviour in the
depletion and inversion regions is more interesting and intriguing. For values of surface
potential ѱs, greater than 3VT,(~78 mV at room temperature), we can use the simplified
expression for the total semiconductor charge density Q's given by Eq. (156). Taking the
derivative of that expression with respect to the surface potential ѱs, we get the following
expression for the semiconductor capacitance:

C-V Characteristics contd.. MOSFET Contd…

Since the total semiconductor charge is composed of depletion charge and inversion charge,
hence, the total semiconductor capacitance (C′s ) can be further divided into two components:
one due to the depletion charges (C′b) and the other due to the inversion charges (C′i ), with
C′s = C′b + C′i. Thus, the small-signal equivalent circuit as shown in last slide can be further
expanded to include the capacitances associated with the depletion and the inversion charges
individually by splitting C’s into C’b and C’i ,which happen to be in parallel with each other.
This equivalent circuit is shown in Figure below. An exact analysis of the structure, without
making any assumptions whatsoever, gives the following expressions for the depletion and the
inversion capacitances

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C-V Characteristics contd.. MOSFET Contd…

All these capacitances are plotted as function of surface potential.

C-V Characteristics contd.. MOSFET Contd…

Now, as VGB is raised to a value near VFB (but still less than VFB), the capacitance would start
to drop since the semiconductor capacitance at this point would be a function of the bias
voltage. When VGB becomes exactly equal to VFB, the semiconductor surface is under the
flatband condition, and the total gate-to-body capacitance C′gb of the structure will be given by
a series combination of C′ox. and C′FB (semiconductor flat band capacitance, when ѱs=0,
[C′FB=εs/LDp(Debye length)]. If VGB is increased further, then the semiconductor surface would
start to deplete, and the depletion capacitance C′b will now appear in series with C′ox. With
increasing VGB, ѱs, and dB would keep on increasing and C′b , would keep on dropping, which
would cause C′gb to decrease with increasing VGB and this trend would continue.
However, as ѱs approaches the inversion layer starts to build up and the inversion capacitance
C′i starts to become important. Eventually, in the strong inversion region, C′i becomes much
larger than C′b, (as well as C′ox.) and C′gb approaches C′ox., the same behaviour as observed in
the accumulation region). However, there is a significant difference between these two regions,
even though both of them portray the same characteristic. In the accumulation region, the
surface charges are constituted of holes, which are the majority carriers in the p-type substrate,
and are in a plentiful supply. However, the inversion charges are made up of electrons, which
are the minority carriers in a p-type substrate, and their supply is limited. Note that in the
strong inversion region, the rate of electron build up at the surface is a strong function of the
thermal EHP generation rate, since it is the only source of generation of minority carriers, in
the absence or any other excitation.

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C-V Characteristics contd.. MOSFET Contd…

Thus, we have two distinct

behaviours: low frequency and
high frequency characteristics.
An additional behavior is
observed if the measurement
frequency is extremely high. For
this case, not only the inversion
layer electron build-up is unable
to keep up with the signal
frequency, but also a quasi-non-
equilibrium state
is created within the substrate, where a large amount of depletion ions ate uncovered
instantly (known as deep depletion) in order to compensate for the gate charge. This
causes a sudden widening of the depletion region, which drastically reduces the
depletion capacitance as well as the total capacitance of the structure. The entire
behaviour is shown in Figure above. This is an extremely important characteristic,
from which various device parameters can be extracted.

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MOSFET Contd…

Threshold Voltage: Consider the NMOS structure shown in Figure. Let us consider first,
both the source and the body terminals are tied to ground. Under this condition, it should be
obvious that the structure is electrically two-dimensional in nature, i.e., there is a vertical
electric field between the gate and the substrate because of the applied gate potential, as well
as a lateral electric field between the drain and the source due to the applied drain potential.
Both these fields have a strong influence on the overall behaviour of the device, and
essentially these devices operate under a two-dimensional field.

Threshold Voltage contd.. MOSFET Contd…

Now, if we assume that the applied drain

voltage is also equal to zero, then the
device would have only one electric field
due to the gate. Now, if the gate voltage is
greater than the flatband voltage VFB then
we first have the depletion and then the
inversion modes of operation. The band
diagram of the structure along the y-
direction would look exactly similar to
that for a two- terminal MOS structure,
and would be the same for all x, since the
drain-to-source voltage VDS is equal to
Zero. This is shown in Figure below.
Depending on the value of the gate-to-
body voltage VGB, the surface potential
ѱs, would change according to that given
by Eq. (157), which is reproduced here
for convenience:

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Threshold Voltage contd.. MOSFET Contd…

Threshold Voltage contd.. MOSFET Contd…

Since the junctions are n+p, hence,

we have invoked the one-sided step
junction approximation, and shown
the depletion region only in the body.
There will be depletion region under
the gate as well due to the gate
voltage. Note that even though all the
depletion regions are touching each
other, the device is not under punch-
through breakdown, since as we
move from the source to the drain,
the source and drain regions are
lateral and contributed by the
source/drain, whereas those under
the gate are vertical and contributed
by the gate.

However, if a drain voltage VD (note that with the source grounded, VD,
equals the drain-to-source voltage VDS) is applied, the scenario becomes
different. Since it alters the charge balance scenario along the channel, i.e.,
along x, with this situation shown in Figure (b) [ next slide]

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Threshold Voltage contd.. MOSFET Contd…

Note also that VGC at x = 0 is equal to VGS (=VGB-VSB), and at x= L, it is equal to VGD(= VGB-
VDB), with VGD being less VGS (since VDB >VSB). Hence, as we move along the channel from
the source to drain, VGC keeps on reducing and the level of inversion keeps on dropping
(since VGC, in effect, is responsible for the creation of the inversion layer). This phenomenon
is shown by a wedge shaped inversion layer in Fig. (b).

Threshold Voltage contd.. MOSFET Contd…

Also, the drain-body reverse bias being larger than

(a)
the source-body reverse bias, the depletion region
under the drain has larger width (shown as dBD in the
figure) than that under the source (denoted by dBS in
the figure). Corresponding band diagrams are shown
in Fig. (a) and (b) in this slide. Fig (a) is valid for
structure [ Fig. (b) also, ] but only at source end, i.e.,
at x = 0. On the other hand, the band diagram shown
Fig. (b) holds good for the structure shown in Fig.
(b), but only at the drain end, i.e., at x = L.

In Fig. (a), there is a single continuous Fermi level

(EF) in the substrate, with its separation from the gate
Fermi level (EFm) being equal to qVG. The small
width of the depletion region dBS, whereas in Fig. (b),
the Fermi levels of the surface electrons (EFn) and
bulk holes (EFp = EFs) [these are actually quasi-Fermi
levels (Imrefs)] split by qVD. This is because the
electrons at the drain end of the channel have an
energy qVD lower than that of the holes in the
substrate, which is portrayed clearly in Fig. (b).

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Threshold Voltage contd.. MOSFET Contd…

Also noted that in this figure, the EFn at the surface

and the Fermi level of the gate (EFm is separated by
q(VG- VD). At any other point in the channel, the
band diagram would look similar to the one shown in
Fig. (b), with the exception that in Si, EFn and EFp
would be separated by qVCB(x), and at the surface,
EFn and EFp would be separated by q[VG -VCB(x)].
The larger depletion width dBD near the drain should
also be noted. now if we put,

In Eq (161), we can get

So,

Threshold Voltage contd.. MOSFET Contd…

Equation (162) yields that the gate-to-channel voltage required to create strong inversion
in the channel is a function of the position x, and would increase as we move from the
source to the drain, since VCB(x) increases with increasing x. Thus, we have to make some
other assumption(s) in order to define an exact value of the threshold for a given device.
In the literature, it has been universally accepted to define this parameter as gate to source
voltage (VGS) required to create strong inversion at the source end (i.e. at x=0). Therefore,
the expression for the threshold voltage VTHN (which is also abbreviated as VTN) for an n-
channel MOSFET can now be obtained from Eq. (162) by putting x = 0, and identifying
that VCB at x = 0 is equal to VSB. Thus,

Similarly for p-channel MOSFET,

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MOSFET Contd…

Body effect: Eqn. (163) and Eqn. (164) can be expressed as,

Here, VBS is nothing but potential of substrate w.r,t. source. It may be +ve or -ve

For a given value of γ, VTN has a square root dependance on VBS. This
phenomena is called Body effect. Here, VBS is nothing but potential of substrate
w.r,t. source. It may be +ve or -ve

Body Effect contd.. MOSFET Contd…

Equation (165) can also be alternately written as

where VTN0 is defined as the zero back-bias (1.e., VBS= 0) threshold voltage, and is given by

Equation (167) states that with the application of a normal back bias (i.e., VBS negative, i.e.,
VSB positive), the threshold voltage for an n-channel MOSFET can be made greater than
VTN0 (i.e., becomes more positive). Now, the threshold voltage for a p-channel MOSFET,
fabricated on a n-type substrate, with a uniform doping concentration of ND cm-3 , can be
straight away given by

with the zero back bias threshold voltage given by

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Body Effect contd.. MOSFET Contd…

Equation (169) states that with the application of a back bias (VSB negative), the threshold
voltage for a p-channel MOSFET decreases below VTP0 (becomes more negative).
The zero back-bias threshold voltage VTN0 for an n-channel MOSFET, as given by Eq. (168)
can be either negative or positive. MOSFET having positive VTN0 are known as enhancement
mode (also referred to as normally off) devices, where the word normally implies that VGS=0.
On the other hand, n-channel MOSFETS having negative VTN0 are known as depletion mode
(also referred to as normally on) devices, since these are on even with VGS = 0, and a negative
VGS with magnitude less than VTN0 is needed to turn these devices off.
Similarly, p-channel devices having negative values of VTPO are known as enhancement mode
devices, and those having positive values of VTPO are known as depletion mode devices. Note
that a depletion mode n-channel MOSFET can he made to operate as an enhancement mode
device by the application of a suitable back bias that would change its threshold voltage to a
positive value. Symbols of diff. MOSFETs are shown below

(a) n-ch enhancement mode MOSFET

(b) p-ch enhancement mode MOSFET
(c) n-ch depletion mode MOSFET
(d) p-ch depletion mode MOSFET

Body Effect contd.. MOSFET Contd…

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Body Effect contd.. MOSFET Contd…

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MOSFET Contd…

Current Voltage Characteristics: Let us consider that there is a vertical field present in
the device due to the applied gate voltage and it forms strong inversion channel. Say this field
is denoted by  (along y-refer to the coordinate system shown in Figure earlier.). Now, in
y
order for the inversion carriers to move along the inversion channel by the drift mechanism,
another voltage is also applied at the drain (VDS), which creates a lateral field along the
channel, and let us denote this field by x (along x). Therefore, the device is under a two-
dimensional electric field, and unless we make some assumptions, simple analysis of this
device is out of question. The assumption that is commonly made is known as the gradual
channel approximation (GCA), in which we state that the rate of change of vertical field is
much larger than the rate of change of lateral field, or, in mathematical terms, The physical
implication of this assumption is that we are neglecting any distortion of the vertical electric
field lines (due to the gate voltage) caused by the lateral field lines (due to the drain voltage).

Another immediate consequence of this assumption is that the channel potential

VC(x) (measured with respect to the source) due to the applied drain voltage can be
assumed to change linearly from the source end to the applied VDS at the drain end.

Current-voltage characteristics contd.. MOSFET Contd…

Now, to evaluate the drain current ID, we assume that the entire current is one-dimensional
(i.e., along the x-direction) and solely contributed by the drift mechanism. Thus, we start with
the one-dimensional point form of Ohm’s law, given by

where Jx is the current density along the x-direction, n is the conductivity of the
channel, and  x is the electric field along the x-direction. Note that in the above
equation, we are using absolute values of Jx, and  x since the direction of the drain
current (ID) is already known a priori. What we are interested in is basically its
magnitude. Hence, we are avoiding carrying unnecessary negative signs in our
derivations. The conductivity of the channel n is given by

where n is the volume concentration of electrons in the inversion channel, and µn is the
mobility of these electrons. The electric field  x , present in the channel is given by

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Current-voltage characteristics contd.. MOSFET Contd…

Now, the drain current ID is given by

where A is the cross-sectional area faced by the carriers moving along the channel and is
given by

where W is the channel width (perpendicular to the screen), and δd is an average thickness of
the inversion layer (the exact computation of δd is quite tedious. The inversion charge per
unit area Q′I can also be expressed as

Combining above equations, the drain current ID can be given by

This expression has to be integrated from x=0 [corresponding to the source end, with
VC(0)=0] to x=L [corresponding to the drain end, with VC(L)=VDS] in order to get the total
drain current ID. Thus,

Current-voltage characteristics contd.. MOSFET Contd…

Since the current ID has to be constant for any x, it can be brought out of the integral on the
left hand side of the equation. In order to evaluate the integral on the right hand side of Eq.
(178), the electron mobility µn, must be known as a function of the channel voltage VC(x);
since, in reality, it should change with respect to x, due to the electron concentration n
changing with x along the channel. Right now, to avoid complexity, we are making another
simplifying assumption that µn is constant. Under this assumption, the integration can be
performed easily with the result

The parameter kN is known as the device transconductance parameter, and is given by

with k′N being known as the process transconductance parameter, and is given by

The parameter (W/L) is known as the aspect ratio of the device.

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Current-voltage characteristics contd.. MOSFET Contd…

N.B.: For p-channel devices, all the voltages appearing in Eq. (179) are negative. Hence, the
magnitude of the drain current flowing through a p-channel device can be easily obtained if
we take the absolute values of all the voltages, and replace kN by kP, where kP is again known
as the device transconductance parameter, but now for p-channel devices, and is given by

where,

where, µP is the hole mobility

Note: For all devices fabricated on the same substrate will have the same oxide
thickness (known as the vertical dimension), thus producing identical values of the
oxide capacitance per unit area C′ox for both n-and p-channel devices. Then, the only
difference between k′N and k′P stems from the difference between the electron and
the hole motilities (µn and µp respectively). Typically, the electron mobility µn is
about 2.5 times that hole mobility µp. Hence, in general, k′N ≈ 2.5 k′P. On the other
hand, different devices fabricated on the same substrate can have different values of
the device transconductance parameter, since the channel length and width (L and
W, respectively-also known as the lateral dimensions) for each device can be
independently controlled by appropriate layout in the masking process.

Current-voltage characteristics contd.. MOSFET Contd…

Let us investigate the characteristic defined by Eq.(179). The dependence of ID on VGS and
VDS is explicit in this equation, whereas its dependence on VBS is implicit through the term
VTN. For small values of VDS, the V2DS term on the right hand side of Eq. (179) can be
neglected and then, the current ID, would change linearly with VDS, for a given value VGS.
However, with an increase in VDS, the effect of the quadratic term in VDS on the drain current
increases, and it puts a restraining effect on the rate of increase of ID with respect to VDS.
Thus, the slope of the ID-VDS characteristic starts to drop and the characteristic becomes non-
linear. Eventually, ID attains its maximum value when VDS becomes exactly equal to (VGS-
VTN), which can be verified easily by taking the derivative of Eq. (179) with respect to VDS
and equating that to zero.

With further increase in VDS. Eq. (179) VGS and VBS constant
predicts that ID would now start to drop from
its maximum value and eventually become
zero. This is shown in Figure right side
where the part of the characteristic beyond
the peak is shown by a dotted line. However, Eq. (179)
note that with increasing VDS it is physically
impossible for the current, after attaining its
peak, to drop to zero.

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Current-voltage characteristics contd.. MOSFET Contd…

In order to get an insight into the actual facts occurring within the device, let us concentrate
on the following. Using the expression for position (x) dependent channel inversion charge
density (per unit area) Q′I as a function of x, the charge density at the drain end, i.e., at x=L,
with corresponding VC(L) becoming equal to VDS, can be written as

When VDS becomes exactly equal to (VGS-VTN), the VGS and VBS constant
channel vanishes. This phenomenon is known as the
pinching off of the channel at the drain end.
Neglecting any higher order effects for the time being,
since the channel gets pinched off at this point, hence,
for a given VGS, no further increase in ID is possible
for any subsequent increase in VDS. i.e., for values of
VDS higher than this, the current remains constant.

This current is given by the value obtained from Eq. (179) by substituting VDS= (VGS-VTN).
This phenomenon is known as current saturation or simply saturation, with the corresponding
saturated drain current ID,sat obtained by substituting VDS = (VGS- VTN) in Eq. (179) as,

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Current-voltage characteristics contd.. MOSFET Contd…

Nonidealities: I-V characteristics of the MOSFET fabricated using present

technology differs from the ideal behaviour. With modern devices having length of
the channel below 50 nm, even below 20 nm/14 nm or even less, the higher order
effects become important. Semi-empirical or empirical model for different effects is
important, to observe the change in characteristics. We shall discuss short channel
effects, narrow channel effects and hot carrier effects as some important effects
present in modern MOSFETS. Under short channel effects again we shall focus on
channel length modulation, carrier velocity saturation, drain-induced barrier
lowering (DIBL) and punch through effects. Most of the modern MOSFETS
exhibit these effects.

Channel length modulation: This

is an effect very similar to the
Early effect discussed in context of
BJTs, where the collector current
is seen to increase with the
collector-to-emitter voltage in the
forward active mode of operation,
due to the effect of the base width
modulation.

Channel length modulation contd.. MOSFET Contd…

Similar effect is exhibited by MOSFETs as well, where the drain current increases with the
drain-to-source voltage in the saturation region. Recall that in MOSFETS under saturation, the
point in the channel which pinches off must have a drain-to-source potential equal to VDS, sat
(Eq. (185). For applied drain-to-source voltage VDS equal to VDS, sat, this pinch-off point is
right at the drain end. For applied VDS greater than VDS, sat however, the pinch-off point starts
to move towards the source, since it is defined as the point where the applied bias equals
VDS,sat. The difference between the applied VDS and VDS, sat [i.e., (VDS- VDS, sat)] drops in the
region between the pinch-off point (P) and the drain shown in Figure below. The length of this
region (denoted by Xd in the figure) is known as the pinched-off region length, the saturation
region length or the drain region length, etc.

Under this condition, the effective

channel length Leff is no longer equal
to the actual channel length L, but is
reduced by the amount of Xd, i.e.,
Leff =L-Xd .
Now, note that if the channel length L
is very long, then the effect of Xd, on
L would be inconsequential, and Leff
would be approximately equal to L
for any VDS.

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Channel length modulation contd.. MOSFET Contd…

However, if L is small to start with, then Xd, may become a significant fraction of it, and, in
that case, Leff would keep on decreasing as VDS is increased beyond VDS, sat. Thus, from the
saturated drain current expression given by Eq. (185), it can be seen that the only change that
needs to be incorporated into this expression, in order to include the channel length
modulation effect, is to replace the channel length term (L) by the effective channel length
(Leff ). The expression for ID can be written as,

However, since Leff is function of VDS, hence ID,sat does not remain constant in ID-
VDS curve. It is shown in the figure next slide.

Channel length modulation contd..

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Where mn*, is the effective

mass of electrons.

Now vd can be expressed as

Carrier velocity saturation contd..

>

Considering both the channel length modulation and carrier velocity saturation effect, the
expression for saturation current can be expressed as,

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Carrier velocity saturation contd..

Based on the model for velocity saturation, a rough

estimate of transit time of carriers to travel the length of
the channel with constant maxm. Velocity can be done.
From that maximum operational frequency can be
predicted as given below.

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Drain Induced Barrier Lowering (DIBL): This effect is primarily exhibited by devices
biased in the subthreshold (or weak inversion) mode of operation. This effect disappears
completely as the device enters the moderate inversion region. The variation of the surface
potential (ѱs) with respect to the channel length is shown in Fig. below for two n-channel
MOSFETs, one having a channel length of 1.0 µm (device A, Fig. right), and the other having
a channel length of 0.2 µm (device B, Fig. left) on the same axis.

Two potential profiles are shown

for each case: one (solid line)
corresponds to VDS=0, and the
other (dotted line) corresponds to
VDS>0. It is also assumed that
VBS= 0. For VDS = 0, the diagrams
correspond to the situation when
the applied gate-to-body voltage
VGB is equal to the flatband
voltage VFB, so that far away
from the source-body and drain-
body junctions, or, more
specifically, near the middle part
of the channel, the surface
potential ѱs, = 0.

DIBL contd..

From this middle region as the source-

body and drain-body junctions are
approached at either end of the channel,
ѱs, starts to increase, and eventually
becomes equal to Vbi at both source and
drain ends, where Vbi is the built-in
potential of the source/drain-body
Junctions.
Also it is to be noted that this change in
ѱs, (i.e., from zero to Vbi) takes place
over a region that is equal depletion
width of the source-body and drain-body
junctions.
Thus, for VDS=0, both the source and drain are sitting at a potential higher than the substrate by
an amount equal to Vbi, and there exists an energy barrier equal to qVbi for electrons belonging
to the source to get injected into the substrate (i.e., the channel region) [note that the energy
profile would be the inverse of the potential profile shown in Figure, due to the negative charge
of electrons]. Since the amount of carrier injection is proportional to the negative exponent of
the barrier height, hence, very few electrons would surmount this barrier and appear in the
channel region. Exactly similar situation would be encountered in drain-channel junction. With
VDS = 0, the structure is at equilibrium, and these two injection components would exactly
cancel each other, with no net current flow through the device.

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DIBL contd..

Under the application of a non-zero VDS,

however, the potential profile along the channel
changes, since now the drain must be at a
potential VDS higher than the source, and at a
potential (Vbi+VDS) higher than the substrate.
Thus, the drain-body Junction effectively gets
reverse biased by an amount equal to the
applied VDS (Since VBS= 0), with the amount of
carrier injection from the drain to the channel
region dropping further. Now, for a device
having a long channel length (device A in Fig.),
the changing potential near the drain region
does not affect the potential profile near the
source at all, thus keeping the
source-channel barrier height in tact at a value equal to qVbi with no change in the amount of carrier
injection from the source to the channel, as compared to the case with VDS = 0. However, it is to be noted
that now there is an imbalance of the two injection components, with the result that a net current
(subthreshold) flows through the device from the drain to the source (with the electrons travelling from the
source to the drain). On the contrary, if the channel length is very small (device B in Fig.), then the
changing potential near the drain region would start to affect the channel potential near the source end, the
exact evaluation of which can be done by performing a two-dimensional electrostatic analysis of the
structure. This is mathematically very tedious. However, it is obvious from Figure that for device B, the
applied drain-to-source potential actually reduces the source-channel potential barrier height, as can be
observed from the enlarged diagram for that region.

DIBL contd..

This reduction in the source-channel potential barrier would exponentially increase the
amount of electron injection from the source to the channel region, thus translating to a large
change in the carrier injection caused by a little change in the barrier height. Comparing this
case with the previous scenario (large channel length device (A) with non-zero VDS), we can
immediately see that a short channel device (B) would have an enhanced subthreshold
current due to the larger amount of injection from the source to the channel region due to an
effective reduction of the source-channel barrier height caused by an applied VDS. This
phenomenon is referred to in the literature as the drain-induced barrier lowering (DIBL)
effect.

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DIBL contd..

Punch Through: Punchthrough is a negative form of device breakdown, and, if not properly
taken care of, can completely destroy the device. Basically, this form of breakdown takes
place when the depletion regions associated with the drain-body and the source-body
junctions touch each other, as shown in Figure. Two forms of such breakdown can occur, one
when the depletion regions touch each other at the surface, which is known as the surface
punchthrough; and the other when the depletion regions touch each other somewhere below
the surface (i.e., in the bulk), and is known as the subsurface (or bulk) punchthrough.

The surface
punchthrough
is an unlikely
phenomenon,
since for a
given gate and
drain voltages,
when the
region under
the gate
near the source side is under depletion, the one near the drain side may be under
accumulation, with almost no depletion width. However, the subsurface (or bulk)
punchthrough is a much more likely phenomenon, if at all punchthrough breakdown does take
place within the device.

Punch through contd..

In cither case, the electric fields associated with the depletion regions [as shown in Fig.]
cancel each other to the first order (since they are oppositely directed), and, as such, two n+
regions (i.e., the source and the drain get connected directly through a very low resistance
region (i.e., the depletion region, which now offers very low resistance due to the cancellation
of the two oppositely directed electric fields) across the entire applied drain-to-source voltage
VDS. The result is a huge current flow through the device, since almost the entire applied VDS
gets dropped in the source and drain regions, which themselves typically have very low
resistances due to their high doping levels. The resulting Joule heating of the device can even
create a total meltdown.

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Hot Carrier Effects These

effects are becoming
increasingly important in
modern MOSFETs having
ultra-small channel lengths
(typically less than 0.2 µm)
and subjected to bias voltages
of the order of 3 V or more.
The small channel length
coupled with high amount of
bias voltage creates a very
high electric field near the
drain in the drain-substrate depletion region. This high field near the drain are quite
problematic for small channel length devices, since this is primarily responsible for the
initiation of the avalanche breakdown of the drain- substrate junction, as well as the
origination of the substrate current and the gate current. Referring to Figure, where a pictorial
representation of the various events occurring in the depletion region near the drain of an n-
channel MOSFET, biased in the saturation region and carrying a finite amount of drain
current, is presented. As per the figure, the electrons are moving in the channel from the source
end to the drain end, and, as they approach the drain, they face an ever increasing electric field,
which peaks right at the drain-body junction. The immediate effect of this electric field is an
acceleration of the carriers, since the force on them increases. Therefore, the carriers start to
increase their speed as well as their kinetic energy as they move down the channel.

Hot carrier effect contd..

If the kinetic energy thus acquired by

any particular electron becomes
greater than the band gap energy of Si
(=1.12 eV at room temperature), then
this electron can collide with an atom
and dislodge an electron from its outer
shell, thus creating an empty state
there. Recall that this phenomenon is
the familiar impact ionization, and the
result is the generation of an electron-
hole pair (EHP).
The electron and hole created by this process would also start to gather energy from the field,
and when this energy becomes greater than the band gap energy of Si, then they too would be
capable of creating further EHPs. Thus, the process repeats itself, and from a single electron, a
large number of carriers (both electrons and holes) are created near the drain. It can be
observed that the electric field in this region would assist in immediate separation of these
generated carriers by exerting forces in opposite directions, such that they do not get a chance
to recombine. In particular, electrons would be accelerated towards the drain terminal, and
holes towards the substrate terminal. Note that these electrons are over and above the ones
that actually constitute the normal drain current, and, thus, the result of this process of impact
ionization is a sudden increase in the drain current. This phenomenon is known as the
avalanche breakdown of the drain-substrate junction.

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Hot carrier effect contd..

What is more interesting is that the holes that get pushed towards the substrate create a
substrate current. The sudden appearance of the substrate current is a tell tale sign that the
drain-substrate junction is undergoing avalanche breakdown. The exact analysis of the
substrate current Isub is pretty tedious, however, an empirical model exists which is seen to
portray the actual behaviour quite accurately, and is given by

where ID is the drain current, Ki is an empirical fitting parameter, having values in the range of
1-3 V-1, VDS is the applied drain-to-source voltage, VDS,sat, saturation drain-to-source voltage,
and Vi is another fitting parameter, with van ranging between 10-30 V.

Using eqn. (194) above, VDS,sat comes out to be 0.31 V (note the reduction from 0.5 V
obtained earlier, a change of 38%).

Problem: Using the transit time model, roughly estimate the maximum frequency of operation fmax for an n-
channel MOSFET having channel length of (i) 1 µm, and (i) 0.1 µm. Assume that the carriers in the channel for
both the devices are travelling with their maximum drift velocity of 1.3 x 107 cm/sec. Comment on the answers.
Solution Simple substitution of values in Eq. (192) gives fmax equal to 0.13 THz and 1.3 THz (T= 1012) for the
channel length equal to 1 µm and 0.1 µm, respectively. These results are absolutely hypothetical for the
reason stated above. MOSFETs are yet to break the GHz barrier, even though intense research is taking place
to push up their maximum operating frequency.