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Lectures 18 19

The document provides an overview of the SRAM cell anatomy, detailing the processes for reading and writing data, including the roles of bit lines and word lines. It discusses the structure of a 6T SRAM cell, emphasizing the importance of cell size, read stability, and writeability. Additionally, it highlights the significance of pre-charging bit lines and managing noise margins for optimal performance in SRAM arrays.

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7 views14 pages

Lectures 18 19

The document provides an overview of the SRAM cell anatomy, detailing the processes for reading and writing data, including the roles of bit lines and word lines. It discusses the structure of a 6T SRAM cell, emphasizing the importance of cell size, read stability, and writeability. Additionally, it highlights the significance of pre-charging bit lines and managing noise margins for optimal performance in SRAM arrays.

Uploaded by

pavanbose19
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Anatomy of the SRAM Cell

Write:
•set bit lines to new data value Read:
•b’ = ~b •set bit lines high
•raise word line to “high” •set word line high
•sets cell to new state •see which bit line goes low
One Row of a memory can contain up to 256 SRAM cells (or even more)
Loading on the Decoder which generated WL (Wordline)
WL0

BL BLB BL BLB BL BLB


One Column of SRAM array – may contain 256 cells (or even more)
BL loading decides the read and write access times
No. of cells (density) Versus Latency
WL0

WL1

BL BLB BL BLB BL BLB


6T SRAM Cell
• Cell size accounts for most of array
size
• Reduce cell size at cost of
complexity/margins
• 6T SRAM Cell
• Read:
• Precharge bit, bit_b
• Raise wordline
• Write:
• Drive data onto bit, bit_b
• Raise wordline
SRAM Read bit bit_b

Precharge both bitlines high word


P1 P2
Then turn on wordline N2 N4

One of the two bitlines will A A_b


N1 N3
◦ be pulled down by the cell

Ex: A = 0, A_b = 1 A_b bit_b


◦ bit discharges, bit_b stays high
1.5
◦ But A bumps up slightly
1.0
Read stability word bit

◦ A must not flip 0.5

◦ N1 >> N2 A
0.0
0 100 200 300 400 500 600
time (ps)
bit bit_b
word
P1 P2
N2 N4
A A_b
N1 N3

SRAM Read, 0 is stored in the cell


SRAM Write
bit bit_b

Drive one bitline high, other low word


P1 P2
Then turn on wordline N2 N4
A A_b
Bitlines overpower cell N1 N3

Ex: A = 0, A_b = 1, bit = 1, bit_b = 0


A_b
◦ Force A_b low, then A rises high
1.5 A
Writability bit_b
◦ Must overpower feedback 1.0

◦ P2 << N4 to force A_b low,


0.5
word
◦ N1 turns off, P1 turns on,
◦ raise A high as desired 0.0
0 100 200 300 400 500 600 700
time (ps)
SRAM Sizing
High bitlines must not overpower inverters during reads
But low bitlines must write new value into cell
bit bit_b
word
weak
med med
A A_b
strong
Pre-charge
Equalize bitlines
to minimize
 voltage difference
when using sense
amplifiers
bit bit_b
Write Driver
Sense Amplifier
Static Noise Margin
Read Noise Margin Write Noise Margin

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