Introduction to using the Controller Area Network (CAN) module (NI 985x) with CompactRIO

Publish Date: Oct 24, 2014

Overview
National Instruments CompactRIO CAN modules (NI 9852, NI 9853) work with LabVIEW FPGA to make the most powerful, flexible, and reliable CAN solution for difficult applications such as
Hardware-in-the-Loop (HIL), Rapid Control Prototyping (RCP), and Rest-of-bus (Restbus) simulation.
CompactRIO's rugged temperature and physical ratings make it ideal for both in-vehicle and stationary applications in demanding environments where traditional CAN solutions may fail. In addition
to demanding CAN applications, CompactRIO CAN is also ideal for traditional CAN applicatiosn including bus monitoring, logging, and CAN bus participation.
This tutorial covers setting up a CompactRIO Project with the NI 9853 or NI 9852 module, developing FPGA and Real-Time Host VIs, and background information about CAN frames and
channels.

Table of Contents
1. Equipment Required
2. Application Architecture
3. Setting up a CompactRIO/FPGA Project
4. Setting the CAN Baud Rate
5. Developing a FPGA VI
6. Developing a Real-Time Host VI and Transferring CAN Data from FPGA to Real-Time
7. CAN Frames Channel Conversion Library
8. Appendix
9. Additional Links

1. Equipment Required
This tutorial assumes you have the following equipment and software available:
1. CompactRIO Controller (cRIO-90xx) and Chassis (cRIO-91xx) -or- CompactRIO Integrated System.
2. NI 9853 High Speed CAN module or NI 9852 Low Speed CAN module.
3. LabVIEW Professional Development Environment 8.x or newer
4. LabVIEW FPGA Module 8.x or newer
5. LabVIEW RT Module 8.x or newer
6. Latest version of NI-RIO driver software
2. Application Architecture

The reference architecture for this tutorial is shown above. For this application on CompactRIO, we will need two VIs - a Real Time VI to run on the CompactRIO processor, and a LabVIEW FPGA
VI to program the FPGA to which CompactRIO CAN module interfaces.
The LabVIEW for Windows Host VI contains the user interface for your real-time system. It runs on the CompantRIO host in the application.
You will use the LabVIEW Real-Time Module for adding deterministic floating point processing and control algorithms on a dedicated processor. The LabVIEW Real-Time application is divided
into two parts: the time-critical loop and the normal priority loop. These two loops are contained within separate VIs. Any code that must execute deterministically is placed in the time-critical loop
with all other code in the normal priority loop. In most programs, the time-critical loop handles all control tasks and/or safety monitoring, and the normal priority loop handles all communication and
datalogging.
The LabVIEW FPGA VI is used for implementing custom I/O or ultra high-speed control. Since your LabVIEW code is executing directly in hardware, you are able to achieve hardware-level
(nano-second) determinism and performance up to 150kHz. The LabVIEW FPGA module is found between the CAN module and the Real-Time Module. Because we can control the CAN
communication from the FPGA module, we have unprecedented performance and flexibility.
We will begin the tutorial by programming the FPGA.
3. Setting up a CompactRIO/FPGA Project
1. Ensure your CompactRIO is accessible from Measurement and Automation Explorer.
2. Open LabVIEW and launch the FPGA Project Wizard.
1. Select FPGA Project from the Targets drop down menu on the LabVIEW Getting Started Window and click Go.

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2. In the FPGA Project Wizard dialog box, select CompactRIO Reconfigurable Embedded System as the desired project type. Click Next > to proceed.

3. In the next window, you have two options.

Option 1 (LabVIEW 8.5 and later): The Discover existing system option automatically detects a connected FPGA target and all connected modules. If we actually had a CompactRIO or other
FPGA target connected to this machine, you could select the Discover existing system option.
Option 2 (LabVIEW 8 - 8.2): Select a target and modules manually. Select the Create new system >> click Next >.
1. In the Select a controller by type dialog, select the controller module for your system and click Next >.
2. In the Select an FPGA target by type dialog, select the FPGA target for your system and click Next >.
3. In the Configure C Series Modules dialog, select the C Series Module and click the arrow to insert the C Series Module module into <Slot 1> of the Module configuration.
4. Repeat step c. for the remaining C Series Modules for slots 2, 3, and 4 respectively.

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 1. After you have entered all the C Series Modules continue by clicking Next >.
4. The next dialog box generates a preview of a LabVIEW project with your CompactRIO Real-Time target, FPGA target, and all the C Series I/O modules configured. Make sure the Launch
FPGA Wizard when finished check box is unchecked.
Click Finish to create the LabVIEW Project.
Your LabVIEW Project is used to manage and configure all the needed resources for FPGA devices such as CompactRIO Modules, I/O, clocks, FIFOs and VIs. When using a LabVIEW Real-Time
platform with a LabVIEW FPGA device, you will need to add the following resources in this order to the project:
1. Real-Time target (CompactRIO)
2. FPGA Target ( CompactRIO backplane or R Series device)
3. CompactRIO Expansion Chassis (R Series only)
4. CompactRIO Modules

(The Project Explorer window with a FPGA project loaded)

4. Setting the CAN Baud Rate
Now that the project is set up, we can set the baud rate of the module. For most applications, this will not change, however it is possible to programmatically change the baud rate of the CAN
modules without recompiling the FPGA. Refer to the LabVIEW help for how to do this.
1. Globally Setting the Baud Rate: This option is used when the baud rate or termination is pre-determined and will not change while the program is running.
In the project, right click on your C Series Module and select Properties.
In the C Series Module Properties dialog box:
1. Select the CAN0 or CAN1 tab and select the desired baud rate from the Baud Rate list box.
2. Click OK.

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With the modules configured, we can now program the LabVIEW FPGA VI.
5. Developing a FPGA VI
1. First, create a new VI. In the Project Explorer window, right click on FPGA Target and select New >> VI.
2. VIs under the FPGA target inherit the FPGA I/O function palette and the FPGA Math & Analysis Palette. Use the functions in these palettes to interact with the FPGA programmatically.

2. To read and write from the CAN module, use the I/O Node (Functions Palette » FPGA I/O). The I/O node will send or receive one CAN frame each time it is called. The NI-985x modules has
an internal write buffer of 17 frames that will queue messages between calls to the I/O node. The I/O node will not return a value until a frame arrives. You have the option of returning data from
the I/O Node either as a cluster (default) or and array of bytes. The node defaults to cluster, you can change it by right clicking on the node and selecting Properties. The byte array output
facilitates easy usage of the DMA FIFO node for sending data to the host.
I/O Nodes can also be used for writing frame out to the CAN bus. Change the node to a write node by right clicking the node and selecting "Change to Write". Read and write nodes can be used
on the same port. It is recommended to only use one CAN read node per port. Multiple write nodes can be used per port; the I/O node will automatically prevent any conflicts between multiple
nodes.

The example above shows reading CAN frames from the I/O node and sending the frames to the host PC through DMA FIFOs. Refer to the LabVIEW help for more information about DMA FIFOs .
3. When you have finished building the FPGA VI, you will need to compile the code. The compile process is initiated by pressing the Run button in the VI.
The Build process will always compile the top-level VI in the project. You can only have one top level VI at a time. The time required to compile can take anywhere from minutes to hours depending
on the complexity of your VI. You are able to program your Real-Time VI while the FPGA VI is compiling.
Every time you change your LabVIEW FPGA code keep in mind that, the code must be recompiled.

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6. Developing a Real-Time Host VI and Transferring CAN Data from FPGA to Real-Time
Basic VI Setup

Accessing data from an FPGA VI follows the traditional Open-Read/Write-Close model.

1. First create a new VI. In the Project Explorer window, right click on your CompactRIO module and select New » VI
2. VIs under the FPGA target inherit the FPGA I/O function palette and the FPGA Math & Analysis Palette. Use the functions in these palettes to interact with the FPGA programmatically.
Invoke Method: Invoked method or action from host VI

Open FPGA VI Reference: Opens a reference to the FPGA VI or bitfile and FPGA target you select in the shortcut menu or that you specify with the resource name input. You must open a
reference to the FPGA target before you can communicate between the host VI and the FPGA VI.
Close FPGA VI Reference: Stops and resets the FPGA VI running on the FPGA target and closes the references to the VI.
3. The VIs needed to control and monitor data passed through the FPGA VI can be found at FPGA Interface » Read/Write Control. Refer to the LabVIEW FPGA Module Training (FPGA I/O
Section) for more information on accessing FPGA front panel controls. For accessing the FPGA VI created in the previous example, we will use DMA FIFOs.

4. The best method for bringing CAN data from the FPGA to the LabVIEW host is through DMA FIFOs. See the LabVIEW help for more information about DMA FIFOs . The example above shows
reading CAN frame data one frame at a time from the DMA FIFO. For maximum performance, you can increase the number of elements read to a higher multiple of 6, reducing the number of
accesses to the DMA fifo and eliminating overhead. Once the frames are read in, they need to be converted in order to be useful on the host. One useful method of doing this is with the CAN
Frame to Channel Converison Library.
5. Deploy Real-Time Host VI: When the VI is completed, press Run button and the VI will be deployed and run on the CompactRIO.
7. CAN Frames Channel Conversion Library
Conversion between CAN Frames and Channels:

The core unit of data transfer on a CAN bus is the frame. A frame contains 8 bytes of data, header, timestamp, and error information. Processing, analyzing, and storing data on the frame level is
the most powerful and flexible method, however it is more complicated. Most CAN data represents real world values such as voltages, forces, and speeds. Since CAN raw data frames always
have to be in byte units, the data must be scaled and offset to change the data to real world units. CAN data in real-world units are known as Channels.
Converting many different CAN data frames to a variety of channels can be tedious to program for large channel counts. This is where the CAN Frame to Channel Conversion Library becomes
useful. This library is a collection of VIs for fast conversion of CAN frames to scaled channel information. It is optimized for with Windows PCs, Pharlap (90xx) Real-Time controllers, and VxWorks
(91xx) Real-Time controllers. This library uses significantly less CPU than converting frames with the NI-CAN driver.

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When installing the CAN Frame Channel Conversion Library, there are multiple examples that are included in the .zip file. An excellent reference is be the included
VxWorks_Basic_Input_Output_DMA example. It is a more complete example that describes a full implementation of the library and is a great starting point for a project.
The path to find this example from within the .zip file is:
C ANFrameChannelConversionLibrary\Examples\ 90xx_VxWorks\VxWorks_Basic_Input_Output_DMA
If you have a CAN database ( .dbc or .ncd ) file, the channel configuration has already been created using a tool such as Vector’s CANdb Editor. You can use each signal name in the CAN
database as a channel name in the Frame to Channel Conversion Library..
Conclusions: You have now created a LabVIEW Controller Area Network (CAN) with CompactRIO project. You have stepped through the setup of each of the major components in the
CompactRIO project. These include setting up the CompactRIO project, and getting started with the FPGA and Real-Time Host VIs. Also you were introduced to the CAN Frame Channel
Conversion Library which will be useful when developing applications.

There are many additional links that go more in depth on related topics covered in this introduction. Also there are two examples attached to this introduction. These examples require the proper
setup and devices. They should also be used as references on getting started with setup and initial programming of the FPGA and Real-Time VIs.

8. Appendix
Programmatically Setting the Baud Rate and Termination: This option is used when the program needs to change the baud rate or termination while it is running.
In LabVIEW, you can use the FPGA I/O property node for the specified CAN port with the property Bit Timing selected to change the Baud Rate.
Note: You must stop each CAN port before changing timing or disabling Auto Start (preferred). An error will occur if this is not done properly.
The correct usage of the FPGA I/O property node is to include an FPGA I/O Method Node with the Stop method selected before writing to the FPGA Property Node, then use another FPGA
I/O Method Node with the Start method selected right afterwards. This will guarantee that the CAN port has been stopped before changing the timing. The termination can be changed in a
similar manner.

9. Additional Links
Using LabVIEW for Rapid Control Prototyping and Hardware-in-the-Loop Simulation
HIL (Hardware-in-the-Loop) Evaluation of Vehicle Components with LabVIEW Real-Time and CarSim/TruckSim
CAN Frame Channel Conversion Library
Frame Channel Conversion Library User Guide
Controller Area Network (CAN) Overview
Proper Termination for NI-CAN Hardware
Symptoms of Improper CAN Termination

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