2024-12-26

Digital Design

L10: Logic Synthesis with Verilog HDL

Duong Ngoc Phap, Ph.D

Faculty of Computer Engineering and Electronics

December 26, 2024

Content

Logic Synthesis
Impact of logic synthesis
Verilog HDL Synthesis
Synthesis design flow, Verification of Gate-Level
netlist

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Logic Synthesis with Verilog HDL

 Define logic synthesis and explain the benefits of logic
synthesis.
 Identify Verilog HDL constructs and operators accepted in
logic synthesis. Understand how the logic synthesis tool
interprets these constructs.
 Explain a typical design flow, using logic synthesis. Describe
the components in the logic synthesis-based design flow.
 Describe verification of the gate-level netlist produced by logic
synthesis.
 Understand techniques for writing efficient RTL descriptions.
 Describe partitioning techniques to help logic synthesis
provide the optimal gate-level netlist.
 Design combinational and sequential circuits, using logic
synthesis.

Logic Synthesis with Verilog HDL

 Define logic synthesis and explain the benefits of logic
synthesis.
 Identify Verilog HDL constructs and operators accepted in
logic synthesis. Understand how the logic synthesis tool
interprets these constructs.
 Explain a typical design flow, using logic synthesis. Describe
the components in the logic synthesis-based design flow.
 Describe verification of the gate-level netlist produced by logic
synthesis.
 Understand techniques for writing efficient RTL descriptions.
 Describe partitioning techniques to help logic synthesis
provide the optimal gate-level netlist.
 Design combinational and sequential circuits, using logic
synthesis.

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What Is Logic Synthesis?

 Simply speaking, logic synthesis is the process of
converting a high-level description of the design into an
optimized gate-level representation, given a standard
cell library and certain design constraints.
 A standard cell library can have simple cells, such as
basic logic gates like and, or, and nor, or macro cells,
such as adders, muxes, and special flip-flops.
 A standard cell library is also known as the technology
library.
 Logic synthesis always existed even in the days of
schematic gate-level design, but it was always done
inside the designer's mind.

 The designer would first understand the architectural

description. Then he would consider design constraints
such as timing, area, testability, and power.
 The designer would partition the design into high-level
blocks, draw them on a piece of paper or a computer
terminal, and describe the functionality of the circuit. This
was the high-level description.
 Finally, each block would be implemented on a hand-
drawn schematic, using the cells available in the
standard cell library.
 The last step was the most complex process in the
design flow and required several time-consuming design
iterations before an optimized gate-level representation
that met all design constraints was obtained.

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Verilog HDL Synthesis

 The term RTL(Register transfer level ) is used for an HDL
description style that utilizes a combination of data flow and
behavioral constructs.
 Logic synthesis tools take the register transfer-level HDL
description and convert it to an optimized gate-level netlist.
 Verilog and VHDL are the two most popular HDLs used to
describe the functionality at the RTL level. In this chapter,
we discuss RTL-based logic synthesis with Verilog HDL.
 Behavioral synthesis tools that convert a behavioral
description into an RTL description are slowly evolving, but
RTL-based synthesis is currently the most popular design
method. Thus, we will address only RTL-based synthesis in
this chapter

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Verilog Constructs

Verilog Operators
 Almost all operators in Verilog are allowed for logic
synthesis.
 Table 14-2 is a list of the operators allowed. Only
operators such as === and !== that are related to x and z
are not allowed, because equality with x and z does not
have much meaning in logic synthesis.
 While writing expressions, it is recommended that you
use parentheses to group logic the way you want it to
appear.
 If you rely on operator precedence, logic synthesis tools
might produce an undesirable logic structure.

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Interpretation of a Few Verilog

Constructs
 Having described the basic Verilog constructs, let us try to
understand how logic synthesis tools frequently interpret
these constructs and translate them to logic gates.
 Assign statement
 The assign construct is the most fundamental construct used
to describe combinational logic at an RTL level. Given below
is a logic expression that uses the assign statement.
 assign out = (a & b) | c;
 This will frequently translate to the following gate-level
representation:

 If a, b, c, and out are 2-bit vectors [1:0], then

the above assign statement will frequently
translate to two identical circuits for each
bit.

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 If arithmetic operators are used, each arithmetic operator is

implemented in terms of arithmetic hardware blocks available
to the logic synthesis tool. A 1-bit full adder is implemented
below.
 assign {c_out, sum} = a + b + c_in;
 Assuming that the 1-bit full adder is available internally in the
logic synthesis tool, the above assign statement is often
interpreted by logic synthesis tools as follows:

 If a multiple-bit adder is synthesized, the synthesis tool

will perform optimization and the designer might get a
result that looks different from the above figure.
 If a conditional operator ? is used, a multiplexer circuit
is inferred.
 assign out = (s) ? i1 : i0;
 It frequently translates to the gate-level representation
shown in Figure 14-3.

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 The if-else statement

 Single if-else statements translate to multiplexers where
the control signal is the signal or variable in the if clause.
 if(s)
 out = i1;
 else
 out = i0;
 The above statement will frequently translate to the gate-
level description shown in Figure 14-3. In general,
 multiple if-else-if statements do not synthesize to large
multiplexers

 The case statement

 The case statement also can used to infer multiplexers.
The above multiplexer would have been inferred from
the
 following description that uses case statements:
 case (s)
 1'b0 : out = i0;
 1'b1 : out = i1;
 endcase
 Large case statements may be used to infer large
multiplexers.

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 for loops
 The for loops can be used to build cascaded
combinational logic. For example, the following for loop
builds an
 8-bit full adder:
 c = c_in;
 for(i=0; i <=7; i = i + 1)
 {c, sum[i]} = a[i] + b[i] + c; // builds an 8-bit ripple adder
 c_out = c;

 The always statement

 The always statement can be used to infer sequential and
combinational logic.
 For sequential logic, the always statement must be
controlled by the change in the value of a clock signal clk.
 always @(posedge clk)
 q <= d;
 This is inferred as a positive edge-triggered D-flipflop with d
as input, q as output, and clk as the clocking signal.
 Similarly, the following Verilog description creates a level-
sensitive latch:
 always @(clk or d)
 if (clk)
 q <= d;

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Synthesis Design Flow-RTL to Gates

An Example of RTL-to-Gates
 Design specification
 A magnitude comparator checks if one number is greater
than, equal to, or less than another number. Design a 4-
 bit magnitude comparator IC chip that has the following
specifications:
 The name of the design is magnitude_comparator
 Inputs A and B are 4-bit inputs. No x or z values will appear
on A and B inputs
 Output A_gt_B is true if A is greater than B
 Output A_lt_B is true if A is less than B
 Output A_eq_B is true if A is equal to B
 The magnitude comparator circuit must be as fast as possible.
Area can be compromised for speed.

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 RTL description
 The RTL description that describes the magnitude comparator
is shown in Example 14-1. This is a technology independent
description. The designer does not have to worry about the
target technology at this point.
 Example 14-1. RTL for Magnitude Comparator
 //Module magnitude comparator
 module magnitude_comparator(A_gt_B, A_lt_B, A_eq_B, A,
B);//Comparison output
 output A_gt_B, A_lt_B, A_eq_B;
 //4-bits numbers input
 input [3:0] A, B;
 assign A_gt_B = (A > B); //A greater than B
 assign A_lt_B = (A < B); //A less than B
 assign A_eq_B = (A == B); //A equal to B
 endmodule

Reference / Text Book Details

Sl.No
Title of Book Author Publication Edition
.

Verilog HDL: A Guide to Pearson

1 Digital Design and Synthesis Samir Palnitkar 2nd
Education

VHDL for Programmable PHI/Pearson

2 Logic Kevin Skahill 2nd
education
Springer
Donald E.
The Verilog Hardware Science+Busin
3 Thomas, Philip 5th
Description Language ess Media,
R. Moorby
LLC
Advanced Digital Design with Pearson
4 Michael D. Ciletti 2nd
the Verilog HDL (Prentice Hall)
Padmanabhan,
5 Design through Verilog HDL Wiley Latest
Tripura Sundari

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Q&A

December 26, 2024

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