Gate-Level Minimization

Chapter 3
 Chapter Objectives
 Know how to derive and simplify a Karnaugh map for
Boolean function of 2,3, and 4 variables.
 Know how to derive the prime implicants of a Boolean
function.
 Know how to obtain the sum of products and the product
of sums forms of a Boolean function directly from its
Karnaugh map.
 Know how to create the Karnaugh map of a Boolean
function from its truth table.
 Know how to use don’t care conditions to simplify a
Boolean function.

Gate-Level Minimization 2-2

 Chapter Objectives
 Know how to form a two-level NAND and a two-level
NOR implementation of a Boolean function.
 Know how to declare a Verilog module or a VHDL entity-
architecture for a combinational logic circuit.
 For a given logic diagram of a combinational circuit,
know how to write a structural model of the circuit using
(a) Verilog predefined primitives or (b) user-defined
VHDL components.
 Given a test bench, know how to draw the waveform of
an input signal to the unit under test.

Gate-Level Minimization 2-3

3-1 Introduction
 Gate-level minimization is the design task of
finding an optimal gate-level implementation
of Boolean functions describing a digital
circuit.
 The chapter will also introduce the role and
use of hardware description languages in
modern logic design methodology.

It will be assumed that the simplest algebraic

expression is one that has a minimum number of
terms with the smallest possible number
of literals in each term.

Gate-Level Minimization 3-4

3-2 The Map Method
 The complexity of the digital logic gates
 the complexity of the algebraic expression
 Logic minimization
 algebraic approaches: lack specific rules
 the Karnaugh map (or K-map)
 a simple straight forward procedure
 a pictorial form of a truth table
 applicable if the # of variables < 7
 A diagram made up of squares
 each square represents one minterm

Gate-Level Minimization 3-5

 Boolean function
 sum of minterms
 sum of products (or product of sum) in the simplest
form
 a minimum number of terms
 a minimum number of literals
 The simplified expression may not be unique

Gate-Level Minimization 3-6

 Two-Variable Map
 A two-variable map
 four minterms
 x' = row 0; x = row 1
 y' = column 0;
y = column 1
 a truth table in square
diagram
 xy
 x+y =

Gate-Level Minimization 3-7

 Three-variable map
 eight minterms
 the Gray code sequence
 any two adjacent squares in the map differ by only
on variable
 primed in one square and unprimed in the other
 e.g. m5 and m7 can be simplified
 m5+ m7 = xy'z + xyz = xz (y'+y) = xz

Gate-Level Minimization 3-8

3-3 Four-Variable Map
 The map
 16 minterms
 combinations of 2, 4, 8, and 16 adjacent squares

Gate-Level Minimization 3-9

 Prime Implicants
 all the minterms are covered
 minimize the number of terms
 a prime implicant: a product term obtained by
combining the maximum possible number of
adjacent squares (combining all possible
maximum numbers of squares)
 essential: a minterm is covered by only one prime
implicant
 the essential P.I. must be included

Gate-Level Minimization 3-10

 Consider F ( A, B, C , D ) = ∑ (0, 2,3,5,7,8,9,10,11,13,15)
 the simplified expression may not be unique
 F = BD+B'D'+CD+AD = BD+B'D'+CD+AB′
= BD+B'D'+B'C+AD = BD+B'D'+B'C+AB'

Gate-Level Minimization 3-11

 3-4 Five-Variable Map
 Map for more than four variables becomes
complicated
 five-variable map: two four-variable map (one on
the top of the other)

補充圖 Gate-Level Minimization 3-12

3-4 Product of Sums Simplification
 Approach #1
 Simplified F' in the form of sum of products
 Apply DeMorgan's theorem F = (F')'
 F': sum of products => F: product of sums
 Approach #2: duality
 combinations of maxterms (it was minterms)
 M0M1 = (A+B+C+D)(A+B+C+D')
= (A+B+C)+(DD') CD
= A+B+C AB 00 01 11 10
00 M0 M1 M3 M2
01 M4 M5 M7 M6
11 M12 M13 M15 M14
10 M8 M9 M11 M10
Gate-Level Minimization 3-13
  Consider the function defined in Table 3.1.

In sum-of-minterm:

F ( x, y , z ) = ∑ (1,3, 4,6)

In sum-of-maxterm:

F ′( x, y , z ) = Π (0, 2,5,7)

Taking the complement of F′

F ( x, y , z ) = ( x′ + z′)( x + z )

Gate-Level Minimization 3-14

  Consider the function defined in Table 3.1.

Combine the 1’s:

F ( x, y , z ) = x′z + xz′
Combine the 0’s :
F ( x, y , z ) = xz + x′z′

Gate-Level Minimization 3-15

3-5 Don't-Care Conditions
 The value of a function is not specified for
certain combinations of variables
 BCD; 1010-1111: don't care
 The don't care conditions can be utilized in
logic minimization
 can be implemented as 0 or 1
 Example 3-8
 F (w,x,y,z) = Σ(1,3,7,11,15)
 d(w,x,y,z) = Σ(0,2,5)

Gate-Level Minimization 3-16

  Figure 3.15(a)：F = yz + w'x'
 Figure 3.15(b)：F = yz + w'z
 F = Σ(0,1,2,3,7,11,15) ; F = Σ(1,3,5,7,11,15)
 either expression is acceptable

 Also apply to products of sum

Gate-Level Minimization 3-17
3-6 NAND and NOR Implementation
 NAND gate is a universal gate
 can implement any digital system

Gate-Level Minimization 3-18

 Two graphic symbols for a NAND gate

Gate-Level Minimization 3-19

Two-level Implementation
 two-level logic
 NAND-NAND = sum of products
 Example: F = AB+CD
 F = ((AB)' (CD)' )' =AB+CD

Gate-Level Minimization 3-20

 The procedure
 simplified in the form of sum of products
 a NAND gate for each product term; the inputs to
each NAND gate are the literals of the term
 a single NAND gate for the second sum term
 A single literal requires an inverter in the first level

Gate-Level Minimization 3-21

Multilevel NAND Circuits
 Boolean function implementation
 AND-OR logic => NAND-NAND logic
 AND => NAND + inverter
 OR: inverter + OR = NAND

Gate-Level Minimization 3-22

NAND Implementation

Gate-Level Minimization 3-23

NOR Implementation
 NOR function is the dual of NAND function
 The NOR gate is also universal

Gate-Level Minimization 3-24

  Two graphic symbols for a NOR gate

Example: F = (A + B)(C + D)E

Gate-Level Minimization 3-25

Example: F = (AB′ +A′B)(C + D′)

Gate-Level Minimization 3-26

 3-7 Other Two-level Implementations
 Wired logic
 a wire connection between the outputs of two
gates
 open-collector TTL NAND gates: wired-AND logic
 the NOR output of ECL gates: wired-OR logic
F = ( AB )′ ⋅ (CD )′ = ( AB + CD )′ = ( A′ + B′)(C ′ + D′) AND-OR-INVERT function
F = ( A + B )′ + (C + D )′ = [( A + B )(C + D )]′ OR-AND-INVERT function

Gate-Level Minimization 3-27

 Nondegenerate Forms
 16 possible combinations of two-level forms
 eight of them: degenerate forms = a single operation
 The eight nondegenerate forms
 AND-OR, OR-AND, NAND-NAND, NOR-NOR, NOR-OR,
NAND-AND, OR-AND, AND-OR
 AND-OR and NAND-NAND = sum of products
 OR-AND and NOR-NOR = product of sums
 NOR-OR, NAND-AND, OR-AND, AND-OR = ?

Gate-Level Minimization 3-28

AND-OR-Invert Implementation
 AND-OR-INVERT (AOI) Implementation
 NAND-AND = AND-NOR = AOI
 F = (AB+CD+E)'
 F' = AB+CD+E(sum of products)

 simplify F' in sum of products Gate-Level Minimization 3-29

 OR-AND-INVERT (OAI) Implementation
 OR-NAND = NOR-OR = OAI
 F = ((A+B)(C+D)E)'
 F' = (A+B)(C+D)E (product of sums)

 simplified F' in products of sum Gate-Level Minimization 3-30

Tabular Summary and Examples

Gate-Level Minimization 3-31

Gate-Level Minimization 3-32
3-8 Exclusive-OR Function
 Exclusive-OR (XOR)
 x⊕y = xy'+x'y
 Exclusive-NOR (XNOR)
 (x⊕y)' = xy + x'y'
 Some identities
 x⊕0 = x
 x⊕1 = x'
 x⊕x = 0
 x⊕x' = 1
 x⊕y' = (x⊕y)'
 x'⊕y = (x⊕y)'
 Commutative and associative
 A⊕B = B⊕A
 (A⊕B) ⊕C = A⊕ (B⊕C) = A⊕B⊕C

Gate-Level Minimization 3-33

 Implementations
 (x'+y')x + (x'+y')y = xy'+x'y = x⊕y

Gate-Level Minimization 3-34

Odd function
 A⊕B⊕C = (AB'+A'B)C' +(AB+A'B')C
= AB'C'+A'BC'+ABC+A'B'C
= Σ(1,2,4,7)
 an odd number of 1's

Gate-Level Minimization 3-35

 Logic diagram of odd and even functions

Gate-Level Minimization 3-36

 Four-variable Exclusive-OR function
 A⊕B⊕C⊕D = (AB’+A’B)⊕(CD’+C’D)
= (AB’+A’B)(CD+C’D’)+(AB+A’B’)(CD’+C’D)

Gate-Level Minimization 3-37

Parity Generation and Checking
 Parity Generation and Checking
 a parity bit: P = x⊕y⊕z
 parity check: C = x⊕y⊕z⊕P
 C=1: an odd number of data bit error
 C=0: correct or an ever # of data bit error

Gate-Level Minimization 3-38

Parity Generation and Checking

Gate-Level Minimization 3-39

Parity Generation and Checking

Gate-Level Minimization 3-40

3.9 Hardware Description Language (HDL)
 Describe the design of digital systems in a
textual form
 hardware structure
 function/behavior
 Timing
 VHDL and Verilog HDL

Gate-Level Minimization 3-41

 A hardware description language (HDL) is a
computer-based language that describes the
hardware of digital systems in a textual form.
 As a documentation language, an HDL is
used to represent and document digital
systems in a form that can be read by both
humans and computers and is suitable as an
exchange language between designers.
 Design entry creates an HDL-based
description of the functionality that is to be
implemented in hardware.

Gate-Level Minimization 3-42

 Logic simulation displays the behavior of a
digital system through the use of a computer.
 The stimulus (i.e., the logic values of the
inputs to a circuit) that tests the functionality
of the design is called a test bench.
 Logic synthesis is the process of deriving a
list of physical components and their
interconnections (called a netlist ) from the
model of a digital system described in an
HDL.

Gate-Level Minimization 3-43

 Timing verification confirms that the
fabricated, integrated circuit will operate at a
specified speed.
 In VLSI circuit design, fault simulation
compares the behavior of an ideal circuit with
the behavior of a circuit that contains a
process-induced flaw.

Gate-Level Minimization 3-44

Verilog—Design Encapsulation
 Examples of keywords
 Module
 Endmodule
 Input
 Output
 Wire
 And
 Or
 Not

Gate-Level Minimization 3-45

Verilog Example

[註：上列程式碼的 ” // | is logical “OR”

operator”，應修改為” // || is the logical “OR”
operator” ；另外，” // & is the logical “AND”
operator” ，應修改為 “// && is the logical “AND”
operator”。]
Gate-Level Minimization 2-46
VHDL—Design Encapsulation
 Entity
 Provides a name by which a design can be
identified
 Specifies the interface of the design with its

environment
 Architecture
 Describes how the outputs of an entity are formed from its
inputs

Gate-Level Minimization 3-47

VHDL Example

Figure 3.36
Entity-Architecture pair for or_and_vhdl.

Gate-Level Minimization 2-48

Verilog Example

Figure 3.37
Schematic for and_or_prop_delay.

Gate-Level Minimization 2-49

 Gate Delays
Example: timescale directive
‘timescale 1 ns/100ps

Gate-Level Minimization 3-50

 Gate Delays

Figure 3.38
Simulation waveforms of and_or_prop_delay.

Gate-Level Minimization 3-51

 VHDL Example

Figure 3.39
Entity-architecture for a structural model of and_or_prop_delay_vhdl.

Gate-Level Minimization 2-52

 VHDL Packages, Libraries, and Logic Systems

 A package provides a repository for declarations that may

be common to several design units.
 A package may have an optional body, which could
contain declarations of components, as well as functions,
and procedures supporting behavioral models.
 A package statement has the syntax:

Gate-Level Minimization 3-53

VHDL Packages, Libraries, and Logic Systems

Table 3.6
Logic Symbols of the IEEE_std_logic_1164 Package.

Gate-Level Minimization 3-54

Truth Tables In HDLs
 Verilog—user-defined primitives
 and, or, etc., are referred to as system primitives
 User-defined primitives (UDPs) do not use the

keyword pair module… endmodule; instead with

the keyword paid primitive…endprimitive
 Verilog Example 3.4 defines a UDP with a truth table
 A UDP is declared with the keyword

primitive ,followed by a name and port list

 There can be only one output, and it must be

listed in the port list and declared with keyword

output

Gate-Level Minimization 3-55

Verilog Example

Figure 3.40
Schematic for Circuit with_UDP_02467.

Gate-Level Minimization 2-56