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APB Protocol - Part1

The APB protocol is a low-cost, low-power interface designed for connecting peripherals and memory components to a CPU in SoC designs, characterized by its non-pipelined, synchronous operation. It facilitates communication with low bandwidth peripherals and operates through a series of defined states including Idle, Setup, and Access, with specific signals governing the data transfer process. Key signals include PCLK, PRESETn, PADDR, and PREADY, which manage the timing and control of data transactions.

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42 views

APB Protocol - Part1

The APB protocol is a low-cost, low-power interface designed for connecting peripherals and memory components to a CPU in SoC designs, characterized by its non-pipelined, synchronous operation. It facilitates communication with low bandwidth peripherals and operates through a series of defined states including Idle, Setup, and Access, with specific signals governing the data transfer process. Key signals include PCLK, PRESETn, PADDR, and PREADY, which manage the timing and control of data transactions.

Uploaded by

kollasunnykumar123
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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APB PROTOCOL

PART - 1
KOTHA VANI
INDEX
◦ Introduction
◦ APB Topology
◦ Block Diagram
◦ Signal Description
◦ Protection Unit Support
◦ Operating States
Introduction
◦ The APB protocol is a low-cost interface, low frequency, low power and a
Single channel protocol used to connect various peripherals or memory
components to a CPU in SoC designs.
◦ The APB interface is not pipelined and is a simple, synchronous protocol.
Every transfer takes at least two cycles to complete.
◦ Used to communicate with the low bandwidth peripheral components like
I2C, PCI, UART, Timer, Keypad and PIO.
◦ The APB interface is designed for accessing the programmable control
registers of peripheral devices. APB peripherals are typically connected to
the main memory system using an APB bridge. For example, a bridge from
AXI to APB could be used to connect a number of APB peripherals to an
AXI memory system.
APB Topology
Block Diagram
Signal Description
SIGNAL SOURCE DESCRIPTION

PCLK Clock PCLK is a clock signal. All APB signals are timed against the rising
edge of PCLK.
PRESETn System bus PRESETn is the reset signal and is active-LOW. PRESETn is normally
reset connected directly to the system bus reset signal.
PADDR Master PADDR is the APB address bus.

PPROT Master Protection type

PSELx Master The Master generates a PSELx signal for each Slave. PSELx indicates
that the Slave is selected and that a data transfer is required.
PENABLE Master PENABLE indicates the second and subsequent cycles of an APB
transfer.
PWRITE Master PWRITE indicates an APB write access when HIGH and an APB read
access when LOW
PWDATA Master The PWDATA write data bus is driven by the APB bridge Master
during write cycles when PWRITE is HIGH.
SIGNAL SOURCE DESCRIPTION

PSTRB Master PSTRB indicates which byte lanes to update during a write transfer.
There is one write strobe for each 8 bits of the write data bus. PSTRB
must not be active during a read transfer.
PREADY Slave PREADY is used to extend an APB transfer by the Slave.

PSLVERR Slave Transfer error. PSLVERR is an optional signal that can be asserted
HIGH by the Slave to indicate an error condition on an APB transfer
PRDATA Slave The PRDATA read data bus is driven by the selected Slave during
read cycles when PWRITE is LOW.
Protection Unit Support
Operating States
• Idle state → default state

• Setup state → when PSELx, is asserted. The interface only


remains in the SETUP state for one clock cycle and always
moves to the ACCESS state on the next rising edge of the
clock.

• Access state → PENABLE is asserted. The signals like PADDR,


PPROT, PWRITE, PWDATA, (only for write transactions), & PSTRB
must not change in the transition between SETUP and
ACCESS and between cycles in the ACCESS state.

• Exit from the Access state is controlled by the PREADY signal


from the Slave.
• Stay in Access state if PREADY is low.
• Goto IDLE if PREADY is High and no more data.
• Goto SETUP state if PREADY is High and more data
pending.

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