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Real Time Clock

The document describes a Verilog implementation of a real-time clock using upcounters and seven-segment displays. It includes modules for counting seconds, minutes, and hours, as well as a testbench for simulation. The design features enable the clock to reset and clear, with appropriate display outputs for each time unit.

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4 views5 pages

Real Time Clock

The document describes a Verilog implementation of a real-time clock using upcounters and seven-segment displays. It includes modules for counting seconds, minutes, and hours, as well as a testbench for simulation. The design features enable the clock to reset and clear, with appropriate display outputs for each time unit.

Uploaded by

kollasunnykumar123
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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REAL TIME CLOCK

TOP MODULE:-
module upcounter #(parameter max_value = 15, count_size = 4)
(input clk, rst, en, clr,
output reg [count_size-1 : 0] count );
always@(posedge clk or posedge rst or posedge clr)
begin
if(rst)
count <= 4'b0000;
else if (en)
begin
if (count == max_value)
count <= 4'b0000;
else
count <= count + 1;
end
end
endmodule

module seven_segment_display( input [3:0] in,


output reg [6:0] display);
always@(*)
begin
case(in)
4'b0000: display = 7'b1111110;
4'b0001: display = 7'b0110000;
4'b0010: display = 7'b1101101;
4'b0011: display = 7'b1111001;
4'b0100: display = 7'b0110011;
4'b0101: display = 7'b1011011;
4'b0110: display = 7'b1011111;
4'b0111: display = 7'b1110000;
4'b1000: display = 7'b1111111;
4'b1001: display = 7'b1111011;
default: display = 7'b0000000;
endcase
end
endmodule

module real_time_clock (input clk, rst, en, clr,


output [6:0] secl, secm, minl, minm, hrl, hrm);

wire [3:0] SECL, SECM, MINL, MINM, HRL, HRM;

upcounter #(9) secL (.clk(clk), .rst(rst), .en(1'b1), .clr(1'b0), .count(SECL));


seven_segment_display seCL (.in(SECL), .display(secl));

wire SECM_EN;
assign SECM_EN = (SECL == 4'b1001);

upcounter #(5) secM (.clk(clk), .rst(rst), .en(SECM_EN), .clr(1'b0), .count(SECM));


seven_segment_display SEC (.in(SECM), .display(secm));

wire MINL_EN;
assign MINL_EN = ((SECM == 4'b0101) && (SECL == 4'b1001));

upcounter #(9) minL (.clk(clk), .rst(rst), .en(MINL_EN), .clr(1'b0), .count(MINL));


seven_segment_display miNL (.in(MINL), .display(minl));

wire MINM_EN;
assign MINM_EN = ((MINL == 4'b1001) && (SECM == 4'b0101) && (SECL == 4'b1001));

upcounter #(5) minM (.clk(clk), .rst(rst), .en(MINM_EN), .clr(1'b0), .count(MINM));


seven_segment_display miNM (.in(MINM), .display(minm));

wire HRL_EN;
assign HRL_EN = ((MINM == 4'b0101) && (MINL == 4'b1001) && (SECM == 4'b0101) && (SECL
== 4'b1001));

upcounter #(9) hrL (.clk(clk), .rst(rst), .en(HRL_EN), .clr(1'b0), .count(HRL));


seven_segment_display hRM (.in(HRL), .display(hrl));

wire HRM_EN;
assign HRM_EN = ((HRL == 4'b1001) && (MINM == 4'b0101) && (MINL == 4'b1001) && (SECM
== 4'b0101) && (SECL == 4'b1001));

wire clrs;
assign clrs = ((HRL == 4'b0010) && (HRM == 4'b0011) && (MINM == 4'b0101) && (MINL ==
4'b1001) && (SECM == 4'b0101) && (SECL == 4'b1001));

upcounter #(2) hrM (.clk(clk), .rst(rst), .en(HRM_EN), .clr(clrs), .count(HRM));


seven_segment_display hRL (.in(HRM), .display(hrm));
endmodule

Test module:-
module testbench;
reg clk, rst, en, clr;
wire [6:0] secl, secm, minl, minm, hrl, hrm;

real_time_clock rtc (
.clk(clk),
.rst(rst),
.en(en),
.clr(clr),
.secl(secl),
.secm(secm),
.minl(minl),
.minm(minm),
.hrl(hrl),
.hrm(hrm)
);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
rst = 1;
en = 0;
clr = 0;
#15;
rst = 0;
en = 1;
#1000000;
clr = 1;
#10;
clr = 0;
#100
$stop();
end
initial begin
$monitor("Time: %0t | SECL: %b | SECM: %b | MINL: %b | MINM: %b | HRL: %b | HRM: %b",
$time, secl, secm, minl, minm, hrl, hrm);
end
endmodule

OUTPUT:-

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