CPE3341: Digital System Design Lab

Design Lab # 2
Verilog: Data-Flow Modeling
Objective: Lab #2 will familiarize students with Data-Flow Modeling of digital
circuits in Verilog Programming Language. Students will also learn about writing
test-benches in Verilog for digital designs.

Tasks included in this Lab are:

5. Design data flow model of a 1-bit full adder in Verilog HDL

6. Write Stimulus module to test the functionality of 1-bit full adder

7. Design data flow model of a 4 to 1 MUX in Verilog HDL

8. Write a Stimulus module to test the functionality of 4 to 1 MUX

Complete your Lab Assignments in Lab .Submit your lab report to Lab Instructor.

1 Design of 1-bit Full Adder

(a). Create a new ModelSim project. Project will simulate a 1-bit Full Adder Module in Data-
flow Modeling

(b). Add new file of type Verilog to the project. Write Verilog module for 1-bit full adder in data
follow modeling in the file.

(c). Add new file of type Verilog to the same project. Write Stimulus module for testing and
verification of 1-bit full adder in the file. Stimulus module should instantiate the 1-bit full adder
module.

Give all possible input combinations to test 1-bit full adder module. Use the $monitor to display
all inputs and outputs of the design module.

(e). Compile the project and correct any syntax errors. Next simulate the project and display
results in output window. Also verify timing waveform in the timing window

Verify the results and show them to the lab instructor

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Below are circuit diagrams of 1-bit Full Adder and 4-bit Full adder blocks

Figure 16.1-bit Full Adder Circuit

Figure 17. Four bit full adder Circuit

2 Design of 4 to 1 MUX

(a). Create a new ModelSim project. Project will simulate a 4 to 1 MUX Module in Data-flow
Modeling

(b). Add new file of type Verilog to the project. Write Verilog module for 4 to 1 MUX in data
flow modeling in the file.

(c). Add new file of type Verilog to the same project. Write Stimulus module for testing and
verification of 4 to 1 MUX in the file. Stimulus module should instantiate the 4 to 1 MUX
module.

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Give different input combinations of input and selection lines to the design module. Use the
$monitor to display all inputs and outputs of the 4 to 1 MUX module.

(d). Compile the project and correct any syntax errors. Next simulate the project and display
results in output window. Also verify timing waveform of output

Verify the results and show them to the lab instructor

Below is circuit diagrams of 4 to 1 MUX and 8 to 1 MUX

Figure 18. 4 to 1 MUX Circuit

Figure 19. 8 to 1 MUX using 4 to 1 MUX's

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 Design Lab # 2

Lab Assignment
Activity# 01

• Create a new project in ModelSim, add the files containing 1-bit full adder module and
Stimulus module to the project
• Compile and run the simulation of 1-bit adder in ModelSim
• Create a new project in ModelSim, add the files containing 4 to 1 MUX module and
Stimulus module to the project
• Compile and run the simulation of 4 to 1 MUX in ModelSim
• Display inputs and outputs of 1-bit full adder and 4 to 1 MUX and show results to Lab
Instructor

Activity# 02
• Write Verilog code in data flow modeling for 4-bit Full Adder Circuit. 4-bit adder
module will instantiate multiple instances of 1-bit Full adder designed in Task 1
• Write Stimulus module to verify your 4-bit full adder design. Stimulus module should
give 8 different inputs to 4-bit adder and display corresponding outputs using $monitor.
Also display output waveform

Activity#03
• Write Verilog Module for an 8 to 1 MUX in data flow modeling. 8 to 1 MUX module will
instantiate multiple instances of 4 to 1 MUX already implement in Task 1. Also add any
other required logic for 8 to 1 MUX
• Write Stimulus for 8 to 1 MUX in Verilog. Stimulus should check output for different
combinations of input & select lines to 8 to 1 MUX

Lab Check-Off

• Demonstrate your design and show outputs and wave window saved file for each Task
to Lab Instructor

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 Design Lab # 2
Lab Report
Student Name:_____________________ Reg. #________________

Answer the following:

1. Explain objective of the Lab and outline the Lab tasks

2. Explain functionality of each Task implemented in the Lab

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 3. A full subtractor has three 1-bit inputs x, y, and z (previous borrow) and two 1-
bit outputs D (difference) and B (borrow). Logic equations for D and B are as
follows:

D = x'y'z + x'yz' + xy'z' + xyz

B = x'y + x'z +yz

Implement subtractor as a Verilog module.

(Remember that + in logic equations corresponds to a logical OR operator )

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 4. This a valid 2:1 MUX statement:
wire a, b, sel, q;
assign q = (~sel& a) | (sel& b);

But the following is not:

wire[3:0] a, b, q;
wiresel;
assign q = (~sel& a) | (sel& b);

Why?

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 Lab Exercise and Summary

Summary should cover Introduction, Procedure, Data Analysis and Evaluation.

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Student’s Signature: ________________ Date: ________________

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 LABORATORY SKILLS ASSESSMENT (Psychomotor)
Total Marks: 100

Criteria Level 1 Level 2 Level 3 Level 4 Score

(Max Marks) 0% ≤ S < 50% 50% ≤ S< 70% 70% ≤ S< 90% 90%≤ S ≤100% (S)
Procedural Selects Selects and applies Selects and applies Selects and
Awareness inappropriate appropriate skills the appropriate applies
(20) skills and/or and/or strategies strategies and/or appropriate
strategies required by the skills specific to the strategies and/or
required by the task with some task without skills specific to
task errors significant errors the task without
any error
Practical Makes several Makes few critical Makes some non- Applies the
Implementation critical errors in errors in applying critical errors in procedural
(30) applying procedural applying procedural knowledge in
procedural knowledge knowledge perfect ways
knowledge
Safety Requires constant Requires some Follows safety Routinely follows
(10) reminders to reminders to follow procedures with safety procedures
follow safety safety procedures only minimal
procedures reminders
Use of Uses tools, Uses tools, Uses tools, Uses tools,
Tool/Equipment equipment and equipment and equipment and equipment and
(20) materials with materials with materials with materials with a
limited some competence considerable high degree of
competence competence competence
Participation Shows little Demonstrates Demonstrates Actively helps to
to Achieve commitment to commitment to commitment to identify group
Group Goals group goals and group goals, but group goals and goals and works
(10) fails to perform has difficulty carries out assigned effectively to
assigned roles performing roles effectively meet them in all
assigned roles roles assumed
Interpersonal Rarely interacts Interacts with other Interacts with all Interacts
Skills in positively within a group members if group members positively with all
Group Work group, even with prompted spontaneously group members
(10) prompting and encourages
such interaction
in others

Marks Obtained

Instructor’s Signature: ________________ Date: ________________

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 LABORATORY SKILLS ASSESSMENT (Affective)

Total Marks: 40

Criteria (Max. Level 1 Level 2 Level 3 Level 4 Score

Marks) 0% ≤ S < 50% 50% ≤ S < 70% 70% ≤ S < 90% 90% ≤ S ≤ 100% (S)
Introduction Very little Introduction is brief Introduction is nearly Introduction complete
(5) background with some minor complete, missing some and well-written;
information mistakes minor points provides all necessary
provided or background principles
information is for the experiment
incorrect
Procedure Many stages of the Many stages of the The procedure could be The procedure is well
(5) procedure are not procedure are more efficiently designed and all stages
entered on the lab entered on the lab designed but most of the procedure are
report. report. stages of the procedure entered on the lab
are entered on the lab report.
report.
Data Record Data is brief and Data provides some Data is almost complete Data is complete and
(10) missing significant significant but has some minor relevant. Tables with
pieces of information and has mistakes. units are provided.
information. few critical Graphs are labeled. All
mistakes. questions are
answered correctly.
Data Analysis Data are presented Data are presented Data are presented in Data are presented in
(10) in very unclear in ways (charts, ways (charts, tables, ways (charts, tables,
manner. Error tables, graphs) that graphs) that can be graphs) that best
analysis is not are not clear understood and facilitate
included. enough. Error interpreted. Error understanding and
analysis is included. analysis is included. interpretation. Error
analysis is included.
Report Report contains Report is somewhat Report is well organized Report is well
Quality many errors. organized with and cohesive but organized and
(10) some spelling or contains some cohesive and contains
grammatical errors. grammatical errors. no grammatical errors.
Presentation seems
polished.

Marks Obtained
LABORATORY SKILLS ASSESSMENT (Cognitive)

Total Marks: 10
( If any )
Marks Obtained

Instructor’s Signature: ________________ Date: ________________

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