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Capital University of Science and Technology, Islamabad

The document outlines the course CPE3343: Digital System Design offered by Capital University of Science and Technology, detailing prerequisites, credit hours, and recommended textbooks. It aims to teach students digital design techniques using Verilog HDL for modeling digital systems and focuses on efficient design of data path and control path units. Course learning outcomes include applying digital design knowledge, designing algorithm-to-architecture mappings, and documenting technical reports on real-world engineering problems.

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mohammaduzair726
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14 views3 pages

Capital University of Science and Technology, Islamabad

The document outlines the course CPE3343: Digital System Design offered by Capital University of Science and Technology, detailing prerequisites, credit hours, and recommended textbooks. It aims to teach students digital design techniques using Verilog HDL for modeling digital systems and focuses on efficient design of data path and control path units. Course learning outcomes include applying digital design knowledge, designing algorithm-to-architecture mappings, and documenting technical reports on real-world engineering problems.

Uploaded by

mohammaduzair726
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Capital University of Science and Technology, Islamabad

Department of Electrical and Computer Engineering

CPE3343: Digital System Design

Pre-requisite(s): CPE3333: Microprocessors and Interfacing

Credit Hours: 3

Total No. of Lectures: 48

Recommended Book(s): 1. “Verilog HDL- A Guide to Digital Design & Synthesis” 2nd
Edition By Sameer Palnitkar (or any Later Edition)
2. “Digital Design of Signal Processing Systems A Practical
3. Approach” by Shoab A. Khan, John Wiley Sons, 2011

Ref. Book(s): “Advanced Digital Design with the Verilog HDL” First Edition,
by Michael D. Ciletti, 2003, Prentice Hall

Targeted SDGs SDG-4: Quality Education


SDG-9: Industry, Innovation and Infrastructure

Course Objectives:
This course will introduce students to digital design techniques for mapping algorithms to Application
specific integrated circuits (ASICs) and architecture of Field programmable gate arrays (FPGAs).
Hardware descriptive language, Verilog will be used for modeling of digital systems and Mentor
Graphics EDA tool Modelsim will be used for design and simulation of digital systems and ASICs.
Course will focus on efficient design of data path and control path units, finite state machines and
mapping of algorithms to hardware.

Course Learning Outcomes (CLOs):


At the end of this course, the students should be able to:

No Description Taxonomy
PLOs
Level

Apply knowledge of digital design to model data-


path and control-path blocks in hardware PLO:1
CLO:1 description language (Verilog HDL) at various C3 (Engineering
levels of abstraction, testing and verification of Knowledge)
design modules by writing test-benches.

172
Design data-path and control-path blocks for
PLO:3
algorithm-to-architecture mapping by applying (Design and
CLO:2 C5
concepts of combinational and sequential logic, Development
finite state machines (FSMs) and design of Solutions)
optimization techniques.
Design and implement a solution for a real-world
PLO:4
CLO:3 problem on FPGAs using Verilog HDL and C6
Investigate the data-path and control-path for (Investigation)
optimal design constraints

Write a technical report documenting the analysis


of a given real-world complex engineering problem
and the details of its solution and formulate project PLO:7
CLO:4 deliverables with the knowledge of its impact on the A3 (Environment
and
environment and the society such that project Sustainability)
outcome is a sustainable solution in the light of
defined SDG goals.

Course Contents:

1. Introduction to ASIC Design & FPGAs


x Objectives of Digital Design
x Digital Design Flow
x ASIC Design Front end vs. Back end

2. Review of Digital Logic Design


x Review of Combinational Logic (Muxes, decoders, encoders, ROMs)
x Review of Sequential Logic (Flip Flops, State Diagrams, Counters, Registers)

3. Overview of Verilog HDL


x Verilog Syntax & Operators
x Verilog Gate Level & Data Flow Modeling
x Verilog Behavioral Modeling & RTL Design
x Test bench writing, Self-checking test benches
x RTL Coding Guide Lines

4. Representation of Numbers &Fixed Point Arithmetic


x Signed Numbers Representation
x Qn.m Format &Fixed Point Conversion
x Fixed point Arithmetic (Addition, Multiplication)
x Overflow & Saturation in fixed point arithmetic

5. Pipelining in Hardware
x Critical path of digital design
x Pipelining & Pipelined architectures

173
x Data coherency in pipelined architectures

6. Efficient Design of Control Unit


x Moore& Mealy Finite State Machine (FSMs)
x Micro-programmed State Machine
x Algorithmic State Machines (ASMs) & FSM to ASM Conversion
x Design of Control Unit
x Design of Single Cycle Processor

7. Field Programmable Gate Arrays (FPGA’s)


x Architecture of FPGA’s
x Logic Synthesis & FPGA based Design Methodology

8. Time-shared Architectures
x One to one mapping vs. time-shared architectures
x Design of Bit Serial Adder
x Design of Sequential Multiplier

9. Efficient design of Data path Units


x Digital design of Fast Adders
x Carry Skip Adder, Carry propagate adder, Conditional Sum Adder
x Digital Design of Fast Multipliers
x Carry Save Adder & Partial Product Reduction
x Carry Save , Dual Carry Save & Wallace Tree Reduction
x CSD Representation & Booth Recoding
x Design of Barrel Shifter

174

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