Kathmandu University

Department of Computer Science and Engineering

Dhulikhel, Kavre

A Mini Project Report

on

“RANN 12-bit Computer Design”

[Code No: COMP 315]

(For partial fulfilment of 3rd Year/1st Semester in Computer Engineering)

Submitted By:

Aavash Adhikari (01)

Nishant Ghimire (17)
Ram Krishna Ghimire (20)
Nishchal Raj Subedi (54)

Submitted To:
Pankaj Raj Dawadi

(Department of Computer Science and Engineering)

Submission Date: June 8, 2024

ACKNOWLEDGEMENT

We wish to extend our heartfelt thanks to Mr. Pankaj Raj Dawadi, our mentor, for his
invaluable guidance, direction, and unwavering support throughout the development of
our computer design, rooted in the foundational principles of "Basic Computer." Our
gratitude also extends to all those who facilitated our successful completion of this
endeavor. Through this project, we deepened our comprehension of essential
components like computer memory, registers, and flip-flops. Additionally, we
appreciate the university and the Department of Computer Science and Engineering
(DOCSE) for granting us the opportunity to undertake this project.
Abstract

A computer is an electronic device capable of interpreting and carrying out a few sets
of commands and instructions built into its design. These commands make up the
computer's instruction set. RANN computer is a 12-bit CPU computer that has
implemented all the basic requirements of a basic computer.

We have implemented various instructions based on the suitability of our computer

architecture. Our computer features a 3-bit opcode, an 8-bit address length, and a 1-bit
addressing mode, making it a functional 12-bit CPU basic computer. The RANN
includes the following hardware components:

1. A memory of 256 x 12

2. Registers: AR, PC, DR, AC, SC, IR, TR, INPR, OUTR

3. flip-flops: R, S, E, IEN, FGI, FGO

4. 3 X 8 Decoders

5. A 12-bit common bus system

6. Control Logic gates

7. Adder and logic circuit connected to the input of AC

As we have used a 256 x 12 sized memory, it will allow us to have 256 different slots
wherein 12 different bits can be stored and executed in each slot.

To simplify and enhance the flow of instructions, we have implemented a 12-bit

Common Bus System. The hardware components, when assembled along with various
logic gates such as AND and OR gates, enable us to execute different instructions and
achieve the desired output.

i
Table of Contents

ACKNOWLEDGEMENT ............................................................................................. i
Abstract .......................................................................................................................... i
List of Figures .............................................................................................................. iv
List of Tables ................................................................................................................ v
Chapter 1 Introduction ............................................................................................ 1
Chapter 2 Design Considerations ........................................................................... 2
2.1 Instruction Format .......................................................................................... 2
2.2 Addressing Modes .......................................................................................... 2
2.2.1 Direct Addressing Mode ......................................................................... 3
2.2.2 Indirect Addressing Mode....................................................................... 3
2.3 Instruction Sets ............................................................................................... 4
2.3.1 Memory Reference Instruction (MRI) .................................................... 4
2.3.2 Register Reference Instruction (RRI) ..................................................... 5
2.3.3 Input Output Instruction (IOI) .................................................................... 5
2.4 Control Unit.................................................................................................... 6
2.4.1 Timing and Control ................................................................................. 6
2.4.2 Timing Signals ........................................................................................ 8
2.5 Instruction Cycle ............................................................................................ 8
2.5.1 Fetch Cycle ............................................................................................. 8
2.5.2 Decode Cycle .......................................................................................... 9
2.5.3 Execution Cycle .................................................................................... 11
2.6 I/O and Interrupt ........................................................................................... 13
2.6.1 Register Transfer Operations in Interrupt Cycle ................................... 15
2.7 Components.................................................................................................. 16
2.7.1 Registers ................................................................................................ 16
2.7.2. Arithmetic and Logic Unit (ALU) ............................................................. 18
2.7.3. Memory ..................................................................................................... 18

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 2.7.4. Common Bus System ................................................................................ 19
2.7.5 Flip Flops .................................................................................................... 21
Chapter 3 Design of Components ......................................................................... 22
3.1 Control of Registers and Memory ................................................................ 22
3.1.1 AR ............................................................................................................... 22
3.1.2 DR ............................................................................................................... 23
3.1.3 PC ............................................................................................................... 24
3.1.4 SC ............................................................................................................... 24
3.1.5 IR ................................................................................................................ 25
3.1.6 TR ............................................................................................................... 25
3.1.7 OUTR ......................................................................................................... 26
3.1.8 AC ............................................................................................................... 26
3.1.9 Memory ...................................................................................................... 27
3.2 Control of Flags ............................................................................................ 28
3.2.1 Start-Stop Flip Flop (S) ............................................................................ 28
3.2.2 End-around Carry (E) ............................................................................... 29
3.2.3 Interrupt Flip Flop(R) ............................................................................... 29
3.2.3 Interrupt Enable (IEN) .............................................................................. 30
3.2.3 Input Flag (FGI)........................................................................................ 30
3.2.3 Output Flag (FGO) ..................................................................................... 31
3.3 Control of Common Bus ................................................................................... 32
3.4. ALU (Adder and Logic Circuit) ....................................................................... 36
Chapter 4: Conclusion................................................................................................. 37

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List of Figures

Figure 1. Instruction Format ......................................................................................... 2

Figure 2. Direct Addressing Mode................................................................................ 3
Figure 3. Indirect Addressing Mode ............................................................................. 3
Figure 4. Control Unit of RANN computer .................................................................. 7
Figure 5. Instruction Types ......................................................................................... 10
Figure 6. Flowchart for interrupt cycle ....................................................................... 14
Figure 7. Common Bus System .................................................................................. 20
Figure 8. r signal ......................................................................................................... 22
Figure 9. p signal......................................................................................................... 22
Figure 10. AR Control ................................................................................................ 23
Figure 11. DR Control ................................................................................................ 23
Figure 12. PC Control ................................................................................................. 24
Figure 13. SC Control ................................................................................................. 25
Figure 14. IR Control .................................................................................................. 25
Figure 15. TR Control ................................................................................................. 26
Figure 16. OUTR Control ........................................................................................... 26
Figure 17. AC Control ................................................................................................ 27
Figure 18. Memory Write ........................................................................................... 27
Figure 19. Memory Read ............................................................................................ 28
Figure 20. S Flip Flop ................................................................................................. 28
Figure 21. E Flip Flop ................................................................................................. 29
Figure 22. R Flip Flop ................................................................................................. 29
Figure 23. IEN Control ............................................................................................... 30
Figure 24. FGI Control ............................................................................................... 30
Figure 25. FGO Control .............................................................................................. 31
Figure 26. Control of Common Bus System............................................................... 35
Figure 27. One stage of ALU ...................................................................................... 36

iv
List of Tables

Table 1. Addressing Modes .......................................................................................... 2

Table 2. Memory Reference Instruction ....................................................................... 4
Table 3. Register Reference Instruction........................................................................ 5
Table 4. Input Output Instruction.................................................................................. 5
Table 5. Register Reference Instructions .................................................................... 11
Table 6. One stage of ALU ......................................................................................... 12
Table 7. Input Output Instructions .............................................................................. 13
Table 8. Flip Flops ...................................................................................................... 21
Table 9. Control of Common Bus ............................................................................... 32

v
Chapter 1 Introduction

Computers can only process binary code, which consists of specific instructions. The
capacity of computers to understand and carry out these instructions is ingrained in
their design, forming an instruction set. Choosing the correct set of instructions and
binary code is vital for computer developers.

RANN is a 12-bit CPU that we have developed and simulated, implements all the ideas
of Computer System Architecture together. It has different instructions based on the
suitability of design. RANN has one bit addressing mode, 3 bit opcode, and 8 bit
address length.

The major hardware components of our basic computer is described below:

1. A memory of 256 x 12

2. Registers: AR, PC, DR, AC, IR, TR, INPR, OUTR, SC

3. flip-flops: R, S, E, IEN, FGI, FGO,

4. Decoders

5. A 12-bit common bus system

6. Control Logic gates

7. Adder and logic circuit connected to the input of AC.

1
Chapter 2 Design Considerations
The following section describes the design process, the internal architecture of the
RANN computer, and the instruction set supported by this computer.

2.1 Instruction Format

There are two parts an instruction can be divided into. They are:

a. Operation code (Opcode): It specifies the operation for an instruction.

b. Address: It specifies the registers and/or locations in the memory to use for a
particular operation.

In the RANN computer, the memory contains 256 (or 28) words, so we need 8 bits to
specify the memory address used by an instruction. Given that each word is 12 bits, we
allocate 8 least significant bits (LSBs) for the address. The most significant bit (MSB)
is reserved to represent the addressing mode. The remaining 3 bits are used to represent
the opcodes of the instruction.

Figure 1. Instruction Format

2.2 Addressing Modes

There are 2 addressing modes used in the RANN computer. They are:
Table 1. Addressing Modes

Addressing Mode Field Addressing Mode

Io 0 Direct

I1 1 Indirect

2
2.2.1 Direct Addressing Mode

The address of the operand is stored in the memory location specified in the instruction
in the direct addressing mode.

Figure 2. Direct Addressing Mode

2.2.2 Indirect Addressing Mode

The address of the operand is stored in the instruction in the indirect addressing mode.

Figure 3. Indirect Addressing Mode

3
2.3 Instruction Sets
The different types of instruction formats with their instruction types in RANN
Computer is described below:

2.3.1 Memory Reference Instruction (MRI)

In MRI, 4 bits are read from the memory during the fetch and decode cycle. It is used
to specify the memory operation, and the next 8 bits read from the memory contains
the memory address of the operand.
Table 2. Memory Reference Instruction

SYMBOL DECODER OPCODE DESCRIPTION

I=0 I=1

SWP D0 0000X 1000X SWAP the value of AC with

memory word

AND D1 0001X 1001X AND the AC with memory

word

ADD D2 0010X 1010X ADD the memory word of AC

and save to AC

LDA D3 0011X 1011X Load accumulator with memory

word

STA D4 0100X 1100X Store value of AC to memory

BUN D5 0101X 1101X Branch unconditionally

BSA D6 0110X 1110X Branch and save the return

address

Here, ‘X’ represents an 8-bit memory address

4
2.3.2 Register Reference Instruction (RRI)

RRI instructions manipulate the contents of the registers without involving memory
locations.

RANN has the following register reference instructions.

Table 3. Register Reference Instruction

Symbol Instruction Description

CLA 0111 00000001 Clear AC

CLE 0111 00000010 Clear E

CME 0111 00000100 Complement E

SHL 0111 00001000 Shift Left Output Register

SHR 0111 00010000 Shift Right Output Register

CMA 0111 00100000 Complement the Accumulator

INC 0111 01000000 Increment AC

HLT 0111 10000000 Halt the Computer

2.3.3 Input Output Instruction (IOI)

Table 4. Input Output Instruction

Symbol Instruction Description

INP 1111 00000001 Input character to AC

5
 OUT 1111 00000010 Output character from AC

SKI 1111 00000100 Skip on Input Flag

SKO 1111 00001000 Skip on Output Flag

IENT 1111 00010000 Interrupt Enable On

IENF 1111 00100000 Interrupt Enable Off

2.4 Control Unit

The control unit in the RANN computer is set up with a hardwired control system. It
uses circuits made of gates, flip-flops, and other digital components. Its main role is to
organize how the computer operates, deciding how instructions and data move around
inside the system.

2.4.1 Timing and Control

The RANN computer relies on a master clock to ensure synchronization. This clock
sends regular pulses to various components like flip-flops and memory registers.
However, these pulses only impact a component if it's instructed to do so by a control
signal. These control signals originate from the control unit, directing different parts of
the computer. For instance, they guide the memory on data transmission and instruct
the processor on which operations to execute.

6
 Figure 4. Control Unit of RANN computer

The block diagram of the control unit is shown in the figure above. It consists of two
decoders, a sequence counter, and several control logic gates. An instruction read from
memory is placed in the instruction register (IR). The IR consists of three parts: the
addressing mode field, the operation code, and the address. The addressing mode field
in bits 12 is stored in I flip flop. Similarly, the operation codes in bits 10 through 8 are
decoded with a 3 x 8 decoder. The eight outputs of the opcode decoder are designated
by the symbols D0 through D7. Bits 0 through 7 are applied to the control logic gates.

7
2.4.2 Timing Signals

The 4-bit sequence counter can count in binary from 0 through 15. Its outputs are
decoded into 16 timing signals labeled T0 through T15. The sequence counter can be
either incremented or cleared synchronously. Typically, the counter is incremented to
generate the sequence of timing signals through the 4x16 decoder. Occasionally, after
the completion of an instruction, the counter is reset to 0, causing the next active timing
signal to be T0.

2.5 Instruction Cycle

A machine instruction is executed in the following cycle:

1. Fetch Cycle: Here, the instruction is fetched from the main memory.

2. Decode Cycle: Following instruction fetching, the decoding process occurs

within this cycle, primarily during the T2 cycle. Here, the design ensures that
instructions are routed to their respective addressing modes accordingly.

3. Execution Cycle: The instructions are finally executed in this phase.

2.5.1 Fetch Cycle

In the fetch cycle, the instruction is retrieved from memory and stored in the instruction
register. Initially, the address of the next instruction in memory is held in the program
counter. During the first T0 timing signal, this address is transferred to the Address
Register. Subsequently, during the next timing signal, the content of the memory
pointed to by the Address Register is copied to the instruction register. At the same
time, both the Program Counter and the Address Register are incremented by one.
The following RTL denotes the fetch cycle.

T0 : AR ← PC
T1 : IR ← M[AR], PC ← PC + 1

8
2.5.2 Decode Cycle

During the decode cycle, the instruction stored in the instruction register is decoded to
determine its type. This decoding process generates the necessary lines to specify the
operation to be performed. The RTL (Register Transfer Language) notation represents
the decoding cycle.
T2 : D0…D7 ←Decode IR (10-8), I ← IR(11), AR ←IR(7-0)

Determine the type of instruction

After the instruction is fetched from memory, it undergoes decoding during the T2
cycle to determine its nature before proceeding to the Execution cycle. The decoded
values of I and D0 to D7 are evaluated to identify whether the instruction is MRI
(Memory Reference Instruction), RRI (Register Reference Instruction), or IOI
(Input/Output Instruction).
A flowchart illustrating the fetch and decode cycle is provided below.

9
 Figure 5. Instruction Types

From Figure 5,
D7’IT3 : AR ← M[AR]
D7’I’T3 : Nothing (NOP)
D7I’T3 : Execute a register reference instruction
D7IT3 : Execute an input-output instruction

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2.5.3 Execution Cycle

After the decision is made in the T2 cycle, the instructions are directed to their
respective addressing modes. Subsequently, during the T3 cycle, the execution phase
commences. The instructions are divided into three categories: register-reference,
memory-reference, and input-output instructions.

2.5.3.1 Register Reference Instructions (RRI)

D7I’T3 = r (Common for all register-reference instructions)

R : SC ← 0
Table 5. Register Reference Instructions

Symbol Instruction Description

CLA rB0 AC ← 0

CLE rB1 E←0

CME rB2 E ← E’

SHL rB3 AC ← shl AC

SHR rB4 AC ← shr AC

CMA rB5 AC ← (AC)’

INC rB6 AC ←AC + 1

HLT rB7 S ← 0 (S: start stop flip flop)

11
2.5.3.2 Memory Reference Instructions (MRI)

Table 6. One stage of ALU

Symbol Instruction Cycle

SWP D0T4 : TR ← M[AR]

D0T5: M[AR] ← AC
D0T6 : AC ← TR, SC ← 0

AND D1T4 : DR ← M[AR]

D1T5 : AC ← AC ^ DR, SC ← 0

ADD D2T4 : DR ← M[AR]

D2T5 : AC ← AC + DR, E ← Cout SC ← 0

LDA D3T4 : DR ← M[AR]

D3T5 : AC ← DR, SC ← 0

STA D4T4 : DR ← M[AR], SC ← 0

BUN D5T4 : PC ← AR, SC ← 0

BSA D6T4 : M[AR] ←PC, AR ← AR + 1

D6T5 : PC ← AR, SC ← 0

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2.5.3.3 Input Output Instructions (IOI)

D7IT3 : p (Common to all I/O instructions)

Table 7. Input Output Instructions

Symbol Instruction Description

INP pB0 AC ← INPR, FGI← 0

OUT pB1 OUTR← AC, FGO← 0

SKI pB2 If(FGI==1) then PC← PC+1

SKO pB3 If(FGO==1) then PC← PC+1

IENT pB4 IEN ← 1

IENF pB5 IEN ← 0

2.6 I/O and Interrupt

An interrupt is a signal emitted by a device connected to a computer or from a program

running within the computer. It temporarily pauses or halts a service or ongoing
process. Interrupts occur when data needs to be transferred, such as when input is being
fetched or output is being transferred from OUTR. The I/O interface monitors the I/O
devices instead of the CPU. When the interface detects that an I/O device is ready for
data transfer, it sends an interrupt request to the CPU. Upon detecting an interrupt, the
CPU briefly suspends its current task, switches to the service routine to handle the
transfer, and then resumes the previous task.

13
 Figure 6. Flowchart for interrupt cycle

Here, ‘R’ represents an interrupt flip-flop.

14
2.6.1 Register Transfer Operations in Interrupt Cycle

The interrupt cycle begins after the last execution phase if the interrupt flip-flop R is
set to 1. This flip-flop is activated if the IEN (Interrupt Enable) is equal to 1 and either
FGI (Flag for Input) or FGO (Flag for Output) is equal to 1. This condition can occur
during any clock transition except when timing signals T0, T1, or T2 are active. The
condition for setting flip-flop R to 1 can be expressed with the following register
transfer statement:
T0’T1’T2’(IEN)(FGI + FGO): R ← l
The symbol ‘+’ between FGI and FGO in the control function designates a logic OR
operation. This is ANDed with IEN and T0’T1’T2’.
We now modify the fetch and decode phases of the instruction cycle. Instead of solely
relying on timing signals T0, T1, and T2 (as shown in Figure:6), we will AND these
signals with the interrupt flip-flop R to recognize the fetch and decode phases using the
three control functions RT0, RT1, and RT2. This modification ensures that after an
instruction is executed and the SC (Sequence Counter) is cleared to 0, the control will
enter a fetch phase only if R equals 0. However, if R equals 1, indicating an interrupt
request, the control will proceed through an interrupt cycle. During this cycle, the return
address (available in PC - Program Counter) will be stored into memory location 0, the
control will branch to memory location 1, and the interrupt enable (IEN), interrupt flip-
flop (R), and SC will all be cleared to 0. This sequence of microoperations can be
implemented as follows:
RT0 : AR ← 0, TR ← PC
RT1 : M [AR] ← TR, PC ← 0
RT2 : PC ← PC+1, IEN ← 0, R ← 0, SC ← 0
During the first timing signal, the Address Register (AR) is cleared to 0, and the content
of the Program Counter (PC) is transferred to the temporary register (TR). With the
second timing signal, the return address is stored in memory at location 0, and the PC
is cleared to 0. During the third timing signal, the PC is incremented to 1, the interrupt

15
enable (IEN) and interrupt flip-flop (R) are cleared, and control returns to T0 by
clearing the Sequence Counter (SC) to 0.
At the beginning of the next instruction cycle, the condition RT0 is met, and the content
of the PC is equal to 1. The control then proceeds through an instruction cycle that
fetches and executes the BUN (Branch Unconditionally) instruction located at memory
location 1.

2.7 Components

2.7.1 Registers
RANN Computer is composed of 9 registers. They are as follows:

2.7.1.1 Instruction Register (IR)

Size: 12 bits
IR stores the 12 bits of instruction read from the memory. At the start of each instruction
cycle, the address contained in the PC is transferred to the AR, and the content of the
memory location pointer by AR is then transferred to the IR through the common bus
system (CBS). Once the instruction is loaded in the IR it is then decoded to obtain the
decoded lines (10-8), (D0 - D7) and B0 - B7 which along with the timing signals are
used to provide the necessary control signals for the computer to execute the stated
operation.

2.7.1.2 Program Counter

Size: 8 bits
The program counter contains the address of the memory location where the next
instruction is located. At the beginning of each instruction cycle (fetch), the content of
the program counter is transferred to AR and then is incremented by one point to the
next consecutive location. In the case of subroutines, the content of the program counter
(PC) is saved in the memory and is loaded with the location of the memory containing

16
the subroutine procedure. Finally, at the end of the subroutine call, the PC is loaded
with the previously saved address and the execution cycle continues.

2.7.1.3 Data Register

Size: 12 bits
The data register is used to store the operand read from the memory that is to be
processed. The output of the data register is an input to the ALU.

2.7.1.4 Accumulator

Size: 12 bits
The accumulator is the main register for most of the operations. It stores the result of
any operation after its completion. The input of the accumulator comes from the output
of the ALU. The input of the accumulator is not directly interfaced with the CBS. The
output of the AC goes to the common bus system which goes to ALU as the first
operand, the second being the content of the Data register.

2.7.1.5 Input Register

Size: 6 bits
Input register (INPR) is connected to the ALU and the content of the input register is
transferred to the ALU on the selection of the transfer operation.

2.7.1.6 Output Register

Size: 6 bits
Output register (OUTR) is used by the computer to provide output. It receives its output
from the common bus system which usually comes from the accumulator. This output
may be then connected to an external display.

2.7.1.7 Temporary Register

Size: 12 bits

17
A 12-bit non-programmable register is used to hold data during an arithmetic and logic
operation. In our RANN computer design, the temporary register came into play, when
we were performing the SWP operation.

2.7.1.8. Sequence Counter

It is used for data rarely written to (e.g. system time), where the reader wants a
consistent set of information and is willing to retry if that information changes. In
RANN, a 3-bit sequence counter is used which is connected to a 4 x 16-bit decoder.

2.7.1.9. Address Register

Size:8 bits
It contains the main memory addresses of data and instructions or a portion of the
address that is used in the calculation of the complete addresses. It holds the memory
location of data that needs to be accessed.

2.7.2. Arithmetic and Logic Unit (ALU)

The arithmetic and logic unit in our computer performs arithmetic and logical
operations.

2.7.3. Memory

Size: 256*12
The memory size of 256 x 12 indicates a basic computer having 256 different slots
where 12 bits of instructions can be stored and executed in each slot. Memory stores
both the instruction and the data on which processing is to be performed. We require
an 8-bit address line to address all the words of the memory. Memory receives its
address from the Address Register (AR), it receives/sends its data from the common
bus system, read or write operations are distinguished from the control signal.

18
2.7.4. Common Bus System

The RANN Computer uses a 12-bit pathway called a bus to connect its internal
registers. These registers include Memory, Accumulator, Address Register, Program
Counter, Instruction Register, Temporary Register, and Data Register, each capable of
handling 12 bits of data. The Data Register communicates with the Arithmetic Logic
Unit (ALU), which is connected to both the Control Unit and the 12-bit Accumulator.

The Control Unit directs the system's operations and communicates with different parts
using control signals. It gets instructions from the Instruction Register, interprets them,
and coordinates tasks accordingly. Additionally, there's an Output Register with a
capacity of 6 bits, connected directly to the bus, enabling output operations. On the
other hand, an Input Register communicates with the ALU to receive incoming data.

To facilitate efficient data transfer between registers, an 8x1 Multiplexer is employed,

allowing the selection of specific registers for data transmission. Selection lines for the
multiplexer are determined by the output of a 3x8 encoder, streamlining the process of
selecting the appropriate register for data transfer.

In a nutshell, the RANN Computer employs a 12-bit bus to connect various registers,
facilitating data transfer and manipulation under the control of the Control Unit.

19
Figure 7. Common Bus System

20
2.7.5 Flip Flops

There are 6 flags used in RANN Computer. They are as follows:

Table 8. Flip Flops

Flip Flops Description

E End Around Carry

FGI Input Flag

FGO Output Flag

IEN Interrupt Enable Flag

R Interrupt Flag

S Start Stop Flip Flop

21
Chapter 3 Design of Components

3.1 Control of Registers and Memory

The following are the controls of registers and memory used in computers. For
simplification, we have used r and p as a combination of signals such as:

Figure 8. r signal

r → D7I’T3

Figure 9. p signal

p → D7IT3

3.1.1 AR

LD:
R’T0 : AR ← PC
R’T2 : AR ← IR (11-0)
D7’IT3 : AR ← M[AR]

INC:
D6T4 : AR ← AR + 1

CLR:
RT0 : AR ← 0

22
 Figure 10. AR Control

3.1.2 DR

LD:
D1T4 : DR ← M[AR]
D2T4 : DR ← M[AR]
D3T4 : DR ← M[AR]
D4T4 : DR ← M[AR]

Figure 11. DR Control

23
3.1.3 PC

LD:
D5T4 : PC ← AR
D6T5 : PC ← AR

INC:
R’T1 : PC ← PC + 1
pB3 : PC ← PC + 1 (if FGO = 1)
pB2 : PC ← PC + 1 (if FGI = 1)
RT2 : PC ← PC + 1

Figure 12. PC Control

3.1.4 SC

CLR:
r : SC ← 0
D0T6 : SC ← 0
D1T5 : SC ← 0
D2T5 : SC ← 0
D3T5 : SC ← 0

24
 D4T4 : SC ← 0
D5T4 : SC ← 0
D6T5 : SC ← 0
RT2 : SC← 0

Figure 13. SC Control

3.1.5 IR
CLR:
R’T1 : IR ← M[AR]

Figure 14. IR Control

3.1.6 TR
LD:
D0T4 : TR ← M[AR]

25
 RT0 : TR ← PC

Figure 15. TR Control

3.1.7 OUTR

LD:
pB1 : OUTR ← AC

Figure 16. OUTR Control

3.1.8 AC
LD:
pB0 : AC ← INPR
D3T5 : AC ← DR
D0T6 : AC ← TR
rB4 : AC ← (AC)’

INC:
rB6 : AC ← AC + 1

26
CLR:
rB0 : AC ← 0

Figure 17. AC Control

3.1.9 Memory

3.1.9.1 Memory Write:

D0T5 : M[AR] ← AC
D6T4 : M[AR] ← PC
RT1 : M[AR] ← TR

Figure 18. Memory Write

27
3.1.9.2 Memory Read:
R’T1 : IR ← M[AR]
D7’IT3 : AR ← M[AR]
D1T4 : DR ← M[AR]
D2T4 : DR ← M[AR]
D3T4 : DR ← M[AR]
D4T4 : DR ← M[AR]
D0T4 : TR ← M[AR]

Figure 19. Memory Read

3.2 Control of Flags

3.2.1 Start-Stop Flip Flop (S)

rB7 : S ← 0

Figure 20. S Flip Flop

28
3.2.2 End-around Carry (E)

rB1 : E ← 0
rB2 : E ← E’
D2T5 : E ← Cout

Figure 21. E Flip Flop

3.2.3 Interrupt Flip Flop(R)

T0’T1’T2’(IEN)(FGI + FGO): R ← l
RT2 : R ← 0

Figure 22. R Flip Flop

29
3.2.3 Interrupt Enable (IEN)
pB4 : IEN ← l
pB5 : IEN ← 0
RT2 : IEN ← 0

Figure 23. IEN Control

3.2.3 Input Flag (FGI)

pB0 : FGI ← 0

Figure 24. FGI Control

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3.2.3 Output Flag (FGO)

pB1 : FGO ← 0

Figure 25. FGO Control

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3.3 Control of Common Bus

The 12-bit common bus is controlled by the selection inputs S2, S1, S0. Each binary
number selects each register. Each binary number is associated with a Boolean variable
X1 through X7.

Table 9. Control of Common Bus

X7 X6 X5 X4 X3 X2 X1 S2 S 1 S0 Register for the selected bus

0 0 0 0 0 0 0 0 0 0 None

0 0 0 0 0 0 1 0 0 1 AR

0 0 0 0 0 1 0 0 1 0 PC

0 0 0 0 1 0 0 0 1 1 DR

0 0 0 1 0 0 0 1 0 0 AC

0 0 1 0 0 0 0 1 0 1 IR

0 1 0 0 0 0 0 1 1 0 TR

1 0 0 0 0 0 0 1 1 1 Memory

The Boolean functions for the encoders are:

S0 = X1 + X3 + X5 + X7
S1 = X2 + X3 + X6 + X7
S2 = X4 + X5 + X6 + X7

To find the logic that makes X1 = 1, we extract all those statements with AR as source.
D5T4 : PC ← AR
D6T5 : PC ← AR

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X1 = D5T4 + D6T5

To find the logic that makes X2 = 1, we extract all those statements with PC as source.
R’T0 : AR ← PC
RT0 : TR ← PC
D6T4 : M[AR] ← PC
X2 = R’T0 + RT0 + D6T4

To find the logic that makes X3 = 1, we extract all those statements with DR as source.
D3T5 : AC ← DR
X3 = D3T5

To find the logic that makes X4 = 1, we extract all those statements with AC as source.
pB1 : OUTR ← AC
D1T5 : AC ← AC AND DR
D2T5 : AC ← AC + DR
X4 = D3T5 + D1T5 + D2T5

To find the logic that makes X5 = 1, we extract all those statements with IR as source.
R’T2 : AR ← IR (7-0)
R’T2 : AR ← IR (7-0)
X5 = R’T2

To find the logic that makes X6 = 1, we extract all those statements with TR as source.
RT1 : M[AR] ← TR
D0T6 : AC ← TR
X6 = D0T6 + RT1

To find the logic that makes X7 = 1, we extract all those statements with M[AR] as
source.
D7’IT3 : AR ←M[AR]

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R’T1 : IR ← M[AR]
D1T4 : DR ← M[AR]
D2T4 : DR ← M[AR]
D3T4 : DR ← M[AR]
D4T4 : DR ← M[AR]
D0T4 : TR ← M[AR]
X7 = D7’IT3 + R’T1 + D1T4 + D2T4 + D3T4 + D4T4 + D0T4

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Figure 26. Control of Common Bus System

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3.4. ALU (Adder and Logic Circuit)
We have implemented the one stage of the ALU with the corresponding input and
output carries.

Figure 27. One stage of ALU

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Chapter 4: Conclusion

Designing a 12-bit CPU was a complex yet indispensable process required to integrate
all concepts of Computer System Architecture. A comprehensive understanding of
computer organization and architecture was vital for the completion of this task.

After all hardware components were assembled accordingly, ensuring that different
instructions could run smoothly without causing any issues was found to be more
challenging than initially anticipated. However, through gradual work, the assembly of
all signal and control lines, and the alignment of the appropriate logic gates, led to the
successful design of the computer, which we named RANN.

In summary, crafting the 12-bit CPU, RANN, underscored the importance of Computer
System Architecture understanding, overcoming initial challenges to achieve
successful implementation.

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