Scribd
Upload
12 views1 page

VLSI2THEORY

Uploaded by

Boini RamNaresh Yadav
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
12 views1 page

VLSI2THEORY

Uploaded by

Boini RamNaresh Yadav
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 1

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY

HYDERABAD
UNIVERSITY COLLEGE OF ENGINEERING
WANAPARTHY
Narsingaipalli, Gopalpet Road, Wanaparthy Dist. Telangana
State – 509103

III B.Tech. II Semester I Mid-Term Examinations MARCH-2025 Part B (Descriptive Paper)


Name of the Branch: ECE Name of the Subject: VLSI
Time: 100 Min. Exam Date: 26-03-2025 Max. Marks: 20
Answer any Four out of Six Questions. All questions carry equal marks

1. Derive the Ids Vs Vds relation for NMOS transistor.When transistor is in Non-saturated
region & saturated region.
2. Explain steps in VLSI Design flow.
3. Draw the stick diagram and layout of CMOS inverter and explain the steps involved in
CMOS inverter stick diagram.
4. Draw the fabrication steps of CMOS transistor and explain its operation in detail.
5. Derive the pull-up to pull-down ratio of NMOS inverter is 4:1 and 8:1.
6. Draw the stick diagrams and explain the steps involved using NMOS design styles
a) NAND Gate b) NOR Gate

You might also like