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SPI Using Verilog 1744191828

The document describes a Verilog implementation of a Serial Peripheral Interface (SPI) master and slave module. The master module handles data transmission with state management for idle, transmission start, data transfer, and end states, while the slave module captures incoming data on the falling edge of the clock. A testbench is also provided to simulate the SPI communication between the master and slave modules.

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5 views5 pages

SPI Using Verilog 1744191828

The document describes a Verilog implementation of a Serial Peripheral Interface (SPI) master and slave module. The master module handles data transmission with state management for idle, transmission start, data transfer, and end states, while the slave module captures incoming data on the falling edge of the clock. A testbench is also provided to simulate the SPI communication between the master and slave modules.

Uploaded by

santhoshvelmurugan728
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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SERIAL PERIPHERAL INTERFACE

USING VERILOG

module spi_verilog_master(
input wire clk,
input wire reset,
input wire tx_enable,
output reg mosi,
output reg sclk,
output reg chip_select
);

//variables and states decleration


parameter idle=2'b00,tx_start=2'b01,tx_data=2'b10,tx_end=2'b11;
reg[1:0] state,next_state;
reg[2:0] count=0;
reg[3:0] bit_count=0;
reg[7:0] send_data=8'd181;

//state update
always@(posedge clk)begin
if(reset)
state<=idle;
else
state<=next_state;
end

//counter for sclk and bit_count


always@(posedge clk)begin
case(state)
idle:
begin
count<=0;
bit_count<=0;
end
tx_start:
begin
count<=count+1;
bit_count<=0;
end

tx_data:
begin
if(bit_count<8)
begin
if(count==7)
begin
bit_count<=bit_count+1;
count<=0;
end
else
count<=count+1;
end
end

tx_end:
begin
bit_count<=0;
count<=count+1;
end

endcase
end

//serial clock generation


always@(posedge clk)begin
case(next_state)
idle:
begin
sclk<=1'b0;
end
tx_start:
begin
if(count<3 || count==7)
sclk<=1'b1;
else
sclk<=1'b0;
end
tx_data:
begin
if(count<3 || count==7)
sclk<=1'b1;
else
sclk<=1'b0;
end
tx_end:
begin
if(count<3)
sclk<=1'b1;
else
sclk<=1'b0;
end
endcase
end

//state table transition


always@(*)begin
case(state)
idle:
begin
chip_select<=1'b1;
mosi<=1'b0;
if(tx_enable)
next_state<=tx_start;
else
next_state<=idle;
end
tx_start:
begin
mosi<=1'b0;
chip_select<=1'b0;
if(count==7)
next_state<=tx_data;
else
next_state<=tx_start;
end
tx_data:
begin
mosi<=send_data[7-bit_count];
if(bit_count<8)
next_state<=tx_data;
else begin
next_state<=tx_end;
mosi<=1'b0;end
end
tx_end:
begin
mosi<=1'b0;
chip_select<=1'b1;
if(count==7)
next_state<=idle;
else
next_state<=tx_end;
end

module spi_slave(
input mosi,
input sclk,
input chip_select,
output[7:0] data_out,
output reg done

);

reg[7:0] data=0;
reg[3:0] bit_count=0;

parameter idle=1'b0,sample=1'b1;
reg state;

always@(negedge sclk)begin
case(state)
idle:
begin
done=1'b0;
if(chip_select)
state<=idle;
else
state<=sample;
end
sample:
begin
if(bit_count<8)
begin
data<={data[6:0],mosi};
bit_count<=bit_count+1;
state<=sample;
end
else
begin
state<=idle;
done<=1'b1;
bit_count<=0;
data<=0;
end
end
default: state<=idle;
endcase
end

assign data_out=data;
endmodule

module top_module(
input clk,
input reset,
input tx_enable,
output done,
output[7:0] data_out,
output sclk,
output chip_select,
output mosi
);

spi_verilog_master
spi_m(.clk(clk),.sclk(sclk),.chip_select(chip_select),.tx_enable(tx_enable),.mosi(mosi),.reset(
reset));
spi_slave
spi_s(.sclk(sclk),.chip_select(chip_select),.mosi(mosi),.done(done),.data_out(data_out));
endmodule

module spi_verilog_tb;

reg clk = 0;
reg rst = 0;
reg tx_enable = 0;
wire mosi;
wire chip_select;
wire sclk;
wire done;
wire[7:0] data_out;

always #5 clk = ~clk;

initial begin
rst = 1;
repeat(5) @(posedge clk);
rst = 0;
end

initial begin
tx_enable = 0;
repeat(5) @(posedge clk);
tx_enable = 1;
end

top_module dut (.clk(clk), .reset(rst), .tx_enable(tx_enable), .mosi(mosi),


.chip_select(chip_select), .sclk(sclk),.data_out(data_out),.done(done));

endmodule

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