Module3

Ch:3 Procedural Statements and

Routines
Ch4: Connecting test bench and DUT
 System Verilog Procedural Statements
• New Operators
– Increment and decrement operator
• Used the same way as C
for (i=0; i<=31; i++)
begin
…
end

• Post-increment/decrement and pre-increment/decrement

j=i++ j is assigned value of i and then i is incremented by 1

j=++i i is incremented by 1 and j is assigned value of i
j=i--; j is assigned value of i and then I is decremented by 1
j=-i; i is decremented by 1 and then j is assigned value of i

• May cause a race condition since ++ and -- operators behave as blocking assignments

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 System Verilog Procedural Statements
for loop variables are declared outside the loop in Verilog
• Concurrent loops interfere with each other

• always @(posedge clock) begin

• For( i=1; i<=1024; i=i+1)
• …
• end
• endmodule

– Enhanced for loops in SV:

– SystemVerilog allows the for loop variables to be
declared inside the loop
• Each variable is local and unique to the loop, hence same name
usage does not cause any interference

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For loop in SV- allows declaration of variable inside ,
multiple variable initialization and multiple modifiers
 System Verilog Procedural Statements
• do…while loop
– A while loop in Verilog might not execute at all
• If the test of control values is false the first time the loop is encountered in the
execution flow

– SystemVerilog adds a do..while loop (similar to C)

• A do while loop executes atleast once
• Control of the loop is tested at the end of each pass of the loop
– All logic for setting the outputs of the loop can be placed inside the loop
– Makes code more concise and intuitive
do <statement or statement block>
while (<condition>);

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break and continue statements
System Verilog Procedural Statements
• break and continue:
• The execution of a break statement leads to the
end of the loop.
• break shall be used in all the loop constructs
(while, do-while, foreach, for, repeat and
forever).
• Execution of continue statement leads to skip the
execution of statements followed by continue
and jump to next loop or iteration value
 Example for break statement
• module break_in_loop;
•
• initial begin
• $display("-----------------------------------------------------------------");
•
• for(int i=0;i<8;i++) begin
• $display("\tValue of i=%0d",i);
• if(i == 4) begin
• $display("\tCalling break,");
• break;
• end
• end
•
• $display("-----------------------------------------------------------------");
• end
• endmodule
• when the loop value equals 4, the break is called this leads to the end of the loop.
 Example for continue statement
• module continue_in_loop;
•
• initial begin
• $display("-----------------------------------------------------------------");
•
• for(int i=0;i<8;i++) begin
•
• if((i > 2) && (i < 7))begin
• $display("\t\tCalling continue,");
• continue;
• end
•
• $display("\t\tAfter Continue\t:: Value of i=%0d",i);
• end
•
• $display("-----------------------------------------------------------------");
•
• end
•
• Endmodule

• when ever the loop value is with in 3 to 6, continue statement will be executed, this leads to skip the execution of
display statement after the continue.
 Task and Function in SV
• A function is meant to do some processing on
the input and return a single value, whereas a
task is more general and can calculate
multiple result values and return them using
output and inout type arguments.
 Task and Function in SV

• Synthesizable Not Synthesizable

 Tasks and functions
• Tasks and Functions provide a means of splitting
code into small parts.
• A Task can contain a declaration of parameters,
input arguments, output arguments, in-out
arguments, registers, events, and zero or more
behavioral statements.
• Static tasks
• Static tasks share the same storage space for all
task calls.
• Automatic tasks
• Automatic tasks allocate unique, stacked storage
for each task call.
• Task declration can be as in verilog 1995/2001 or
can be declared as in C or C++. In SystemVerilog
following rules hold good for any Task declaration
• Default Port Direction : Any port is seen as input,
unless declared as other types. Following are port
types
• input : copy value in at beginning
• output : copy value out at end
• inout : copy in at beginning and out at end
• ref : pass reference
• Default Data TYpe : Unless declared, data types of
ports are of logic type.
• begin..end : There is no need to have begin, end, when
more then one statement is used.
• return : A task can be terminated before endtask, by
usage of return statement.
• Variables : Systemverilog allows to have local static, or
local dynamic variables.
• life time : SystemVerilog allows a task to static or
automatic.
• wire : Wire data type can not be used in port list;
 task arguments in parentheses

• module sv_task;
• int x;
•
• //task to add two integer numbers.
• task sum(input int a,b,output int c);
• c = a+b;
• endtask
•
• initial begin
• sum(10,5,x);
• $display("\tValue of x = %0d",x);
• end
• endmodule
 task arguments in declarations and mentioning directions
• module sv_task;
• int x;
•
• //task to add two integer numbers.
• task sum;
• input int a,b;
• output int c;
• c = a+b;
• endtask
•
• initial begin
• sum(10,5,x);
• $display("\tValue of x = %0d",x);
• end
• endmodule
 Functions
• A Function can contain declarations of range,
returned type, parameters, input arguments,
registers, and events.
• A function without a range or return type
declaration returns a one-bit value
• Any expression can be used as a function call
argument
• Functions cannot contain any time-controlled
statements, and they cannot enable tasks
• Functions can return only one value
• Function declration can be as in verilog 1995/2001 or
can be declared as in C or C++. In SystemVerilog
following rules hold good for any Function declaration
• Default Port Direction : Any port is seen as input,
unless declared as other types. Following are port
types
• input : copy value in at beginning
• output : copy value out at end
• inout : copy in at beginning and out at end
• ref : pass reference
• Default Data TYpe : Unless declared, data types of ports are
of logic type.
• begin..end : There is no need to have begin, end, when
more then one statement is used.
• return : A function can be terminated before endfunction,
by usage of return statement.
• Variables : Systemverilog allows to have local static, or local
dynamic variables.
• life time : SystemVerilog allows a function to be static or
automatic.
• Wire : Wire data type can not be used in port list;
• void : SystemVerilog allows functions to be declared as type
void
 function arguments in parentheses

• module sv_function;
• int x;
• //function to add two integer numbers.
• function int sum(input int a,b);
• sum = a+b;
• endfunction
•
• initial begin
• x=sum(10,5);
• $display("\tValue of x = %0d",x);
• end
• endmodule
 function arguments in declarations and mentioning
directions
• module sv_function;
• int x;
•
• //function to add two integer numbers.
• function int sum;
• input int a,b;
• sum = a+b;
• endfunction
• initial begin
• x=sum(10,5);
• $display("\tValue of x = %0d",x);
• end
• endmodule
 function with return value with the
return keyword
• module sv_function;
• int x;
•
• //function to add two integer numbers.
• function int sum;
• input int a,b;
• return a+b;
• endfunction
•
• initial begin
• x=sum(10,5);
• $display("\tValue of x = %0d",x);
• end
• endmodule
 Void function

• module sv_function;
• int x;
• //void function to display current simulation time
• function void current_time;
• $display("\tCurrent simulation time is %0d",$time);
• endfunction
•
• initial begin
• #10;
• current_time();
• #20;
• current_time();
• end
 discarding function return value

• The function return value must be assigned to

a variable or used in an expression.
• Calling a function without return value
assigned to a variable can result in a warning
message. SystemVerilog void data type is used
to discard a function’s return value without
any warning message.
• module sv_function;
• int x;
• //function to add two integer numbers.
• function int sum;
• input int a,b;
• return a+b;
• endfunction
•
• initial begin
• $display("Calling function with void");
• void'(sum(10,5));
• end
• endmodule
 function call as an expression

• module sv_function;
• int x;
• //function to add two integer numbers.
• function int sum;
• input int a,b;
• return a+b;
• endfunction
• initial begin
• x = 10 + sum(10,5);
• $display("\tValue of x = %0d",x);
• end
• endmodule
 SystemVerilog Tasks and Functions
• Tasks and Functions
– SystemVerilog functions and tasks do not require begin and end
statements
– SystemVerilog adds a return statement
– Void functions do not return a value
– Functions can have output and inout as formal arguments

task reset();
reset_l = 1’b0;
function int add2(int n);
#100
return n + 2;
reset_l = 1’b1;
endfunction
endtask

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 SystemVerilog Tasks and Functions
• Return Statement
– SystemVerilog adds a return statement
• If a return statement is executed that value is returned
else the last value assigned to the function name is the
return value
• A return statement can be used to exit a task or a
function function int add_and_inc (input [31:0] a,b);
add_and_inc=a+b+1; Return has priority over
endfunction returning the value in the
function int add_and_inc (input [31:0] a,b); name of the function
add_and_inc=a+b;
return ++add_and_inc;
endfunction

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 SystemVerilog Tasks and Functions
• Void functions
– Void functions do not return a value
– Output and inout formal arguments allow a void
function to propagate changes to the scope
– A void function can be called like a task but must
adhere to the restriction of function contents

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• typedef struct{
• logic valid;
• logic [7:0] check;
• logic [63:0] data;
• } packet_t;

• function void fill_packet (

• input logic[63:0] data_in, output packet_t data_out);
• data_out.data=data_in;
• endfunction
 SystemVerilog Tasks and Functions
• Passing task/function arguments by name
– SystemVerilog can pass argument values to tasks
or functions using the names of formal arguments
• Reduces errors
– The arguments can be passed in any order
– Syntax for named argument passing is the same as
Verilog’s syntax for named port connections

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• function int divide (input int numerator, denominator);
• if(denominator==0)
• begin
• return 0; always @(posedge clock)
• end result<=divide(b,a)
• else
• return numerator/denominator;
• endfunction

always @(posedge clock)

result<=divide(.deominator(
b),.numerator(a))
 Connecting the Testbench and the
Design
How do I connect my design to the testbench?

Testbench

Design Under
Driver
Test

.*Port, .Name,
?
Interfaces

33
 Connecting the Testbench and the Design
• One way to connect the testbench and the design is to use the
conventional verilog module ports convention

Verilog Connection Review

A_out_signal1 B_in_signal1

A_out_signal2 B_in_signal2
Module A Module B
A_in_signal1 B_out_signal1
A_in_signal2 B_out_signal2

module B (
module A (
input B_in_signal1,
input A_in_signal1,
input B_in_signal2
input A_in_signal2
output B_out_signal1,
output A_out_signal1,
output B_out_signal2,
output A_out_signal2,
); );
…
…
endmodule
endmodule

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 Connecting the Testbench and the Design
• Verilog connection review
– Verilog language connects modules together through module ports
A_out_signal1 conn1 B_in_signal1

A_out_signal2 conn2 B_in_signal2

Module A Module B
A_in_signal1 conn3 B_out_signal1
A_in_signal2 conn4 B_out_signal2

module top (
wire conn1,
wire conn2
wire conn3,
wire conn4,
);
A A_instance1(.A_out_signal1(conn1),
.A_out_signal2(conn2),
.A_in_signal1(conn3),
.A_in_signal2(conn4));
B B_instance1(.B_in_signal1(conn1),
.B_in_signal2(conn2),
.B_out_signal1(conn3),
.B_out_signal2(conn4));
endmodule
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 Connecting the Testbench and the Design
Lets do another example:
Testbench

request [1:0] grant [1:0]

Arbiter
reset clk

module arb_port ( module test (

output logic [1:0] grant, input logic [1:0] grant,
input logic [1:0] request, output logic [1:0] request,
input logic reset, output logic reset,
input logic clk input logic clk
); );
… …
endmodule endmodule

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 System Verilog: .*Port Connections
• Implicit .* port connections
 .* infers connections of all nets and ports of the same name
 For a connection to be inferred the name and the vector sizes should be the
same
 Types connected together should be compatible

module top
logic [1:0] grant,request;
logic clk, reset;
arb_port a1(.grant(grant), .request(request), .reset(reset), .clk(clk));
test t1(.grant(grant), .request(request), .reset(reset), .clk(clk));
…
endmodule

module top
logic [1:0]
grant,request;
logic clk, reset;
arb_port a1(.*);
test t1(.*);
…
endmodule .*Port Connections
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 System Verilog: .Name Connections
• Implicit .name connections
 .name is an abbreviation of named port connections
 .name infers a connection of a net and port of the same name
and same vector sizes
 .name simplifies connections to module instances
 .name can be combined with named port connections

module top
logic [1:0] grant,request;
logic clk, reset;
arb_port a1(.grant, .request, .reset, .clk);
test t1(.grant, .request, .reset, .clk);
…
endmodule

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 Downside of Verilog Connection Conventions
Verilog module port conventions are cumbersome Why?
Lets change the name of a port request to request 1
module arb_port ( module test (
output logic [1:0] grant, input logic [1:0] grant,
input logic [1:0] request1, output logic [1:0] request1,
input logic reset, output logic reset,
input logic clk input logic clk
); );
… …
endmodule endmodule

• Need to change the port list of each module

• Need to change the port list of the connecting module
• Need to change the name in the instantiation of the modules
• Need to change the name everywhere in the hierarchy

What if you forget to change it in someplace?? --> Compilation error!!!!

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 Downside of Verilog Connection Conventions
Verilog connections become especially tedious and
cumbersome for large designs

Internal 10 Instruction Fetch 15 Master

Memory Processor

10 10
main bus

10 10
Test Generator Slave Processor
Number of ports

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 Disadvantages of Verilog Connection Conventions
• Disadvantage of Verilog Module Connections
 Declarations must be duplicated in multiple modules
 Communication protocols must be duplicated in several
modules
 Risk of mismatched declarations
 A change in design specifications can require
modifications in multiple modules

Solution!!!!

SystemVerilog introduces a powerful new port type

called: Interface

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 SystemVerilog Interfaces
• SystemVerilog Interfaces
 SystemVerilog adds a powerful new port type to Verilog, called an
interface.
 An interface allows a number of signals to be grouped together and
represented as a single port
 The declarations of the signals that make up the interface are contained in
a single location.
 Each module that uses these signals then has a single port of the interface
type, instead of many ports with the discrete signals.

Testbench Interface Arbiter

All the signals that are common between the major blocks of the
design are encapsulated in one location- the interface declaration

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 SystemVerilog Interfaces
Using an interface to simplify connections

Testbench Interface Arbiter

request [1:0]
interface arb_if (input bit clk);
logic [1:0] grant, request;
grant [1:0]
reset logic reset;
endinterface
Interface Declaration
clk
module top;
Interface bit clk;
always #5 clk=~clk;
arb_if arbif(clk);
arb a1(arbif);
test t1(arbif);
endmodule: top

Top module using a simple arbiter interface

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 SystemVerilog Interfaces
• Using an interface to simplify connections
interface arb_if (input bit clk);
logic [1:0] grant, request;
logic reset;
endinterface
Interface Declaration

module test (arb_if arbif);

…
initial begin
@(posedge arbif.clk);
arbif.request<=2’b01;
$display (“@%0d: Drove req=01”, $time);
repeat(2) @(posedge arbif.clk);
if(arbif.grant!=2’b01)
$display (“@%0d: a1: grant !=2’b01”, $time);
$finish
end
endmodule: test
test module using a simple arbiter interface

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 SystemVerilog Interfaces
• Connecting interfaces and ports
Signals in an interface are referenced using the port name
<port_name>.<internal_interface_signal_name>

interface arb_if (input bit clk);

logic [1:0] grant, request;
logic reset;
endinterface
Interface Declaration

module top;
bit clk;
always #5 clk=~clk;
arb_if arbif(clk);
arb a1(.grant(arbif.grant),
.request(arbif.request),
.reset(arbif.reset),
.clk(arbif.clk));
test t1(arbif);
endmodule: top

Connecting the arbiter module using ports to the test module using an interface
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 SystemVerilog Interfaces: modports
• Interface modports
 SystemVerilog interfaces provide a means to define different views of the interface
signal
 modport is an abbreviation for module port
 An interface can have any number of modport definitions
 The modport declaration only defines whether the connecting module sees a signal
as an input, output or bidirectional
 By specifying the port directions, modport provides access restrictions
interface arb_if (input bit clk); module arb (abf_if.DUT arbif);
logic [1:0] grant, request; …
logic reset; endmodule
modport TEST(output request,reset, 2. arbiter module with interface using modports
input grant, clk);
modport DUT(input request,reset, clk
output grant); module test (abf_if.TEST arbif);
endinterface …
endmodule
1. Interface Declaration using modports
3. test module with interface using modports

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 SystemVerilog Interfaces
• SystemVerilog interfaces overview
 SystemVerilog interfaces can contain functionality
► They are not just bundle of wires
► Discrete signal and ports for communications can be defined in one
location
► Communication protocols can be defined in the interface
► Protocol checking and other verification routines can be built into the
interface
 SystemVerilog also allows multiple views of the interface to be defined
► For instance the data_bus signal can be defined to be an input,
output or bidirectional port
 SystemVerilog interfaces cannot contain design hierarchy
► cannot contain instances of modules
 SystemVerilog interfaces can be used as a module port
 SystemVerilog interfaces can contain modports
► modports allow modules to see interface differently

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