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Lecture 4

The document discusses transistor symbols and switch level models, focusing on the behavior of series and parallel transistors and the functionality of ideal switches. It explains CMOS technology, including the operation of pull-up and pull-down networks in logic gates, and details the characteristics of CMOS inverters. Key concepts include the states of output in CMOS logic gates and the importance of avoiding contention between networks.

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anusha kulai
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2 views16 pages

Lecture 4

The document discusses transistor symbols and switch level models, focusing on the behavior of series and parallel transistors and the functionality of ideal switches. It explains CMOS technology, including the operation of pull-up and pull-down networks in logic gates, and details the characteristics of CMOS inverters. Key concepts include the states of output in CMOS logic gates and the importance of avoiding contention between networks.

Uploaded by

anusha kulai
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Transistor Symbols and Switch Level Models

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Connection and behavior of series and parallel transistors

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Ideal Switches
•A switch is an electrical component that can break
an electrical circuit, interrupting the current or
diverting it from one conductor to another.
•A pair of contacts is said to be "closed" when
current can flow from one to the other.
•The contacts are said to be “open” if no current
can flow between them at normal voltages
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Assert High/ Assert Low Switches
• Assert-High: Normally open, Push to make

• Assert-Low: Normally Closed, Pull to break

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Series and Parallel connected switches

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Active High and Low Switch

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NMOS, PMOS switches

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CMOS Technology
•Complementary Metal Oxide Semiconductor
•CMOS circuits uses a combination of p-type
and n-type MOSFETs to implement logic
gates and other digital circuits.
•CMOS circuitry dissipates less power.
•Based on Push-Pull Logic
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CMOS Push-Pull Logic
CMOS Push-Pull Network
• pMOS
• “ON” when input is low
• Pushes output high
• nMOS
• “ON” when input is high
• Pulls output low
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When we join a pull-up network to a pull-down network to form a logic gate
they both will attempt to exert a logic level at the output.

Fig: General Logic Circuit using Pull-up and Pull - down network

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• The possible levels at the output are shown in the table.

• The output of a CMOS logic gate can be in four states.


• When both pull-up and pull-down are OFF, the high impedance or floating Z
output state results.
• This is of importance in multiplexers, memory elements, and tristate bus
drivers
• The crowbarred (or contention) X level exists when both pull-up and pull-
down are simultaneously turned ON.
• Contention between the two networks results in an indeterminate output
level and dissipates static power which is an unwanted condition.

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CMOS Logic Gates
• The inverter, NAND, NOR gates are examples of static CMOS logic gates, also
called complementary CMOS gates.
• In general, a static CMOS gate has an nMOS pull-down network to connect the
output to 0 (GND) and pMOS pull-up network to connect the output to (VDD)
• The networks are arranged such that one is ON and the other OFF for any
input pattern.
• The pull-up and pull-down networks in the inverter each consist of a single
transistor.
• Two or more transistors in series are ON only if all of the series transistors are
ON.
• Two or more transistors in parallel are ON if any of the parallel transistors are
ON.
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The Inverter
• A CMOS inverter or NOT gate - using one nMOS
transistor and one pMOS transistor.
• Logic Symbol

• Truth Table

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• Inverter Schematic
15
The bar at the top indicates VDD and the triangle at the bottom
indicates GND.

When the input A is 0, the nMOS transistor is OFF and the pMOS
transistor is ON.

Thus, the output Y is pulled up to 1 because it is connected to


VDD but not to GND.

Conversely, when A is 1, the nMOS is ON, the pMOS is OFF, and Y


is pulled down to ‘0.’

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