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Lecture 5

The document describes the operation of a 2-input NAND gate, which consists of two series nMOS transistors and two parallel pMOS transistors. The output is 0 when both inputs are 1, and 1 when at least one input is 0. It also briefly mentions the construction of k-input NAND gates using multiple nMOS and pMOS transistors.

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anusha kulai
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4 views

Lecture 5

The document describes the operation of a 2-input NAND gate, which consists of two series nMOS transistors and two parallel pMOS transistors. The output is 0 when both inputs are 1, and 1 when at least one input is 0. It also briefly mentions the construction of k-input NAND gates using multiple nMOS and pMOS transistors.

Uploaded by

anusha kulai
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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2 input NAND Gate

1/20/2025 21EC504_VLSI 1
If both inputs are 1, both of the nMOS transistors will be ON and both of the pMOS
transistors will be OFF. Hence, the output will be 0.

Truth Table of NAND Gate


1/20/2025 21EC504_VLSI 2
NAND GATE

• It consists of two series nMOS transistors


between Y and GND and two parallel
pMOS transistors between Y and VDD.
• If either input A or B is 0, at least one of
Schematic the nMOS transistors will be OFF, breaking
the path from Y to GND.
• But at least one of the pMOS transistors
will be ON, creating a path from Y to VDD.
Hence, the output Y will be 1.

Logic Symbol
1/20/2025 21EC504_VLSI 3
2 input NOR Gate

1/20/2025 21EC504_VLSI 4
k-input NAND When any of the When all of the
gates are inputs are 0, the inputs are 1, the
constructed using output is pulled output is pulled
k series nMOS high through the low through the
transistors and k parallel pMOS series nMOS
parallel pMOS transistors. transistors.
transistors. For

1/20/2025 21EC504_VLSI 5

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