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Syllabus VLMR3

The document outlines the course structure for 'Physical Design Fundamentals' at R.V.R. & J.C. College of Engineering, focusing on VLSI design cycles, partitioning, placement, floor planning, and routing techniques. It details course objectives, outcomes, and units covering various aspects of VLSI physical design automation. Learning resources include a primary textbook and several reference books on VLSI design algorithms and structures.

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10 views2 pages

Syllabus VLMR3

The document outlines the course structure for 'Physical Design Fundamentals' at R.V.R. & J.C. College of Engineering, focusing on VLSI design cycles, partitioning, placement, floor planning, and routing techniques. It details course objectives, outcomes, and units covering various aspects of VLSI physical design automation. Learning resources include a primary textbook and several reference books on VLSI design algorithms and structures.

Uploaded by

abhi7416122
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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R.V.R. & J.C. College of Engineering (Autonomous), Guntur-522019, A.P.

R-20

VLMR3 PHYSICAL DESIGN FUNDAMENTALS L T P C Int Ext


3 1 - 4 30 70

COURSE OBJECTIVES:
1. To learn about design cycles.
2. To study various techniques on Partitioning.
3. To understand various techniques on Placement and Floor Planning.
4. To understand various routing techniques and address their problems.

COURSE OUTCOMES:
After successful completion of the course, the students are able to
1. Understand need for VLSI physical design automation.
2. Analyze VLSI automation algorithms for partitioning.
3. Formulate placement, floor planning and pin assignment problems and simulate.
4. Resolve routing issues using various algorithms.

UNIT I [CO:1] (13)

VLSI Physical Design Automation: Introduction, VLSI Design cycle, new trends in VLSI design cycle,
Physical design cycle, new trends in Physical design cycle, Design styles, Full-custom, Standard cell,
Gate arrays, FPGA, Comparison of different design styles, System packaging styles.

UNIT II [CO:2] (12)

Partitioning: Problem formulation, Classification of partitioning algorithms, Group migration algorithms,


Simulated annealing & Evolution, Other partitioning algorithms, Performance driven partitioning.

UNIT III [CO:3] (11)

Floor Planning: Constraint based floor planning, floor planning algorithms for mixed block & cell design.

Placement: Problem formulation, Simulation base placement algorithms, Other placement algorithms.

Pin Assignment: General & channel pin assignment

UNIT IV [CO:4] (12)

Global Routing: Problem formulation, classification of global routing algorithms, Maze routing algorithm,
line probe algorithm, Steiner Tree based algorithms.

Detailed Routing: Problem formulation, classification of routing algorithms, single layer routing
algorithms, two layer channel routing algorithms, three layer channel routing algorithms, and switchbox
routing algorithms.

Over The Cell Routing & Via Minimization: Two layers over the cell routers, constrained & unconstrained
via minimization.

LEARNING RESOURCES:

TEXT BOOK:
Naveed Shervani, “Algorithms for VLSI Physical Design Automation―, Springer Publisher, Third
edition.

REFERENCE BOOK(s):
1. Andrew B.Kahng, Jens Lienig, Igor L. Markov & Jin Hu, "VLSI Physical Design: From Graph
Partitioning to Timing Closure".

B.Tech.(VL)/R-20/2020-2021 Printed through web on 08-04-2025 00:11:59 Page 1/ 2


R.V.R. & J.C. College of Engineering (Autonomous), Guntur-522019, A.P. R-20

2. Christophn Meinel & Thorsten Theobold, "Algorithm and Data Structures for VLSI Design", KAP,
2002.
3. Rolf Drechsheler, "Evolutionary Algorithm for VLSI", Second edition.
4. Trimburger, "Introduction to CAD for VLSI", Kluwer Academic publisher, 2002.

B.Tech.(VL)/R-20/2020-2021 Printed through web on 08-04-2025 00:11:59 Page 2/ 2

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