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10 Performance of Cache Memory

The document discusses the performance of cache memory, including average cost, system access time, and examples of calculations for hit ratios and access times. It also covers cache mapping techniques, including associative, direct, and set-associative mapping, and provides formulas for calculating the number of blocks in main and cache memory. Additionally, it includes examples to illustrate these concepts and calculations.

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18 views8 pages

10 Performance of Cache Memory

The document discusses the performance of cache memory, including average cost, system access time, and examples of calculations for hit ratios and access times. It also covers cache mapping techniques, including associative, direct, and set-associative mapping, and provides formulas for calculating the number of blocks in main and cache memory. Additionally, it includes examples to illustrate these concepts and calculations.

Uploaded by

aaltnazfti
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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LECTURE 10

Computer Architecture

Prepared By :

Firas Abdulrahman Yosif


Computer Architecture

Performance of Cache Memory

1. Average Cost )‫( معدل الكلفة‬

(Measurement of Cache memory performance ( ‫ويستخدم لقياس اداء الذاكرة‬

𝑪𝒄𝑺𝒄 + 𝑪𝒎𝑺𝒎
𝑪𝒔 =
𝐒𝐜 + 𝐒𝐦

: ‫حيث ان‬

Cs: Average cost of system per byte , (main memory plus cache)

Cc: Average cost of cache

Cm: Average cost of main

Sc: Size of cache memory

Sm: Size of main memory

2. System Access Time

Ts= HTc + MTm

M=(1- H) :‫حيث ان‬

Ts: Average system access time

Tc: cache access time

H: hit ratio
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Computer Architecture

M: Miss ratio

Tm: main access time

Example(1): Assume Tc=100 ns , Tm=1000 ns and H=0.9, find Ts?

Solution)
Ts= HTc + (1-H)Tm
Ts= 0.9 * 100 + (1-0.9)*1000
Ts = 190 ns

Example(2): Assume Tc=150 ns , Tm=1500 ns and Ts=250 ns, find H?

Solution)
Ts= HTc + MTm
Ts= HTc + (1-H)Tm
Ts= HTc + Tm - HTm
Ts –Tm = H(Tc –Tm)
𝑻𝒔 − 𝑻𝒎
𝑯=
𝑻𝒄 − 𝑻𝑴

250−1500
𝐻=
150−1500
−1250
𝐻=
−1350
𝑯 = 𝟎. 𝟗𝟐 this computer is perfect

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Computer Architecture

Example(3): Assume Tc=0.000000175 s , Tm=900 ns and H=0.7,

find Ts?

Solution:
Ts= HTc + (1-H)Tm
Ts= 0.7 * 175*10-9 + (1-0.7)*900
Ts= 392.5 ns
Example(4): Assume Tc=300 sec , Tm=1800 sec and Ts=1450 sec, find Hit
ratio?

Solution)
Ts= HTc + MTm
Ts= HTc + (1-H)Tm
Ts= HTc + Tm – HTm
Ts –Tm = H(Tc – Tm)
𝑻𝒔−𝑻𝒎
𝑯 = 𝑻𝒄−𝑻𝒎
1450 − 1800
𝐻=
300 − 1800
−350
𝐻=
−500
𝑯 = 𝟎. 𝟕 this computer isn’t perfect
‫) سريع‬Tc( ‫) انه كلما كان زمن الوصول للمعلومة في الكاش‬4( ‫) والمثال‬2( ‫نالحظ من خالل المثال‬
‫ قريب من الواحد وكانت فرصة العثور على المعلومة اكبر وكانت الحاسبة‬Hit ratio ‫كلما كان الـ‬
. perfect ‫مثالية‬

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Computer Architecture

Cache Mapping

 Elements of Cache Design


 —cache Size
 —Mapping Technique
direct, associative, set associative
 —Replacement Algorithm
LRU, FIFO, LFU, Random
 —Write Policy
Write through, Write back
 —Number of Caches
single or two level

 Mapping Technique

The transformation of data from main memory to cache memory is referred to


as a mapping process.
Cache Memory Mapping: It means how the main memory data will get
mapped into the cache memory, it is copy not moved.
‫ هي تقنية او الية ينفذها نظام التشغيل الرسال نسخة من البيانات‬Cache Memory Mapping ‫الـ‬
main ‫ القادم من الـ‬Block ‫ عن طريق ارسال وتحديد الـ‬main memory ‫المخزونة داخل الـ‬
‫ سوف يخزن وذلك لكي تكون عملية البحث عن المعلومة‬cache ‫ داخل الـ‬slot ‫ في اي‬memory
.‫ من قبل المعالج تكون منظمة وسهلة‬cache ‫داخل الـ‬

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Computer Architecture

 Cache Mapping Techniques

Cache mapping is performed using following three different techniques:

1-Associative mapping

2-Direct mapping

3-Set-associative mapping
The following diagram illustrates the mapping process:

Block diagram illustrate cache mapping

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Computer Architecture

NOTES

 Main memory is divided into equal size partitions called as blocks .


 Cache memory is divided into partitions having same size as that of blocks
called as lines or slot.
 During cache mapping, block of main memory is simply copied to the cache.

:‫ بأستخدام القانون التالي‬main memory ‫ الموجودة في الـ‬blocks ‫يتم حساب عدد الـ‬
𝒔𝒊𝒛𝒆 𝒐𝒇 𝒎𝒆𝒎𝒐𝒓𝒚 𝑺𝒎
1. No. of block in main memory = = 𝑺𝒃𝒍𝒐𝒄𝒌
𝒔𝒊𝒛𝒆 𝒐𝒇 𝒃𝒍𝒐𝒄𝒌

:‫ بأستخدام القانون التالي‬cache memory ‫ الموجودة في الـ‬slots ‫يتم حساب عدد الـ‬
𝒔𝒊𝒛𝒆 𝒐𝒇 𝒄𝒂𝒄𝒉𝒆 𝑺𝒄
2. No. of block in cache memory = = 𝑺𝒃𝒍𝒐𝒄𝒌
𝒔𝒊𝒛𝒆 𝒐𝒇 𝒔𝒍𝒐𝒕

:memory size ‫ عن طريق حجم الذاكرة‬no. of address bus ‫يتم حساب‬


3. Size of memory = 𝟐𝒏𝒐.𝒐𝒇 𝒂𝒅𝒅𝒓𝒆𝒔𝒔 𝒃𝒖𝒔

Example(1) :Suppose cache size= 4K byte, memory size= 32kbyte, data is to


be transferred between main memory and cache in blocks of 16 bytes. Find:
1. No. of block in main memory
2. No. of block in cache memory
3. No. of address bus

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Computer Architecture

Solution)
𝑠𝑖𝑧𝑒 𝑜𝑓 𝑚𝑒𝑚𝑜𝑟𝑦 32𝑘
1. No. of block in main memory = = = 215/ 24
𝑠𝑖𝑧𝑒 𝑜𝑓 𝑏𝑙𝑜𝑐𝑘 16
=211=2k
𝑠𝑖𝑧𝑒 𝑜𝑓 𝑐𝑎𝑐ℎ𝑒 4𝑘
2. No. of block in cache memory = = = 212/24 = 28= 256
𝑠𝑖𝑧𝑒 𝑜𝑓 𝑠𝑙𝑜𝑡 16

3. Size of memory = 2𝑛𝑜.𝑜𝑓 𝑎𝑑𝑑𝑟𝑒𝑠𝑠 𝑏𝑢𝑠 = 32k = 215


No. of address bus = 15

Example(2): Suppose cache size= IK byte, memory size= 64kbyte, data is to


be transferred between main memory and cache in blocks of 8 bytes. Find:
1. No. of block in main memory
2. No. of block in cache memory
3. No. of address bus

Solution)
𝑠𝑖𝑧𝑒 𝑜𝑓 𝑚𝑒𝑚𝑜𝑟𝑦 64𝑘
1. No. of block in block memory = = = 216/23=213=8k
𝑠𝑖𝑧𝑒 𝑜𝑓 𝑏𝑙𝑜𝑐𝑘 8
𝑠𝑖𝑧𝑒 𝑜𝑓 𝑐𝑎𝑐ℎ𝑒 1𝑘
2. No. of block in cache memory = = =210/23=27=128
𝑠𝑖𝑧𝑒 𝑜𝑓 𝑠𝑙𝑜𝑡 8

3. Size of memory = 2𝑛𝑜.𝑜𝑓 𝑎𝑑𝑑𝑟𝑒𝑠𝑠 𝑏𝑢𝑠 = 64k =216


No. of address bus = 16

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