AVR ATMEGA16 MICROCONTROLLER

The ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega16 achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power
consumption versus processing speed.

Features:
 High-performance, Low-power Atmel AVR 8-bit Microcontroller
 Advanced RISC Architecture
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
 High Endurance Non-volatile Memory segments
– 16 Kbytes of In-System Self-programmable Flash program memory
– 512 Bytes EEPROM
– 1 Kbyte Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
 In-System Programming by On-chip Boot Program
 True Read-While-Write Operation
– Programming Lock for Software Security
 JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG
Interface
 Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
 – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
 Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
 8 Single-ended Channels
 7 Differential Channels in TQFP Package Only
 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
 Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
and Extended Standby
 I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
 Operating Voltages
– 2.7V - 5.5V for ATmega16L
– 4.5V - 5.5V for ATmega16
 Speed Grades
0 - 8 MHz for ATmega16L
– 0 - 16 MHz for ATmega16
 Power Consumption @ 1 MHz, 3V, and 25°C for ATmega16L
– Active: 1.1 mA
– Idle Mode: 0.35 mA
 – Power-down Mode: < 1 μA

In order to maximize performance and parallelism, the AVR uses Harvard architecture with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next
instruction is fetched from the program memory. This concept enables instructions to be
executed in every clock cycle. The program memory is In-System Reprogrammable Flash
memory.

The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two
independent registers to be accessed in one single instruction executed in one clock cycle. The
resulting architecture is more code efficient while achieving throughputs up to ten times faster
than conventional CISC microcontrollers.
Pin Descriptions
VCC: Digital supply voltage.
GND: Ground.
Port A (PA7-PA0):
Port A serves as the analog inputs to the A/D Converter. Port A also serves as an 8-bit bi-
directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up
resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics
with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are
externally pulled low, they will source current if the internal pull-up resistors are activated. The
Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port B (PB7-PB0):
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even
if the clock is not running. Port B also serves the functions of various special features of the
ATmega16.

Port C (PC7-PC0):
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even
if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PC5
(TDI), PC3 (TMS) and PC2 (TCK) will be activated even if a reset occurs. Port C also serves the
functions of the JTAG interface and other special features of theATmega16.

Port D (PD7-PD0):
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit).
The Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even
if the clock is not running. Port D also serves the functions of various special features of the
ATmega16.

RESET: Reset Input.

A low level on this pin for longer than the minimum pulse length will generate a reset, even if
the clock is not running. Shorter pulses are not guaranteed to generate a reset.

XTAL1: Input to the inverting Oscillator amplifier and input to the internal clock operating
circuit.
XTAL2: Output from the inverting Oscillator amplifier.
AVCC: AVCC is the supply voltage pin for Port A and the A/D Converter. It should be
externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be
connected to VCC through a low-pass filter.
AREF: AREF is the analog reference pin for the A/D Converter.

AVR CPU Core

Introduction This section discusses the AVR core architecture in general. The main function of
the CPU core is to ensure correct program execution. The CPU must therefore be able to access
memories, perform calculations, control peripherals, and handle interrupts.
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next
instruction is pre-fetched from the program memory. This concept enables instructions to be
executed in every clock cycle. The program memory is In-System Reprogrammable Flash
memory.

The fast-access Register File contains 32 × 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a
typical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can
be used as three 16-bit indirect address register pointers for Data Space addressing – enabling
efficient address calculations. One of the address pointers can also be used as an address pointer
for look up tables in Flash Program memory.

The ALU supports arithmetic and logic operations between registers or between a constant and a
register. Single register operations can also be executed in the ALU. After an arithmetic
operation, the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word
format.

Every program memory address contains a 16-bit or 32-bit instruction. Program Flash memory
space is divided in two sections, the Boot program section and the Application Program section.
Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction
that writes into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack
Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture. The memory
spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt
module has its control registers in the I/O space with an additional global interrupt enable bit in
the Status Register. All interrupts have a separate interrupt vector in the interrupt vector table.
The interrupts have priority in accordance with their interrupt vector position. The lower the
interrupt vector address, the higher the priority. The I/O memory space contains 64 addresses for
CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory
can be accessed directly, or as the Data Space locations following those of the Register File, $20
- $5F.

Stack Pointer:
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to
the top of the Stack. Note that the Stack is implemented as growing from higher memory
locations to lower memory locations. This implies that a Stack PUSH command decreases the
Stack Pointer. If software reads the Program Counter from the Stack after a call or an interrupt,
unused bits (15:13) should be masked out.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks
are located. This Stack space in the data SRAM must be defined by the program before any
subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point
above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the
PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack
with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped
from the Stack with the POP instruction, and it is incremented by two when data is popped from
the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack
Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is
implementation dependent. Note that the data space in some implementations of the AVR
architecture is so small that only SPL is needed. In this case, the SPH Register will not be
present.
Instruction
Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk CPU, directly generated from the selected clock source for
the chip. No internal clock division is used. The below figure shows the parallel instruction
fetches and instruction executions enabled by the Harvard architecture and the fast-access
Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with
the corresponding unique results for functions per cost, functions per clocks, and functions per
power-unit.

The below figure shows the internal timing concept for the Register File. In a single clock cycle
an ALU operation using two register operands is executed, and the result is stored back to the
destination register.
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate reset
vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global
Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the
Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or
BLB12 are programmed. This feature improves software security.

The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The lower the address the higher is the priority level. RESET has the highest
priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be
moved to the start of the Boot Flash section by setting the IVSEL bit in the General Interrupt
Control Register (GICR). The Reset Vector can also be moved to the start of the boot Flash
section by programming the BOOTRST Fuse.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are
disabled. The user software can write logic one to the I-bit to enable nested interrupts. All
enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set
when a Return from Interrupt instruction – RETI – is executed. There are basically two types of
interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts,
the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt
handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also
be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition
occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and
remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or
more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the
corresponding Interrupt Flag(s) will be set and remembered until the global interrupt enable bit is
set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it
will always return to the main program and execute one more instruction before any pending
interrupt is served.

In-System Reprogrammable Flash Program Memory

The ATmega16 contains 16 Kbytes On-chip In-System Reprogrammable Flash memory for
program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 8K
× 16. For software security, the Flash Program memory space is divided into two sections, Boot
Program section and Application Program section. The Flash memory has an endurance of at
least 10,000 write/erase cycles. The ATmega16 Program Counter (PC) is 13 bits wide, thus
addressing the 8K program memory locations.
System Clock and Clock Options Clock Systems and their Distribution
The below figure presents the principal clock systems in the AVR and their distribution. All of
the clocks need not be active at a given time. In order to reduce power consumption, the clocks
to modules not being used can be halted by using different sleep modes.
CPU Clock – clkCPU The CPU clock is routed to parts of the system concerned with operation
of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.

I/O Clock – clkI/O The I/O clock is used by the majority of the I/O modules, like
Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module,
but note that some external interrupts are detected by asynchronous logic, allowing such
interrupts to be detected even if the I/O clock is halted. Also note that address recognition in the
TWI module is carried out asynchronously when clkI/O is halted, enabling TWI address
reception in all sleep modes.

Flash Clock – clkFLASH The Flash clock controls operation of the Flash interface. The Flash
clock is usually active simultaneously with the CPU clock.
Asynchronous Timer Clock – clkASY
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly
from an external 32 kHz clock crystal. The dedicated clock domain allows using this
Timer/Counter as a real-time counter even when the device is in sleep mode.

ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting
the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more
accurate ADC conversion results.

Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting
amplifier which can be configured for use as an On-chip Oscillator. Either a quartz crystal or a
ceramic resonator may be used. The CKOPT Fuse selects between two different Oscillator
amplifier modes. When CKOPT is programmed, the Oscillator output will oscillate will a full
railto- rail swing on the output. This mode is suitable when operating in a very noisy
environment or when the output from XTAL2 drives a second clock buffer. This mode has a
wide frequency range. When CKOPT is unprogrammed, the Oscillator has a smaller output
swing. This reduces power consumption considerably. This mode has a limited frequency range
and it can not be used to drive other clock buffers.

For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and 16 MHz
with CKOPT programmed. C1 and C2 should always be equal for both crystals and resonators.
The optimal value of the capacitors depends on the crystal or resonator in use, the amount of
stray capacitance, and the electromagnetic noise of the environment.
The Oscillator can operate in three different modes, each optimized for a specific frequency
range. The operating mode is selected by the fuses.

Analog to Digital Converter

Features
• 10-bit Resolution
• 0.5 LSB Integral Non-linearity
• ±2 LSB Absolute Accuracy
• 13 μs- 260 μs Conversion Time
• Up to 15 kSPS at Maximum Resolution
• 8 Multiplexed Single Ended Input Channels
• 7 Differential Input Channels
• 2 Differential Input Channels with Optional Gain of 10x and 200x
• Optional Left adjustment for ADC Result Readout
• 0 - VCC ADC Input Voltage Range
• Selectable 2.56V ADC Reference Voltage
• Free Running or Single Conversion Mode
• ADC Start Conversion by Auto Triggering on Interrupt Sources
• Interrupt on ADC Conversion Complete
• Sleep Mode Noise Canceler

The ATmega16 features a 10-bit successive approximation ADC. The ADC is connected to an
8-channel Analog Multiplexer which allows 8 single-ended voltage inputs constructed from the
pins of Port A. The single-ended voltage inputs refer to 0V (GND). The device also supports 16
differential voltage input combinations. Two of the differential inputs (ADC1, ADC0 and ADC3,
ADC2) are equipped with a programmable gain stage, providing amplification steps of 0 dB
(1x), 20 dB (10x), or 46 dB (200x) on the differential input voltage before the A/D conversion.
Seven differential analog input channels share a common negative terminal (ADC1), while any
other ADC input can be selected as the positive input terminal. If 1x or 10x gain is used, 8-bit
resolution can be expected. If 200x gain is used, 7-bit resolution can be expected.

The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is
held at a constant level during conversion. The ADC has a separate analog supply voltage pin,
AVCC. AVCC must not differ more than ±0.3V from VCC.

Internal reference voltages of nominally 2.56V or AVCC are provided On-chip. The voltage
reference may be externally decoupled at the AREF pin by a capacitor for better noise
performance.
Operation The ADC converts an analog input voltage to a 10-bit digital value through
successive approximation. The minimum value represents GND and the maximum value
represents the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V
reference voltage may be connected to the AREF pin by writing to the REFSn bits in the
ADMUX Register. The internal voltage reference may thus be decoupled by an external
capacitor at the AREF pin to improve noise immunity.

The analog input channel and differential gain are selected by writing to the MUX bits in
ADMUX. Any of the ADC input pins, as well as GND and a fixed bandgap voltage reference,
can be selected as single ended inputs to the ADC. A selection of ADC input pins can be selected
as positive and negative inputs to the differential gain amplifier. If differential channels are
selected, the differential gain stage amplifies the voltage difference between the selected input
channel pair by the selected gain factor. This amplified value then becomes the analog input to
the ADC. If single ended channels are used, the gain amplifier is bypassed altogether.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and
input channel selections will not go into effect until ADEN is set. The ADC does not consume
power when ADEN is cleared, so it is recommended to switch off the ADC before entering
power saving sleep modes.

The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and
ADCL. By default, the result is presented right adjusted, but can optionally be presented left
adjusted by setting the ADLAR bit in ADMUX. If the result is left adjusted and no more than 8-
bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then
ADCH, to ensure that the content of the Data Registers belongs to the same conversion. Once
ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been
read, and a conversion completes before ADCH is read, neither register is updated and the result
from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL
Registers is re-enabled. The ADC has its own interrupt which can be triggered when a
conversion completes. When ADC access to the Data Registers is prohibited between reading of
ADCH and ADCL, the interrupt will trigger even if the result is lost.