555 TIMER:

The 555 is an integrated circuit (chip) implementing a variety of timer and multivibrator
applications. The IC was designed and invented by Hans R. Camenzind. It was designed
in 1970 and introduced in 1971 by Signetics (later acquired by Philips). The original
name was the SE555/NE555 and was called "The IC Time Machine". It is still in wide
use, thanks to its ease of use, low price and good stability. As of 2003, 1 billion units are
manufactured every year.

The 555 timer is one of the most popular and versatile integrated circuits ever produced.
It includes 23 transistors, 2 diodes and 16 resistors on a silicon chip installed in an 8-pin
mini dual-in-line package (DIP-8). The 556 is a 14-pin DIP that combines two 555s on a
single chip. The 558 is a 16-pin DIP that combines four, slightly modified, 555s on a
single chip (DIS & THR are connected internally, TR is falling edge sensitive instead of
level sensitive). Also available are ultra-low power versions of the 555 such as the 7555
and TLC555. The 7555 requires slightly different wiring using fewer external
components and less power.

The 555 has three operating modes:

 Monostable mode: in this mode, the 555 functions as a "one-shot". Applications

include timers, missing pulse detection, bouncefree switches, touch switches,
Frequency Divider, Capacitance Measurement, Pulse Width Modulation (PWM)
etc
 Astable - Free Running mode: the 555 can operate as an oscillator Uses include
LED and lamp flashers, pulse generation, logic clocks, tone generation, security
alarms, pulse position modulation, etc.

 Bistable mode: the 555 can operate as a flip-flop, if the DIS pin is not connected
and no capacitor is used. Uses include bounce free latched switches, etc.
 Fig: 555 timer

Pin diagram of 555 Timer

The 555 Timer IC is made to operate in astable mode in this project. In astable mode,
there is no need for an external trigger. The timer operates between two voltage levels
during the on time.

555 Packages:

The 555, in fig. 1 and fig. 2 above, come in two packages, either the round metal-can
called the 'T' package or the more familiar 8-pin DIP 'V' package. About 20-years ago the
metal-can type was pretty much the standard (SE/NE types). The 556 timer is a dual 555
version and comes in a 14-pin DIP package, the 558 is a quad version with four 555's
also in a 14 pin DIP case.

The supply current, when the output is 'high', is typically 1 milli-amp (mA) or less. The
initial monostable timing accuracy is typically within 1% of its calculated value, and
exhibits negligible (0.1%/V) drift with supply voltage. Thus long-term supply variations
can be ignored, and the temperature variation is only 50ppm/°C (0.005%/°C).

All IC timers rely upon an external capacitor to determine the off-on time intervals of the
output pulses. As you recall from your study of basic electronics, it takes a finite period
of time for a capacitor (C) to charge or discharge through a resistor (R). Those times are
clearly defined and can be calculated given the values of resistance and capacitance.

The basic RC charging circuit is shown in fig. 4. Assume that the capacitor is initially
discharged. When the switch is closed, the capacitor begins to charge through the resistor.
The voltage across the capacitor rises from zero up to the value of the applied DC
voltage. The charge curve for the circuit is shown in fig. 6. The time that it takes for the
capacitor to charge to 63.7% of the applied voltage is known as the time constant (t). That
time can be calculated with the simple expression:

t=RXC
Fig 4: Basic RC charging circuit
Fig: Inside the 555 Timer
Fig: 555 Schematic
Specifications of 555 timer:

Supply voltage (VCC) 4.5 to 15 V

Supply current (VCC = +5 V) 3 to 6 mA

Supply current (VCC = +15 V) 10 to 15 mA

Output current (maximum) 200 mA

Power dissipation 600 mW

Operating temperature 0 to 70 °C

Pin description:

1 GND Ground, low level ( OV ) ZERO VOLTS.

2 TR A short pulse high → low on the trigger starts the timer.

3 Q During a timing interval, the output stays at +Vcc.

4 R A timing interval can be interrupted by applying a reset pulse to low (0V).

5 CV Control voltage allows access to the internal voltage divider (2/3 VCC).

6 THR The threshold at which the interval ends.

7 DIS Connected to a capacitor whose discharge time will influence the timing
interval.

8 V+, The positive supply voltage which must be between 3 and 15 V.

 Vcc

Pin 1 (Ground): The ground (or common) pin is the most-negative supply potential of
the device, which is normally connected to circuit common (ground) when operated from
positive supply voltages.

Pin 2 (Trigger): This pin is the input to the lower comparator and is used to set the
latch, which in turn causes the output to go high. This is the beginning of the timing
sequence in monostable operation. Triggering is accomplished by taking the pin from
above to below a voltage level of 1/3 V+ (or, in general, one-half the voltage appearing at
pin 5). The action of the trigger input is level-sensitive, allowing slow rate-of-change
waveforms, as well as pulses, to be used as trigger sources. The trigger pulse must be of
shorter duration than the time interval determined by the external R and C. If this pin is
held low longer than that, the output will remain high until the trigger input is driven high
again. One precaution that should be observed with the trigger input signal is that it must
not remain lower than 1/3 V+ for a period of time longer than the timing cycle. If this is
allowed to happen, the timer will re-trigger itself upon termination of the first output
pulse. Thus, when the timer is driven in the monostable mode with input pulses longer
than the desired output pulse width, the input trigger should effectively be shortened by
differentiation. The minimum-allowable pulse width for triggering is somewhat
dependent upon pulse level, but in general if it is greater than the 1uS (micro-Second),
triggering will be reliable. A second precaution with respect to the trigger input concerns
storage time in the lower comparator. This portion of the circuit can exhibit normal turn-
off delays of several microseconds after triggering; that is, the latch can still have a
trigger input for this period of time after the trigger pulse. In practice, this means the
minimum monostable output pulse width should be in the order of 10uS to prevent
possible double triggering due to this effect. The voltage range that can safely be applied
to the trigger pin is between V+ and ground. A dc current, termed the trigger current,
must also flow from this terminal into the external circuit. This current is typically 500nA
(nano-amp) and will define the upper limit of resistance allowable from pin 2 to ground.
For an astable configuration operating at V+ = 5 volts, this resistance is 3 Mega-ohm; it
can be greater for higher V+ levels.

Pin 3 (Output): The output of the 555 comes from a high-current totem-pole stage made
up of transistors Q20 - Q24. Transistors Q21 and Q22 provide drive for source-type
loads, and their Darlington connection provides a high-state output voltage about 1.7
volts less than the V+ supply level used. Transistor Q24 provides current-sinking
capability for low-state loads referred to V+ (such as typical TTL inputs). Transistor Q24
has a low saturation voltage, which allows it to interface directly, with good noise
margin, when driving current-sinking logic. Exact output saturation levels vary markedly
with supply voltage, however, for both high and low states. At a V+ of 5 volts, for
instance, the low state Vce(sat) is typically 0.25 volts at 5 mA. Operating at 15 volts,
however, it can sink 200mA if an output-low voltage level of 2 volts is allowable (power
dissipation should be considered in such a case, of course). High-state level is typically
3.3 volts at V+ = 5 volts; 13.3 volts at V+ = 15 volts. Both the rise and fall times of the
output waveform are quite fast, typical switching times being 100nS. The state of the
output pin will always reflect the inverse of the logic state of the latch. Since the latch
itself is not directly accessible, this relationship may be best explained in terms of latch-
input trigger conditions. To trigger the output to a high condition, the trigger input is
momentarily taken from a higher to a lower level. This causes the latch to be set and the
output to go high. Actuation of the lower comparator is the only manner in which the
output can be placed in the high state. The output can be returned to a low state by
causing the threshold to go from a lower to a higher level [see "Pin 6 - Threshold"],
which resets the latch. The output can also be made to go low by taking the reset to a low
state near ground [see "Pin 4 - Reset"]. The output voltage available at this pin is
approximately equal to the Vcc applied to pin 8 minus 1.7V.

Pin 4 (Reset): This pin is also used to reset the latch and return the output to a low state.
The reset voltage threshold level is 0.7 volt, and a sink current of 0.1mA from this pin is
required to reset the device. These levels are relatively independent of operating V+
level; thus the reset input is TTL compatible for any supply voltage. The reset input is an
overriding function; that is, it will force the output to a low state regardless of the state of
either of the other inputs. It may thus be used to terminate an output pulse prematurely, to
gate oscillations from "on" to "off", etc. Delay time from reset to output is typically on
the order of 0.5 µS, and the minimum reset pulse width is 0.5 µS. Neither of these figures
is guaranteed, however, and may vary from one manufacturer to another. In short, the
reset pin is used to reset the flip-flop that controls the state of output pin 3. The pin is
activated when a voltage level anywhere between 0 and 0.4 volt is applied to the pin. The
reset pin will force the output to go low no matter what state the other inputs to the flip-
flop are in. When not used, it is recommended that the reset input be tied to V+ to avoid
any possibility of false resetting.

Pin 5 (Control Voltage): This pin allows direct access to the 2/3 V+ voltage-divider
point, the reference level for the upper comparator. It also allows indirect access to the
lower comparator, as there is a 2:1 divider (R8 - R9) from this point to the lower-
comparator reference input, Q13. Use of this terminal is the option of the user, but it does
allow extreme flexibility by permitting modification of the timing period, resetting of the
comparator, etc. When the 555 timer is used in a voltage-controlled mode, its voltage-
controlled operation ranges from about 1 volt less than V+ down to within 2 volts of
ground (although this is not guaranteed). Voltages can be safely applied outside these
limits, but they should be confined within the limits of V+ and ground for reliability. By
applying a voltage to this pin, it is possible to vary the timing of the device independently
of the RC network. The control voltage may be varied from 45 to 90% of the Vcc in the
monostable mode, making it possible to control the width of the output pulse
independently of RC. When it is used in the astable mode, the control voltage can be
varied from 1.7V to the full Vcc. Varying the voltage in the astable mode will produce a
frequency modulated (FM) output. In the event the control-voltage pin is not used, it is
recommended that it be bypassed, to ground, with a capacitor of about 0.01uF (10nF) for
immunity to noise, since it is a comparator input. This fact is not obvious in many 555
circuits since I have seen many circuits with 'no-pin-5' connected to anything, but this is
the proper procedure. The small ceramic cap may eliminate false triggering.
Pin 6 (Threshold): Pin 6 is one input to the upper comparator (the other being pin 5)
and is used to reset the latch, which causes the output to go low. Resetting via this
terminal is accomplished by taking the terminal from below to above a voltage level of
2/3 V+ (the normal voltage on pin 5). The action of the threshold pin is level sensitive,
allowing slow rate-of-change waveforms. The voltage range that can safely be applied to
the threshold pin is between V+ and ground. A dc current, termed the threshold current,
must also flow into this terminal from the external circuit. This current is typically 0.1µA,
and will define the upper limit of total resistance allowable from pin 6 to V+. For either
timing configuration operating at V+ = 5 volts, this resistance is 16 Mega-ohm. For 15
volt operation, the maximum value of resistance is 20 MegaOhms.

Pin 7 (Discharge): This pin is connected to the open collector of a npn transistor (Q14),
the emitter of which goes to ground, so that when the transistor is turned "on", pin 7 is
effectively shorted to ground. Usually the timing capacitor is connected between pin 7
and ground and is discharged when the transistor turns "on". The conduction state of this
transistor is identical in timing to that of the output stage. It is "on" (low resistance to
ground) when the output is low and "off" (high resistance to ground) when the output is
high. In both the monostable and astable time modes, this transistor switch is used to
clamp the appropriate nodes of the timing network to ground. Saturation voltage is
typically below 100mV (milli-Volt) for currents of 5 mA or less, and off-state leakage is
about 20nA (these parameters are not specified by all manufacturers, however).
Maximum collector current is internally limited by design, thereby removing restrictions
on capacitor size due to peak pulse-current discharge. In certain applications, this open
collector output can be used as an auxiliary output terminal, with current-sinking
capability similar to the output (pin 3).

Pin 8 (V +): The V+ pin (also referred to as Vcc) is the positive supply voltage terminal
of the 555 timer IC. Supply-voltage operating range for the 555 is +4.5 volts (minimum)
to +16 volts (maximum), and it is specified for operation between +5 volts and +15 volts.
The device will operate essentially the same over this range of voltages without change in
timing period. Actually, the most significant operational difference is the output drive
capability, which increases for both current and voltage range as the supply voltage is
increased. Sensitivity of time interval to supply voltage change is low, typically 0.1% per
volt. There are special and military devices available that operate at voltages as high as
18 volts.

Operating Modes:

The 555 timer has two basic operational modes: one shot and astable. In the one-shot
mode, the 555 acts like a monostable multivibrator. A monostable is said to have a single
stable state--that is the off state. Whenever it is triggered by an input pulse, the
monostable switches to its temporary state. It remains in that state for a period of time
determined by an RC network. It then returns to its stable state. In other words, the
monostable circuit generates a single pulse of a fixed time duration each time it receives
and input trigger pulse. Thus the name one-shot. One-shot multivibrators are used for
turning some circuit or external component on or off for a specific length of time. It is
also used to generate delays. When multiple one-shots are cascaded, a variety of
sequential timing pulses can be generated. Those pulses will allow you to time and
sequence a number of related operations.

The other basic operational mode of the 555 is as and astable multivibrator. An astable
multivibrator is simply and oscillator. The astable multivibrator generates a continuous
stream of rectangular off-on pulses that switch between two voltage levels. The
frequency of the pulses and their duty cycle are dependent upon the RC network values.
555 Timer as an Astable Multivibrator:

Astable multivibrator

In Astable mode, both transistors are coupled to each other through capacitors.
Whichever transistor is off at any moment cannot remain off indefinitely and its base will
become forward biased as that capacitor charges towards +5 volts. Once that happens,
that transistor will turn on, thereby turning the other one off.

Astable multivibrator (Q1 saturated).

Let us assume that Q1 saturates and Q2 is in cutoff because the circuit is symmetrical
that is, R1 = R4, R2 = R3, C1 = C2, and Q1 = Q2. It is not possible to say which
transistor will actually conduct when the circuit is energized. For this reason, either of the
transistors may be assumed to conduct for circuit analysis purposes.

Essentially, all the current in the circuit flows through Q1. The transistor Q1 offers
almost no resistance to current flow. Notice that capacitor C1 is charging. Since Q1 offers
almost no resistance in its saturated state, the rate of charge of C1 depends only on the
time constant of R2 and C1. It can be noticed that the right-hand side of capacitor C1 is
connected to the base of transistor Q2, which is now at cutoff. The right-hand side of
capacitor C1 is becoming increasingly negative. If the base of Q2 becomes sufficiently
negative, Q2 will conduct. After a certain period of time, the base of Q2 will become
sufficiently negative to cause Q2 to change states from cutoff to conduction. The time
necessary for Q2 to become saturated is determined by the time constant R2C1.

The negative voltage accumulated on the right side on capacitor C1 has caused Q2 to
conduct. Now the following sequence of events takes place almost instantaneously. Q2
starts conducting and quickly saturates, and the voltage at output 2 changes from
approximately -VCC to approximately 0 volts. This change in voltage is coupled through
C2 to the base of Q1, forcing Q1 to cutoff. Now Q1 is in cutoff and Q2 is in saturation.

Astable multivibrator (Q2 saturated).

Rectangular waves.

The output from this 555 Timer IC is taken at pin 3. This output is connected to the motor
driver which is L293D.
The ON and OFF time of this timer in astable mode will be determined by the Resistor
and Capacitor components used in the circuit.

The ON time is given by the formula: Ton= 0.69 (R1+R2) C

And the OFF time as: Toff= 0.69 (R2) C.

Depending on these ON and OFF times, the speed of the motor can be varied. The ON
time can be varied when the value of resistor R1 is varied. To make the motor rotate at
maximum speed, the resistor R1 can be varied upto the maximum level.

555 TIMER AS MONOSTABLE MULTIVIBRATOR:

Theory:-

The 555 timer configured for monostable operation is shown in the figure.
Monostable multivibrator often called a one shot multivibrator is a pulse generating
circuit in which the duration of this pulse is determined by the RC network connected
externally to the 555 timer. In a stable or standby state, the output of the circuit is
approximately zero or a logic-low level. When external trigger pulse is applied output is
forced to go high ( VCC). The time for which output remains high is determined by the
external RC network connected to the timer. At the end of the timing interval, the output
automatically reverts back to its logic-low stable state. The output stays low until trigger
pulse is again applied. Then the cycle repeats. The monostable circuit has only one stable
state (output low) hence the name monostable.

The internal diagram for a 555 timer is shown in the figure.

Pin1: Ground. All voltages are measured with respect to this terminal.
Pin2: Trigger. The output of the timer depends on the amplitude of the external trigger
pulse applied to this pin. The output is low if the voltage at this pin is greater than 2/3
VCC. When a negative going pulse of amplitude greater than 1/3 VCC is applied to this pin,
comparator 2 output goes low, which inturn switches the output of the timer high. The
output remains high as long as the trigger terminal is held at a low voltage.

Pin3: Output. There are two ways by which a load can be connected to the output
terminal: either between pin 3 and ground or between pin3 and supply voltage +VCC.
When the output is low the load current flows through the load connected between pin3
and +VCC into the output terminal and is called sink current. The current through the
grounded load is zero when the output is low. For this reason the load connected between
pin 3 and +VCC is called the normally on load and that connected between pin 3 and
ground is called normally off-load. On the other hand, when the output is high the current
through the load connected between pin 3 and +VCC is zero. The output terminal supplies
current to the normally off load. This current is called source current. The maximum
value of sink or source current is 200mA.

Pin4: Reset. The 555 timer can be reset (disabled) by applying a negative pulse to this
pin. When the reset function is not in use, the reset terminal should be connected to +VCC
to avoid any possibility of false triggering.

Pin5: Control Voltage. An external voltage applied to this terminal changes the threshold
as well as trigger voltage. Thus by imposing a voltage on this pin or by connecting a pot
between this pin and ground, the pulse width of the output waveform can be varied.
When not used, the control pin should be bypassed to ground with a 0.01µF Capacitor to
prevent any noise problems.

Pin6: Threshold. This is the non-inverting input of comparator 1, which monitors the
voltage across the external capacitor. When the voltage at this pin is greater than or equal
to the threshold voltage 2/3 VCC, the output of comparator 1 goes high, which inturn
switches the output of the timer low.
Pin7: Discharge. This pin is connected internally to the collector of transistor Q1. When
the output is high Q1 is OFF and acts as an open circuit to external capacitor C connected
across it. On the other hand, when the output is low, Q1 is saturated and acts as a short
circuit, shorting out the external capacitor C to ground.

Pin8: +VCC. The supply voltage of +5V to + 18V is applied to this pin with respect to
ground.

Operation:

Initially when the circuit is in the stable state i.e., when the output is low, transistor Q1 is
ON and the capacitor C is shorted out to ground. Upon the application of a negative
trigger pulse to pin 2, transistor Q1 is turned OFF, which releases the short circuit across
the external capacitor C and drives the output high. The capacitor C now starts charging
up towards VCC through R. When the voltage across the capacitor equals 2/3 V CC,
comparator 1’s output switches from low to high, which inturn drives the output to its
low state via the output of the flip-flop. At the same time the output of the flip-flop turns
transistor Q1 ON and hence the capacitor C rapidly discharges through the transistor. The
output of the monostable remains low until a trigger pulse is again applied. Then the
cycle repeats.
The pulse width of the trigger input must be smaller than the expected pulse width of the
output waveform. Also the trigger pulse must be a negative going input signal with
amplitude larger than 1/3 VCC.
The time during which the output remains high is given by

t= 1.1 RC seconds

where R is in Ohms and C is in Farads.

Once triggered, the circuit’s output will remain in the high state until the set time, t
elapses. The output will not change its state even if an input trigger is applied again
during this time interval t. The circuit can be reset during the timing cycle by applying
negative pulse to the reset terminal. The output will remain in the low state until a trigger
is again applied.

Bistability:

Something that is bistable can be resting in two states. In physics, for an ensemble of
particles, the bistability comes from the fact that its free energy has three critical points.
Two of them are minima and the last is a maximum. By mathematical arguments, the
maximum must lie between the two minima. By default, the system state will be in either
of the minima states, because that corresponds to the state of lowest energy. The
maximum can be visualised as a barrier.

A transition from one state of minimal free energy requires some form of activation
energy to penetrate the barrier (compare activation energy and Arrhenius equation for the
chemical case.) After the barrier has been reached, the system will relax into the next
state of lowest energy again. The time it takes is usually attributed the relaxation time.
(There might be uncertainty as to which state will be the new one, but it is often well
defined in the situation.)

Optical bistability is an attribute of certain optical devices where two resonant

transmissions states are possible and stable, dependent on the input.

Balls marked "1" and "3" are in the two stable positions
we will look at the simplest circuit you can build with the 555 IC - the bistable. As the
"bi" in its name suggests, the bistable has two stable states, high and low.

The waveforms in figure 1 illustrate the operation of a bistable. Taking the Trigger input
low makes the output of the circuit go into the high state. Taking the Reset input low
makes the output of the circuit go into the low state.

This type of circuit is ideal for use in an automated model railway system where the train
is required to run back and forth over the same piece of track. A push button (or reed
switch with a magnet on the underside of the train) would be placed at each end of the
track so that when one is hit by the train, it will either trigger or reset the bistable. The
output of the 555 would control a DPDT relay which would be wired as a reversing
switch to reverse the direction of current to the track, thereby reversing the direction of
the train.
The 555 Bistable Circuit

Since there is no timing involved in this circuit, no equations are needed to work out the
components. The circuit diagram is given in figure 2.
Building the Circuit

A stripboard layout for the 555 bistable circuit is given in figure 3. It provides a direct
output from the 555 (pin 3), but if you want the bistable to control another device, such as
a motor, you will probably want to leave some extra board space for any extra
components required, such as a DPDT relay. Some suggestions are given in "Using the
555 output" from part 1 of this series, The 555 Timer.

The 220μF capacitor is included to smooth the power supply, and can be omitted if you
are using a regulated supply or the circuit functions correctly without it.

Construction
1. Cut a piece of stripboard to 12 tracks x 21 columns + extra columns for any extra
components required.
2. Fit the 3 wire links.

3. Fit the 10KΩ resistors.

4. Fit the 8-pin IC socket, taking care to align the notch as shown in the layout. Do
not insert the 555 at this time.

5. Fit the 0.01μF and 220μF capacitors. Ensure that the polarity of the 220μF
capacitor is correct. The leads will be marked with '+' or '-'.
6. Fit the components associated with the device that the 555 is controlling.

7. Insert the 555 into its socket, taking care to align the notch with the notch in the
socket.

8. Cut the copper tracks where an X is shown.

9. Connect up a 3V - 15V DC power supply and test the circuit.