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Logic Synthesis For Energy-Efficient Photonic Integrated Circuits

The document discusses logic synthesis for energy-efficient photonic integrated circuits, focusing on optical computing and its components. It presents two proposed algorithms aimed at improving power efficiency in optical networks: combiner elimination and coupler assignment. Experimental results demonstrate significant improvements in power efficiency compared to previous works.

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8 views28 pages

Logic Synthesis For Energy-Efficient Photonic Integrated Circuits

The document discusses logic synthesis for energy-efficient photonic integrated circuits, focusing on optical computing and its components. It presents two proposed algorithms aimed at improving power efficiency in optical networks: combiner elimination and coupler assignment. Experimental results demonstrate significant improvements in power efficiency compared to previous works.

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1750157872
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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リレーションシップ ID rId4 のイメージ パーツがファイルにありませんでした。

Logic Synthesis for


Energy-Efficient Photonic
Integrated Circuits

Zheng Zhao, Zheng Wang, Zhoufeng Ying,


Shounak Dhar, Ray T. Chen, and David Z. Pan

Dept. of Electrical and Computer Engineering


The University of Texas at Austin
1
Outline

 Introduction and background


 Logic synthesis algorithms

 Experimental results

 Conclusion

2
What is Optical Computing?

 Use optics/photonics to perform computation


 Information is an optical signal sourced by lasers
and detected by photodetectors
 Great potentials
› Significant reduction of signal transfer latency
› Ultra-low energy consumption
› Simplified architecture for many computation tasks
Automate the Chip Design Flow

Logic Synthesis  ?
Optical Computing Components
 Microresonator-based Optical Switches
› Can be implemented with microrings/microdisks

2X2 optical switch


Optical Computing Components
 Y-branch combiner and directional coupler
› When there is only one light input
k: coupling constant

Pout = 0.5 PIn1 Pout = k PIn1


Pout = 0.5 PIn2 Pout = (1-k) PIn2

Power efficiency factor = Pout/Pin


 Size of a typical coupler ≈ 2X size of a typical
micro-resonator-based switch
Optical Computing Components
 An NX1 combiner/coupler can be implemented by
connecting an array of 2X1 combiners/couplers
 NX1 coupler of arbitrary power efficiency factors
is achievable by cascading (N-1) 2X1 couplers

3X1 directional coupler

7
Outline

 Introduction and background


 Logic synthesis algorithms

 Experimental results

 Conclusion

8
Previous Works and Problems
 Synthesis using virtual gates [Condrat+, GLSVLSI’2011]
› A large number of optical components and
› Cascaded optical splitters
 BDD-based direct implementation [Wille+, ASPDAC’2015]
› A large number of cascaded optical combiners with
single light input

Each has 3dB loss


cascaded quickly!

9
Previous Works and Problems

 Data structure and the direct implementation

Binary decision diagram Optical direct implementation:


(BDD) each multi-parent BDD node
has a combiner

10
Problem with Direct Implementation
 Due to BDD’s single-path property, any
combiners have at most one light input
 Power is cut by half (3dB)

abc = 101

Light stream to the lower/upper input port

Binary decision diagram


(BDD)
11
Problem with Direct Implementation

♦ Power efficiency is a big issue


› Optical power depletes fast due to device loss
› Optical power become too small to be detected
› Requires more amplifiers which leads to greater overhead

12
Power Efficiency Factor

 For an general optical network, power efficiency


factor 𝛾𝛾 = 𝑃𝑃𝑜𝑜𝑜𝑜𝑜𝑜 /𝑃𝑃𝑖𝑖𝑖𝑖
 In a BDD-based optical network, 𝛾𝛾 can be defined
for
› node, as an optical switch
› edge, as an input branch of a combiner/coupler
› path and the whole network

13
Proposed Algorithms
 Our goal: to improve the worst-case network
efficiency under a reasonable overhead and
computational budget
 Two techniques
› Combiner elimination to avoid cascaded combiner
loss
› Coupler assignment to redistribute the power
resource

14
Technique 1: Combiner Elimination
 Idea: avoid cascaded combiner loss
› e.g., for abc=101
1/4
0

1/2

1/3

Greater combiner loss at the


terminal but not cascaded
Quantify the Benefit
 After eliminating a combiner at an internal node
𝑛𝑛𝑛𝑛𝑛𝑛
𝛾𝛾𝑛𝑛𝑛𝑛𝑛𝑛 /𝛾𝛾𝑜𝑜𝑜𝑜𝑜𝑜 =
1 + 𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛 � 𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛/𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛

 Example: eliminating c’s combiner

nIn=2
nCopy =1
nTerm =2
nCornTerm =1
2
𝛾𝛾𝑛𝑛𝑛𝑛𝑛𝑛 /𝛾𝛾𝑜𝑜𝑜𝑜𝑜𝑜 = = 4/3
1
1+1�
2
Technique 1: Combiner Elimination
 How to select the node
› Benefit ratio: 𝛾𝛾𝑛𝑛𝑛𝑛𝑛𝑛 /𝛾𝛾𝑜𝑜𝑜𝑜𝑜𝑜 > 1
› Overhead: the duplicated node number is controlled
 Heuristic: for paths with the lowest power first
› Compute the ratio and overhead for nodes closer to
the terminal first (generally have smaller overhead)
› If both meet the set criteria, copy the node cone
› Stop until the overhead budget is reached

17
Technique 2: Coupler Assignment
 Idea: redistribute the power with directional
couplers (DCs) instead of combiners
 Assign the coupling efficiency for each DC

*1/3
1
1/3
*2/3
1/2

18
General Coupler Assignment Formulation

 Polynomial programming formulation


› On path 𝒑𝒑𝒊𝒊 , 𝒙𝒙𝒋𝒋 is an assignment of coupling efficiency
for the edge 𝒆𝒆𝒋𝒋
 Objective function Power efficiency for path 𝑝𝑝𝑖𝑖

Other source of power loss on path 𝑝𝑝𝑖𝑖


 Transform the max-min objective to path
constraints with dummy variable f
General Coupler Assignment Formulation

 Other constraints
› Node constraint: rule of power conservation

› Power efficiency for each coupler

 Solvable by semidefinite programming (SDP)


relaxation, but very time consumptive

20
Fast Solution
 Iteratively solve by quadratically constrained
programming (QCP)
› In each iteration, optimize a small set of 𝑥𝑥𝑖𝑖 ’s
 For each critical path,
› Evaluate the divergence factor for each
multi-input node v

› For each selected node, reassign the


two input edges contribute to the div
› Select two nodes with the highest div for QCP

21
Outline

 Introduction and background


 Logic synthesis algorithms

 Experimental results

 Conclusion

22
Experimental Setup
 Two techniques performed iteratively for each
benchmark and stop if no further improvement
 Implementation in C++ with CUDD package

 Linux machine with 8 3.4GHz CPUs

 QCP solver: Gurobi QCP

 Benchmarks
› Microelectronics Center of North Carolina (MCNC)
› International Workshop on Logic and Synthesis
(IWLS) benchmarks
 BDD-reordering heuristic
› CUDD_REORDER_SYMM_SIFT
23
Optical Power Efficiency
Optical Power Efficiency (dB)
Worst-case Terminal

Prev. work: [Wille+,ASPDAC’2015]


Average power efficiency ratio over prev.: 27.02X
Average/greatest CPU time: 1.88s / 14.5s
Loss Distribution
 Distribution moves from low efficiency zone to high
# of path

cps (PO_27) alu4 (PO_7)


# of path

dalu (PO_27) dalu (PO_9)


Power efficiency zone {0∼10−6, 10−6∼10−5, … , 10−1∼1}
Outline

 Introduction and background


 Logic synthesis algorithms

 Experimental results

 Conclusion

26
Conclusion
 We study the optical power depletion, a critical
issue of integrated optical circuits
 We address the problem with two techniques,
combiner elimination and coupler assignment
 which also helps to build a much more noise-
resilient and scalable integrated photonic system

27
Thanks!

Q&A?

28

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