1

VLSI TO YOU YOUTUBE CHANNEL

UVM
(UNIVERSAL VERIFICATION
METHADOLOGY )

BASIC LEVEL INTERVIEW

QUESTIONS
2
VLSI TO YOU YOUTUBE CHANNEL
1. Why do we need UVM methodology?

The Universal Verification Methodology (UVM) is a standardized methodology for verifying digital
designs that helps develop a reusable, modular, and well-structured verification test bench. UVM
provides pre-defined base classes and allows users to extend and reuse pre-defined methods.

UVM uses a set of rules and approaches for verification that allows different teams to collaborate
more effectively and understand each other’s code. This helps to improve communication across
teams.

UVM also provides standardized ways like verbosity control, phases, analysis ports for
communication, pre-built components like uvm_driver, uvm_monitor, uvm_env, etc

2. Difference between uvm_object and uvm_component

3. Difference between uvm_transaction and uvm_sequence_item

1. The uvm_transaction class is inherited from uvm_object that adds additional information on
timing, notification events, and recording interface.

2. The uvm_sequence_item class is derived from the uvm_transaction class that adds basic
functionality for sequence and sequence items like get_sequence_id, set_sequencer,
get_sequence, etc.

3. It is important to note that uvm_transaction usage is deprecated as a base class for user-
defined transactions. Hence, the uvm_sequence_item class shall be used as a base class for
user-defined transactions.

4. Difference between create and new()

The new method is a constructor for SystemVerilog classes to create an object instance.

The create() method of the wrapper class is used to create objects for the uvm_object and
uvm_component class which is commonly known as factory registration.

In UVM based testbench, it is valid to use a new() function to create class objects, but factory
registration has its benefits. The UVM factory allows an object of one type to be overridden with an
object of its derived type without changing the testbench structure. This is known as the UVM
factory override mechanism. This is applicable for uvm objects and components.

5. Difference between copy and clone

The copy method makes a copy of the mentioned object. It performs a deep copy.

The clone method is called the create() method followed by copy(). Thus, it creates and returns a
copy of an object.

6. Difference between uvm_resource_db and uvm_config_db

7. What is severity and verbosity in UVM?

The severity and verbosity are parameters used for controlling the reporting and logging of messages
during the verification process.

Severity: It represents the importance of a message generated during the simulation.

3
VLSI TO YOU YOUTUBE CHANNEL
1. UVM_INFO: Provides general information about the progress of the simulation and also we
can print variable values for ease in debugging

2. UVM_WARNING: Indicates non-critical errors or potential issues

3. UVM_ERROR: Indicates critical errors that require attention.

4. UVM_FATAL: Indicates fatal errors that lead to the termination of the simulation.

Verbosity: It controls the print messages generated by simulation and it helps to print messages in
well well-structured way without flooding the log with all messages.

Levels:

UVM_NONE: No messages are displayed.

UVM_LOW: Minimal information is displayed.

UVM_MEDIUM: Moderate level of information, suitable for regular debugging.

UVM_HIGH: High level of information, providing detailed debugging messages.

6.Difference between sequence and sequencer.

The uvm_sequence defines a sequence of transactions or stimuli that will be applied to the DUT.
Users can also develop complex sequences which consist of multiple sub-sequences.

The uvm_sequencer manages the execution of uvm_sequence that schedules sequences in an order.
Uvm_sequencer ensures synchronization and coordination

7. How to run any test case in UVM?

8. Write a simple uvm sequence template and explain each line.

9. How is scoreboard connected to different components?

The UVM scoreboard is a component that checks the functionality of the DUT. It receives
transactions from the monitor using the analysis export for checking purposes.

The analysis port is used to connect the uvm monitor to the scoreboard to send the sequence items
or transactions for comparison.
4
VLSI TO YOU YOUTUBE CHANNEL

Intermediate
level questions
5
VLSI TO YOU YOUTUBE CHANNEL
1. What are the UVM factory and its use?

The UVM factory is used to create UVM objects and components. This is commonly known as factory
registration. The factory registration for UVM objects and components are lightweight proxies of the
actual objects and components.

In UVM based testbench, it is valid to use a new() function to create class objects, but factory
registration has its benefits. The UVM factory allows an object of one type to be overridden with an
object of its derived type without changing the testbench structure. This is known as the UVM
factory override mechanism. This is applicable for uvm objects and components.

2. Why phases are introduced in UVM? What are all phases present in UVM?

All components are static in the Verilog-based testbench whereas System Verilog introduced the OOP
(Object Oriented Programming) feature in the testbench. In Verilog, as modules are static, users
don’t have to care about their creation as they would have already created at the beginning of the
simulation. In the case of UVM based System Verilog testbench, class objects can be created at any
time during the simulation based on the requirement. Hence, it is required to have proper
synchronization to avoid objects/components being called before they are created, The UVM phasing
mechanism serves the purpose of synchronization.

We have the following phases present in UVM:

1. build_phase

2. connect_phase

3. end_of_elaboration_phase

4. start_of_simulation_phase

5. run_phase

6. pre_reset

7. reset

8. post_reset

9. pre_configure

10. configure

11. post_configure

12. pre_main

13. main

14. post_main

15. pre_shutdown

16. shutdown

17. post_shutdown

18. extract
6
VLSI TO YOU YOUTUBE CHANNEL
19. check

20. report

21. final

3. What approach does build_phase use and why?

The build_phase uses a top-down approach because build_phase creates the parent component first
so that the parent component can be configured and then recursively calls their child components as
per required customization. This ensures proper instantiation and hierarchical connectivity.

4. Draw and explain the verification environment in UVM.

5. What all UVM phases take time?

All run phases (including its sub-phases) take time.

1. run_phase

2. pre_reset

3. reset

4. post_reset

5. pre_configure

6. configure

7. post_configure

8. pre_main

9. main

10. post_main

11. pre_shutdown

12. shutdown

13. post_shutdown

4. What all phases are functions and tasks in UVM?

5. Why do we use the super keyword in phases likes super.build_phase, super.main_phase etc?

The super keyword is used to refer to class members (like build_phase, main_phase, run_phase, etc)
of its immediate base class or uvm_component (if derived class is extended directly from
uvm_component).

6. Difference between `uvm_do and `uvm_rand_send.

Both are uvm sequence macros that are used to generate the sequence or seq_item.

`uvm_do (seq/item) – On calling this macro, create, randomize and send to the driver will be
executed
Example: uvm_do_example
7
VLSI TO YOU YOUTUBE CHANNEL
`uvm_rand_send(seq/item) – It directly sends a randomized seq/item without creating it. So, make
sure the seq/item is created first.
Example: uvm_rand_send_example

7. What are bottom-up and top-down approaches in UVM phases?

These approaches are associated with the execution of various phases of UVM based verification
environment.

1. Bottom-Up Approach: Lower-level components being built and configured before higher-
level components.
Example: connect_phase, start_of_simulation_phase, etc

2. Top-Down Approach: On the contrary, higher-level components are built and configured
before lower-level components.
Example: build_phase, final_phase

8. How do uvm_config_db set/get work?

9. What is an analysis port?

The uvm_analysis_port is a TLM-based class that provides a write method for communication. TLM
analysis port broadcasts transactions to one or multiple components.

Example: tlm_analysis_port_example

10. What are pre_body and post_body used in sequence?

Both are user-defined callback tasks and will be called when the sequence is started.

pre_body: It is a user-definable callback that is called before the execution of body only when the
sequence is started with a ‘start’ task.

post_body: It is a user-definable callback task that is called after the execution of the body only when
the sequence is started with the start method.

11. What is an active and passive agent?

Active Agent: An Active agent drives stimulus to the DUT. It instantiates all three components driver,
monitor, and sequencer.

Passive Agent: A passive agent does not drive stimulus to the DUT. It instantiates only a monitor
component. It is used as a sample interface for coverage and checker purposes.

12. Difference between UVM subscriber and UVM scoreboard

The UVM scoreboard is a component that checks the functionality of the DUT. It receives
transactions from the monitor using the analysis export for checking purposes whereas
the uvm_subscriber class provides a built-in analysis export that connects with the analysis port. As
the name suggests, it subscribes to the broadcaster i.e. analysis port to receive broadcasted
transactions. It is used to implement a functional coverage monitor.

13. What is uvm objection and why do we need it?

14. What are the different ways of exiting the code execution?
8
VLSI TO YOU YOUTUBE CHANNEL
1. Using UVM Objections (Recommended approach): It allows proceeding for the “End of
test”. The simulation time-consuming activity happens in the run phase. If all objections are
dropped for run phases, it means the simulation activity is completed. The test can be ended
after executing clean-up phases.

2. $finish: It tells the simulator to exit the simulation. However, it is not a graceful simulation
for a UVM-based environment.

3. `uvm_fatal: Based on certain conditions as per requirement, it can be used to terminate the
simulation.
Example: If class config class is being used during run_phase and if this config class is not
available in config_db, then uvm_fatal is used to terminate simulation right away.

15. What is a sequence item in UVM?

16. Explain how the sequence starts.

A sequence is started by calling the start method that accepts a pointer to the sequencer through
which sequence_items are sent to the driver. A pointer to the sequencer is also commonly known as
m_sequencer. The start method assigns a sequencer pointer to the m_sequencer and then calls the
body() task. On completing the body task with the interaction with the driver, the start() method
returns. As it requires interaction with the driver, the start is a blocking method.

17. How do sequence, driver, and sequencer communicate?

18. What are lock and grab methods?

19. What are the RAL model and its application?

“The RAL model is an abstract model for registers and memories in DUT.”

The register abstraction layer (RAL) provides standard base class libraries. It is used to create a
memory-mapped model for registers in DUT using an object-oriented model.

The UVM RAL is used to model DUT registers and memories as a set of classes. It generates stimulus
to the DUT and covers some aspects of functional coverage.

20. What do you mean by the front-door and back-door register access?

Front door Access: A register is said to be accessed as a front door if it involves a bus interface. It
does consume time to access the register.

Back door Access: A register is said to be accessed as a back door if it uses a simulator database to
directly access the DUT register using design signals.

21. What is TLM?

TLM establishes a connection between producer and consumer components through which
transactions are sent.

TLM provides

1. unidirectional, bidirectional, or broadcasting manner communication between components

2. Broadcasting of information promptly.

3. One component to multiple components connection.

9
VLSI TO YOU YOUTUBE CHANNEL
4. The mechanism uses task and function methods to establish a connection.

5. FIFO can hold transactions and get them based on the requirement.

6. A higher level of abstraction.

7. Connection to systemC.

22. Explain generalized code structure for UVM monitor and scoreboard.
10
VLSI TO YOU YOUTUBE CHANNEL

Difficult level
questions
11
VLSI TO YOU YOUTUBE CHANNEL
1. Difference between p_sequencer and m_sequencer

m_sequencer p_sequencer

m_sequencer is associated with a

p_sequencer does not actively drive sequences or generate
monitor and is responsible for driving
transactions, thus is also called a virtual sequencer
sequences.

Used along with monitors to

dynamically respond to the design Controls other sequencers and it is not attached to any driver.
behavior

m_sequencer is a handle available by All sequences have a m_sequencer handle but they do not have a
default in a sequence. p_sequencer handle.

No separate macro is needed for the It is defined using macro

declaration `uvm_declare_p_sequencer(sequencer_name).

2. What is the virtual sequence? How is it used? Is it necessary to have virtual sequencer for virtual
sequence?

It is not necessary to have a virtual sequencer for a virtual sequence.

3. Explain the virtual sequencer and its use.

4. What is the UVM barrier and its usage?

5. What is the UVM heartbeat and its usage?

6. What is SIngleton object and its usage?

7. Given an IP, you are the owner of the IP, what are the steps you start with and when will it be
signed off?