COMBINATIONAL CIRCUITS

A combinational circuit is a type of digital logic circuit in which the output is solely determined by the current
inputs, without any memory or feedback loops. It consists of logic gates that combine the input signals to
produce an output based on Boolean algebra.

ADVANTAGES DISADVANTAGE

Simple to design and implement. More prone to glitches.

Faster operation due to lack of memory elements. Complexity increases with the number of inputs.
Lower power consumption compared to sequential circuits.
Static functionality; limited to current input.
Predictable behavior, making testing easier. Cannot store or process sequential data.
Useful for arithmetic, data selection, and High hardware requirements for complex designs.
encoding/decoding.

MUTIPLEXER DEMUTIPLEXER IMPORTANT

It receives binary information from several It is digital circuit that takes a single input
input lines (2n) and route it to a single signal and directs it to one of many
LOGICAL EQUATIONS – Concise, Clarity
output according to select line(N) output lines based on the values of select
lines. and Optimized synthesis but limited
2n:1.
Flexibility and scalability also No
Verilog Implementations of 4:1 assign Y0 = ~A2 & ~A1 & ~A0; explicit Control flow.
USING LOGICAL : assign Y1 = ~A2 & ~A1 & A0;
assign Y2 = ~A2 & A1 & ~A0;
IF ELSE – Synthesize to nested 2:1 MUX
assign Y3 = ~A2 & A1 & A0;
with PERIORITY ENCODING.
assign Y4 = A2 & ~A1 & ~A0;
assign Y5 = A2 & ~A1 & A0;
assign Y6 = A2 & A1 & ~A0;
assign Y7 = A2 & A1 & A0;

ENCODER
An encoder is a combinational circuit
Using Conditional(Ternary) Operator- that converts a set of 2n inputs into an n-
assign Y = S1 ? (S0 ? I3 : I2) bit output, where only one input is high (1) CASE STATEMENT – Synthesize to MUX
: (S0 ? I1 : I0); at any time. OF 2n :1.
case ({I3, I2, I1, I0})
Using if-else statements [PERIORITY] 4'b0001: {Y1, Y0} = 2'b00;
if (sel == 2'b00) out = data[0]; 4'b0010: {Y1, Y0} = 2'b01;
else if (sel == 2'b01) out = data[1]; 4'b0100: {Y1, Y0} = 2'b10;
else if (sel == 2'b10) out = data[2]; 4'b1000: {Y1, Y0} = 2'b11;
else if (sel == 2'b11) out = data[3]; default: {Y1, Y0} = 2'b00;
else out = 1'b00; // Default endcase

Using case statement – DECODER

case (sel) A decoder converts an n-bit input into a
2'b00: out = data [0]; // Select input 0 one-hot output, where each input
2'b01: out = data [1]; // Select input 1 combination produces a unique output.
2'b10: out = data [2]; // Select input 2
2'b11: out = data [3]; // Select input 3 assign Y0 = ~A1 & ~A0; // A1' A0'
default: out = 1'b0; // avoid latch assign Y1 = ~A1 & A0; // A1' A0
endcase assign Y2 = A1 & ~A0; // A1 A0'
assign Y3 = A1 & A0; // A1 A0
 HALF ADDER MAJORITY VOTER MULTIPLIER
add two single-bit binary numbers. It A Majority Voter is a digital circuit . A Binary Multiplier is a digital
has two inputs (A and B) and two that outputs the value that occurs circuit used to multiply two binary
outputs: the Sum and the Carry. most frequently among its inputs. numbers.
Majority = 1 if at least two of the #P0=A0.B0 # P1=A1B0+A0.B1
three inputs are 1. #P2=A1B1+A0B1 #P3=A1B1
XY C S Majority = 0 if at least two of the
00 0 0 three inputs are 0.
01 0 1
10 0 1
11 1 0

module half_adder(
input A, // First input bit module majority_voter( input A,
input B, // Second input bit // First input bit
input B, // Second input bit module binary_multiplier (
output Sum, // Sum output input [1:0] A ,input [1:0] B,
output Carry // Carry output input C, // Third input bit
output Majority // Majority output (0 output [3:0] P );
); assign P[0] = A[0] & B[0];
or 1)
// Sum is the XOR of A and B assign P[1] = (A[1] & B[0]) ^ (A[0] &
);
assign Sum = A ^ B; // Majority logic: Majority = (A & B) | (B B[1]);
// Carry is the AND of A and B & C) | (A & C) assign P[2] = (A[1] & B[1]) ^ ((A[0] &
assign Carry = A & B; assign Majority = (A & B) | (B & C) | B[0]) & (A[1] & B[0]));
(A & C); assign P[3] = A[1] & B[1];
endmodule
endmodule endmodule

FULL ADDER FULL SUBTRACTOR PARITY GENERATOR

A Full Adder is a combinational circuit that Full Subtractor is a combinational A Parity Detector is a digital circuit
adds three bits: two input bits and a carry- circuit that subtracts three binary that checks whether a given set of
in (from a previous stage). It produces two bits: two input bits (A and B) and a bits has even or odd parity. Parity
outputs: the Sum and the Carry-out. borrow-in (Bin from a previous stage refers to the number of 1 bit in a
Sum (S) = A ⊕ B ⊕ Cin =∑(1,2,4,7) or 0). It produces two outputs: the binary number:
Carry-out (Cout) = AB+BC+AC difference (D) and the borrow-out Even parity: The number of 1 bit is
(Bout). even.
Difference (D) = A ⊕ B ⊕ Bin Odd parity: The number of 1 bit is
Borrow-out (Bout) = ~AB +BBin+ ~AB odd.

A B Bin| D Bout
00 0 | 0 0
00 1 | 1 1
01 0 | 1 1
01 1 | 0 1
10 0 | 1 0
10 1 | 0 1 module parity_detector (
module full_adder( 11 0 | 0 0 input [3:0] A, // 4-bit input A
input A, input B , input Cin 11 1 | 1 1 output parityeven // Even parity
output Sum, output Cout
output parityodd //odd parity
);
module full_subtractor( );
// Sum is the XOR of A, B, and Cin
input A, input B , input Bin ,output // Even parity is the XOR of all
assign Sum = A ^ B ^ Cin;
D,OUTPUT Bout ); input bits
// Carry-out is the OR of the AND
assign D = A ^ B ^ Bin; assign parityeven = A[0] ^ A[1] ^
combinations of A, B, and Cin
assign Bout = (~A & B) | (~A & Bin) | (B A[2] ^ A[3];
assign Cout = (A & B) | (B & Cin) | (A &
& Bin); assign parityodd = ~(A[0] ^ A[1] ^
Cin);
endmodule A[2] ^ A[3]);
endmodule
endmodule
DESIGN PROCEDURE Carry Look Ahead Adder MUlTIPY CONSTANT
>>From the specifications of the circuit, To overcome ripple carry delay, we can Let, 3A =2A+A;
determine the required number of inputs and anticipate carry bit generation in Hence, shift once and then add with
outputs and assign a symbol to each. advance. By analyzing input bits early, number
>>Derive the truth table that defines the we can determine if a carry will occur, module MutiPY (
required relationship between input [3:0]NUM, input [3:0]multiplier,
reducing delay.
inputs and outputs. output reg [7:0] result );
Pi = Ai ⊕ Bi Gi = Ai Bi
>>Obtain the simplified Boolean functions integer i;
for each output as a function of the input always @(*) begin
variables(K-MAP). result = 8'd0;
>>Draw the logic diagram and verify it. module CarryLookAheadAdder( for (i = 0; i < 4; i = i + 1) begin
input [3:0]A, B, input Cin, if (multiplier[i] == 1'b1) begin
output [3:0] S,output Cout); result = result + (NUM<< i);
end
Ripple Carry Adder wire [3:0] Ci;
correctness of the design. end
A structure of multiple full adders is assign Ci[0] = Cin; end
cascaded in a manner to gives the assign Ci[1] = (A[0] & B[0]) | ((A[0]^B[0]) endmodule
results of the addition of an n bit binary & Ci[0]);
sequence. assign Ci[2] = (A[1] & B[1]) | ((A[1]^B[1])
Tdelay=(n-1)Tcarry +max(Tcarry,Tsum) & ((A[0] & B[0]) | ((A[0]^B[0]) & Ci[0])));
assign Ci[3] = (A[2] & B[2]) | ((A[2]^B[2])
& ((A[1] & B[1]) | ((A[1]^B[1]) & ((A[0] &
B[0]) | ((A[0]^B[0]) & Ci[0])))));
assign Cout = (A[3] & B[3]) | ((A[3]^B[3])
& ((A[2] & B[2]) | ((A[2]^B[2]) & ((A[1] &
B[1]) | ((A[1]^B[1]) & ((A[0] & B[0]) |
((A[0]^B[0]) & Ci[0])))))));
assign S = A^B^Ci; ABSOLUTE OF VALUE
module ripple_carry_adder(a, b, cin,
endmodule
sum, cout);
input [3:0] a; input [3:0] b; input cin;
output [3:0] sum; output cout; module Absolute_Value (
BCD Adder input [3:0] value,
wire [2:0]c; BCD number can represent 0000-1001,so output [3:0] abs_value );
fulladd a1(a[0],b[0],cin, sum[0],c[0]); when the sum to two BCD number greater assign abs_value = (value[3] ==
fulladd a2(a[1],b[1],c[0],sum[1],c[1]); then 9 ,need to add 0110 to the resulted sum 1'b1) ? (~value + 4'b0001) : value;
fulladd a3(a[2],b[2],c[1],sum[2],c[2]); to make it valid. Use full_adder module. // Take 2's complement if negative
fulladd a4(a[3],b[3],c[2],sum[3],cout); endmodule
endmodule
**full_adder module is in full adder

MAGINTUDE COMPARATOR
A=B: E=(A0⊙B0)(A1⊙B1)
A<B: L=~A1B1+(A1⊙B1)(~A0)B0
A>B: G=A1(~B1)+(A1⊙B1)A0(~B0)

module BCD_Adder (
input [3:0] a, // 4-bit BCD input A
input [3:0] b, // 4-bit BCD input B Multiply by even number :
output [3:0] sum, // 4-bit BCD sum Shift left using << operator.
output carry // Carry out Divide by even number :
); Shift right using >> operator.
wire [4:0] temp_sum; // Temporary 5-bit
module magComp ( Check if to numbers are equal:
sum to handle carry
input [7:0] In1,input [7:0] In2, assign temp_sum = a + b; // Add the BCD
XNOR the numbers.
output Gt,output Lt,output Eq); numbers Check if to numbers are not
reg Gt, Lt, Eq; assign carry = (temp_sum > 4'd9); // Carry equal:
always @ (*) occurs if sum exceeds 9 XOR the numbers.
begin assign sum = carry ? (temp_sum + 4'd6) : Digital circuits negative
Gt <= (In1 > In2) ? 1’b1 : 1’b0; temp_sum; // Adjust for BCD if carry numbers are represented by
Lt <= (In1 < In2) ? 1’b1 : 1’b0;
using 2’s complement .
Eq <= (In1 == In2) ? 1’b1 : 1’b0; endmodule
end
endmodule
R

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