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Implementing A Data Pipeline Project On ARTY Z7 in

This guide details the steps to create a minimal data pipeline project on the ARTY Z7 board using Vivado, simulating sensor data processing. It covers initial project setup, block design creation, configuration of various components like Zynq PS, AXI DMA, and custom processing modules, as well as implementation workflow. The document also outlines the data flow in the system, emphasizing the flexibility for expanding DSP applications.

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Rodrigo Lopes
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21 views4 pages

Implementing A Data Pipeline Project On ARTY Z7 in

This guide details the steps to create a minimal data pipeline project on the ARTY Z7 board using Vivado, simulating sensor data processing. It covers initial project setup, block design creation, configuration of various components like Zynq PS, AXI DMA, and custom processing modules, as well as implementation workflow. The document also outlines the data flow in the system, emphasizing the flexibility for expanding DSP applications.

Uploaded by

Rodrigo Lopes
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Implementing a Data Pipeline Project on ARTY Z7

in Vivado
This guide will walk you through creating a minimal data pipeline project on the ARTY Z7 board
using Vivado. The pipeline will simulate reading external sensor data by having the Processing
System (PS) generate random data, routing it through programmable logic (PL), buffering it in a
FIFO, processing it, and returning the results.

Initial Project Setup


1. Create a New Vivado Project
Launch Vivado and click "Create Project"
Follow the wizard and name your project
Select the ARTY Z7 board under the "Boards" tab (search for "Arty") [1]
Choose the specific model you have (Arty Z7-20 or Arty Z7-10)
2. Create the Block Design
In the Flow Navigator, select "Create Block Design" under IP INTEGRATOR [1]
Name it "DataPipeline" and click OK

Blocks to Include and Justification


1. Zynq7 Processing System
Why: Core component of the Arty Z7, integrating a dual-core ARM Cortex-A9 processor
with FPGA logic [2]
Function: Will generate random data vectors and control the processing flow
How to add: Click "+" in the block design and search for "zynq" [1]
2. AXI Direct Memory Access (DMA)
Why: Enables high-speed data transfer between PS memory and PL without processor
intervention
Function: Transfers data from PS memory to the pipeline and back
How to add: Search for "AXI DMA" in the IP catalog
3. AXI4-Stream Data FIFO
Why: Provides buffering for streaming data, simulating sensor data acquisition [3]
Function: Stores incoming data before processing
How to add: Search for "AXI4-Stream Data FIFO" in the IP catalog
4. AXI Central Direct Memory Access (CDMA)
Why: Transfers data between memory-mapped addresses efficiently [4]
Function: Moves data between Block RAMs in our pipeline
How to add: Search for "AXI CDMA" in the IP catalog
5. Block RAM (BRAM)
Why: On-chip memory for storing data being processed [4]
Function: Temporary storage for data in the processing pipeline
How to add: Add "Block Memory Generator" from the IP catalog
6. Custom Processing Module
Why: Implements the actual computation on the data
Function: Performs the arbitrary computation (simple DSP operations)
How to add: Create a custom RTL module and add it using the "Add Module" feature [5]

Block Connections and Configuration


1. Configure the Zynq Processing System
After adding the Zynq PS, click "Run Block Automation" [1]
Accept the board preset defaults for the Arty Z7
Enable HP0 slave AXI interface for high-performance data transfer
Enable one AXI general-purpose master interface (M AXI GP0)
2. Configure and Connect AXI DMA
Add AXI DMA from the IP catalog
Enable both MM2S (memory to stream) and S2MM (stream to memory) channels
Set appropriate buffer lengths (e.g., 1024)
Connect S_AXI_LITE to the PS M_AXI_GP0 via AXI Interconnect
Connect M_AXI_MM2S and M_AXI_S2MM to PS S_AXI_HP0 via another AXI Interconnect
3. Configure and Connect AXI4-Stream Data FIFO
Add AXI4-Stream Data FIFO from the IP catalog
Configure FIFO depth according to expected data volume (e.g., 1024) [3]
Connect the input (S_AXIS) to the AXI DMA MM2S output (M_AXIS_MM2S)
Connect clock and reset signals
4. Configure and Connect the BRAM
Add Block Memory Generator
Configure as True Dual Port RAM
Set appropriate memory size (e.g., 8KB)
Connect to AXI BRAM Controller
5. Configure and Connect AXI CDMA
Add AXI CDMA from the IP catalog
Connect to AXI Interconnect for control
Connect to BRAM for data transfer [4]
6. Create and Connect Processing Module
Create a simple Verilog/VHDL module performing desired computation
Add to the design using "Add Module" [5]
Connect input to the FIFO output (M_AXIS)
Connect output to the AXI DMA S2MM input (S_AXIS_S2MM)
7. Clock and Reset Configuration
Use the PS's FCLK_CLK0 as the main clock source
Connect to all AXI interfaces and custom modules
Use the PS's FCLK_RESET0_N for reset signals

Implementation Workflow
1. Complete the Block Design
Click the "Regenerate Layout" button (circular arrow icon) to organize the design [1]
Validate the design (checkmark icon) to ensure there are no errors [1]
2. Create the HDL Wrapper
Right-click on the block design in Sources and select "Create HDL Wrapper" [1]
Choose "Let Vivado manage wrapper and auto-update"
3. Generate Bitstream
Run Synthesis, Implementation, and Bitstream Generation
Review the implementation results in the Device tab for resource utilization [1]
4. Export Hardware
Click File > Export > Export Hardware [1]
Include the bitstream in the exported hardware platform
Save the .xsa file to your project directory
5. PS Software Development
Launch Vitis using the exported hardware
Create a basic application that:
1. Allocates memory for input and output buffers
2. Fills input buffer with random data
3. Configures the AXI DMA to transfer data from memory to the pipeline
4. Waits for processing completion
5. Analyzes the results returned to the output buffer

Data Flow in the System


1. PS generates random data and stores it in DDR memory
2. AXI DMA reads this data and converts it to AXI4-Stream
3. Data flows through the AXI4-Stream FIFO, buffering it (simulating sensor input) [3]
4. Custom logic processes the data stream
5. Processed data returns via AXI DMA to PS memory
6. PS analyzes the processed data
This implementation provides a flexible pipeline that can be expanded for more complex DSP
applications while maintaining the simulation of external data acquisition.
⁂

1. https://www.hackster.io/whitney-knitter/getting-started-with-the-arty-z7-in-vivado-2020-2-e9e70f
2. https://www.tme.eu/Document/a65e4dd6390c4810dce969b38148236a/410-346-20.pdf
3. https://www.toolify.ai/gpts/understanding-fifo-in-fpga-311598
4. https://www.hackster.io/503611/arty-z7-ai-accelerator-using-axi-cdma-c34236
5. https://www.xilinx.com/support/documents/sw_manuals/xilinx2022_1/ug994-vivado-ip-subsystems.pdf

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