ANALOG AND DIGITAL CIRCUITS

Course Code: 18AUE211J

Unit 3: Digital Logic Gates and Minimization Techniques

Dr. CARUNAISELVANE.C
Assistant Professor
Automobile Engineering Department
SRM Institute of Science and Technology.
 Logic Gates
 Logic gate: device that acts as a building block for digital
circuits.
 perform basic logical functions that are fundamental to
digital circuits.
 Most electronic devices will have some form of logic gates
in them.
 In a circuit, logic gates will make decisions based on a
combination of digital signals coming from its inputs.
 Most logic gates have two inputs and one output.
 Logic gates are based on Boolean algebra.
 At any given moment, every terminal is in one of the two
binary conditions, false or true.
 False represents 0, and true represents 1.
 Logic gates are commonly used in integrated circuits (IC).
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 Logic Gates

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 Logic Gates

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 Logic Gates
 Logic Gates are manufactured using semiconductor
devices like BJT, Diodes, or FETs.
 Different Gate’s are constructed using Integrated circuits.
 Digital logic circuits are manufactured depending on the
specific circuit technology or logic families.
 The different logic families are RTL(Resistor Transistor
Logic), DTL(Diode Transistor Logic), TTL(Transistor-
Transistor Logic), ECL(Emitter Coupled Logic) &
CMOS(Complementary Metal Oxide Semiconductor
Logic).
 Out of these, RTL and DTL are rarely used.

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 Transistor-Transistor Logic (TTL)
 Transistor-Transistor Logic (TTL) is a logic family made up
of BJTs (bipolar junction transistors).
 As the name suggests, the transistor performs two
functions like logic as well as amplifying.
 The best examples of TTL are logic gates namely the
7402 NOR Gate & the 7400 NAND gate.
 The designing of TTL logic gates can be done with
resistors and BJTs.
 TTLs are available in different types done based on the
output
 Standard TTL and Fast TTL
 Schottky TTL and Advanced Schottky TTL
 High Power TTL and Low Power TTL

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 7400 series TLL

Pin configuration
 Pin1: It is an A-input Gate-1
 Pin2: It is B-input Gate-1
 Pin3: It is Y-output Gate-1
 Pin4: It is an A-input Gate-2
 Pin5: It is a B-input Gate-2
 Pin6: It is a Y-output Gate-2
 Pin7: It is a GND terminal
 Pin8: It is a Y-output Gate-3
 Pin9: It is a B-input Gate-3
 Pin10: It is an A-input Gate-3
 Pin11: It is a Y-output Gate-4
 Pin12: It is a B-input Gate-4
 Pin13: It is an A-input Gate-4
 Pin14: It is a Vcc pin (Positive
Pin
Supply)
Configuration
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 7400 series TLL
 The circuit of a basic 7400 series NAND gate

 The input stage of the

NAND gate is a multi-
emitter transistor. This
takes the inputs and
provides the required
logic.
 The next stage provides
the required phase and
drive for the final stage
 which is the standard
totem pole output.

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 7400 series TLL
 There are three types of output stage that 7400 series
logic may possess.
 Totem pole
 Open collector
 Tri-state
 Totem pole: It comprises two transistors and enables very fast
switching times to be achieved.

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 7400 series TLL
 Totem pole:
 In this arrangement a driver
transistor provides complementary
voltages for the two output
transistors, Q1 and Q2, which form
the totem pole output arrangement.
 In this arrangement either Q1 or Q2
conducts dependent upon the
complementary logic status of the
inputs.
 The diode D1 ensures that Q2 is able
to turn off rapidly when required.

 Advantages :
 Low power consumption
 Fast switching
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 7400 series TLL
 Open collector:
 This form of output has a single
transistor with its emitter connected
to 0V.
 In this way external loads can be
connected between the output, i.e.
the transistor collector and 5V.
 This has many applications including
driving indicator lamps.
 However the speed of switching is
much slower and dependent upon
external influences.

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 7400 series TLL
 Tri-state:
 This form of output has three states as the name implies.
 It is able to provide the high and low of a normal output. It is
also possible to disable the output so it has no effect on the
line being driven - in this state it is open circuit or floating.
 In order to be able to select this state, an additional "enable"
input is required on the chip.
 To achieve the tri-state situation, the internal circuitry is
arranged so that both transistors in the totem-pole output can
be tuned off at the same time.

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 CMOS Logic
 CMOS stands for “Complementary metal Oxide
Semiconductor”.
 It is also known as “complimentary-symmetry metal
Oxide Semiconductor COS-MOS”.
 It is widely used in the integration of chips (ICs),
 Computer memories like RAM, ROM, EEPROM,
 cell phones, microprocessors and microcontrollers.
 The power dissipation and consumption is very less in
CMOS and it is faster, so it is widely used than the bipolar
circuits.

Cross section of two transistors in

a CMOS gate, in an N-well CMOS
process
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 CMOS Logic
 N-channel MOSFET (NMOS):
 NMOS is built over a P
substrate.
 Source and drain are made up
of n type material.
 Here the majority carriers are
 P-channel MOSFET (NMOS):
electrons.
 NMOS is faster than the  NMOS is built over a N
PMOS, because the electrons substrate.
which is the majority carriers  Source and drain are made up
travel twice the time faster of p type material.
than the holes.  Here the majority carriers are
 It conducts when the voltage holes.
is high and does not conduct  NMOS is slower than the
when the voltage is low. NMOS
 It conducts when the voltage
April 8, 2025 is low and does not conduct
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 CMOS Logic
 Working:
 Both NMOS and PMOS together design
the logic function.
 Same input voltage is used to turn ON
one MOSFET and turn OFF other MOSFET.
 So there is no need of pull up resistor in
CMOS.
 NMOS is arranged in the pull down
network between the output and the
ground.
 PMOS is arranged in the pull up network.
 This pull up and pull down network is
arranged in such a way that when one
network is ON, the other network will be
OFF.

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 CMOS Logic
 Working as NAND:
 If both of the A and B inputs are high,
then both the NMOS transistors (bottom
half of the diagram) will conduct:
 Neither of the PMOS transistors (top
half) will conduct, and a conductive
path will be established between the
output and Vss (ground), bringing the
output low.
 If both of the A and B inputs are low, then
neither of the NMOS transistors will
conduct:
 while both of the PMOS transistors will
Circuit diagram of
conduct, establishing a conductive
NAND gate in CMOS
path between the output and Vdd logic
(voltage source), bringing the output
high.
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 CMOS Logic
 Working as NAND:
 If either of the A or B inputs is low,
 one of the NMOS transistors will not
conduct, one of the PMOS transistors will,
and a conductive path will be established
between the output and Vdd (voltage
source), bringing the output high.
 As the only configuration of the two
inputs that results in a low output is when
both are high, this circuit implements a
NAND (NOT AND) logic gate.

Circuit diagram of
NAND gate in CMOS
logic

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 CMOS Logic
 Advantages of CMOS:  Disadvantages of CMOS:
 Power consumption is less  Manufacturing cost is high
 Large fan-out capability  Propagation delay is higher
 High noise immunity and than TTL and ECL
noise margin
 Power dissipation is low
 Faster than NMOS
 Applications of CMOS:
 Analog to digital converter
 Image sensors
 Amplifiers
 Static RAM
 Registers
 Microchip
 Microprocessors and
microcontrollers
April 8, 2025  Transceivers
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 Boolean Algebra
 Boolean Algebra is an algebra, which deals with binary
numbers & binary variables.
 It is also called as Binary Algebra or logical Algebra.
 Boolean Postulates and
 Boolean Basic Laws

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 Boolean Postulates
 Consider the binary numbers 0 and 1,
 Boolean variable x and its complement x′.
 Either the Boolean variable or complement of it is known as
literal.
 The four possible logical OR operations
 x + 0=x
 x + 1=1
 x + x=x
 x + x’ = 1
 Similarly, the four possible logical AND operations
 x.1 = x
 x.0 = 0
 x.x = x
 x.x’ = 0
 These are the simple Boolean postulates. We can verify these
postulates easily, by substituting the Boolean variable with ‘0’
or8,‘1’.
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 Boolean laws
 Following are the three basic laws of Boolean Algebra.
 Commutative law
 Associative law
 Distributive law
 Commutative Law:
 If any logical operation of two Boolean variables give the same
result irrespective of the order of those two variables, then that
logical operation is said to be Commutative. The logical OR &
logical AND operations of two Boolean variables x & y are
shown below
x+y=y+x
x.y = y.x
 The symbol ‘+’ indicates logical OR operation. Similarly, the
symbol ‘.’ indicates logical AND operation and it is optional to
represent. Commutative law obeys for logical OR & logical AND
operations.
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 Boolean laws
 Associative law:
 If a logical operation of any two Boolean variables is performed
first and then the same operation is performed with the
remaining variable gives the same result, then that logical
operation is said to be Associative. The logical OR & logical
AND operations of three Boolean variables x, y & z are shown
below.
x + y+z = x+y + z
x.y.z = x.y.z
 Associative law obeys for logical OR & logical AND operations.

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 Boolean laws
 Distributive law:
 If any logical operation can be distributed to all the terms
present in the Boolean function, then that logical operation is
said to be Distributive. The distribution of logical OR & logical
AND operations of three Boolean variables x, y & z are shown
below.
x.y+z = x.y + x.z
x + y.z = x+y.x+z
 Distributive law obeys for logical OR and logical AND
operations.

 These are the Basic laws of Boolean algebra. We can verify

these laws easily, by substituting the Boolean variables with ‘0’
or ‘1’.

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 Theorems of Boolean Algebra
 The following two theorems are used in Boolean algebra.
 Duality theorem
 DeMorgan’s theorem
 Duality Theorem:
 This theorem states that the dual of the Boolean function is
obtained by interchanging the logical AND operator with logical
OR operator and zeros with ones. For every Boolean function,
there will be a corresponding Dual function.

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 Theorems of Boolean Algebra
 DeMorgan’s Theorem:
 This theorem is useful in finding the complement of Boolean
function.
 It states that the complement of logical OR of at least two
Boolean variables is equal to the logical AND of each
complemented variable.
 DeMorgan’s theorem with 2 Boolean variables x and y can be
represented as
x+y’ = x’.y’
 The dual of the above Boolean function is
x.y’ = x’ + y’
 Therefore, the complement of logical AND of two Boolean
variables is equal to the logical OR of each complemented
variable.
 Similarly, we can apply DeMorgan’s theorem for more than 2
Boolean variables also.
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 Karnaugh Map
 In many digital circuits and practical problems we need to find
expression with minimum variables.
 We can minimize Boolean expressions of 3, 4 variables very
easily using K-map without using any Boolean algebra
theorems.
 K-map can take two forms Sum of Product (SOP) and Product of
Sum (POS) according to the need of problem.
 K-map is table like representation but it gives more information
than TRUTH TABLE.
 We fill grid of K-map with 0’s and 1’s then solve it by making
groups.
 It is a graphical method, which consists of 2n cells for ‘n’
variables.
 The adjacent cells are differed only in single bit position.

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 Karnaugh Map
 Steps to solve expression using K-map:
1. Select K-map according to the number of variables.
2. Identify minterms or maxterms as given in problem.
3. For SOP put 1’s in blocks of K-map respective to the minterms
(0’s elsewhere).
4. For POS put 0’s in blocks of K-map respective to the
maxterms(1’s elsewhere).
5. Make rectangular groups containing total terms in power of
two like 2,4,8 ..(except 1) and try to cover as many elements
as you can in one group.
6. From the groups made in step 5 find the product terms and
sum them up for SOP form.

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 Karnaugh Map
 2 Variable K-Map:
 The number of cells in 2 variable K-map is four, since the
number of variables is two. The following figure shows 2
variable K-Map.

 There is only one possibility of grouping 4 adjacent min terms.

 The possible combinations of grouping 2 adjacent min terms

are {(m0, m1), (m2, m3), (m0, m2) and (m1, m3)}.

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 Karnaugh Map
 3 Variable K-Map:
 The number of cells in 3 variable K-map is eight, since the
number of variables is three. The following figure shows 3
variable K-Map.

 There is only one possibility of grouping 8 adjacent min terms.

 The possible combinations of grouping 4 adjacent min terms are
{(m0, m1, m3, m2), (m4, m5, m7, m6), (m0, m1, m4, m5), (m1,
m3, m5, m7), (m3, m2, m7, m6) and (m2, m0, m6, m4)}.
 The possible combinations of grouping 2 adjacent min terms are
{(m0, m1), (m1, m3), (m3, m2), (m2, m0), (m4, m5), (m5, m7),
(m7, m6), (m6, m4), (m0, m4), (m1, m5), (m3, m7) and (m2,
m6)}.
April
If x=0,
8, 2025 then 3 variable K-map becomes 2 variable K-map.
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 Dr. CARUNAISELVANE.C
Assistant Professor
Automobile Engineering Department
SRM Institute of Science and Technology.
[email protected]
+91 8265804594

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Thank you all for your attention

Carunaiselvane Carounagarane (S’16) received the B.Tech. degree in electrical and electronics engineering
and the M.Tech. degree in electrical drive and control from Pondicherry Engineering College, Pondicherry
University, Puducherry, India, in 2008 and 2012, respectively. He has received the Ph.D. degree from
Indian Institute of Technology Roorkee, India in 2020 under the title “Analysis of Large Hydrogenerators
Operating at Continuous Overloads”. He is currently working as Assistant Professor with Automobile
Engineering Department at SRM Institute of Science and Technology, Chennai, India. From 2008 to 2010, he
was an officer grade Electrical Engineer with Larsen and Toubro Pvt. Ltd., India. From 2012 to 2014, he
has been an Assistant Professor with the Electrical and Electronics Engineering Department, Sri Manakula
Vinayagar Engineering College, Pondicherry University. His research interests include electrical machines,
power electronics, machine design, electric vehicle drives and controls, and renewable and sustainable
energy. Dr. Carunaiselvane has presented many research papers in various national and international
conferences and journals.