CMOS

Digital Integrated
Circuits
Analysis and Design

Chapter 3
MOS Transistor

1
 The Metal Oxide Semiconductor (MOS) structure

• The structure consists of • The basic properties of the

three layer semiconductor
– The metal gate The mass action law:n  p = ni 2

electrode Assume the substrate doping concentration N A

– The insulating oxide
(SiO2) layer ni2
then equilibriumelectronandholeconcpn 0  , p p0  N A
– The p-type bulk NA
semiconductor n=mobile carrier concentration of electron
P=mobile carrier concentration of hole
2
Energy band diagram of a p-type silicon substrate

3
 EF -Ei
The Fermi potential φF =
q
kT ni
For a p-type semiconductor, φFp = ln
q NA
kT N D
For a n-type semiconductor, φFn = ln
q ni
The energy required for an electron to move from the
Fermi level int o free space is called the work function
qφs = qχ + (Ec -EF )
Electron affinity of silicon is the potential
Difference between the conduction band
Level and the vacuum level and is given by
qx.
4
5
Energy diagram of the combined MOS system

• The equilibrium Fermi levels of the semiconductor (Si) substrate

and the metal gate are at the same potential
• The bulk Fermi level is not significantly affected by the bending
• The surface Fermi level moves closer to the intrinsic Fermi level
6
Example 1

7
The MOS System under External Bias - accumulation

• A negative voltage VG is applied to the gate electrode.

– The holes in the p-type substrate are attracted to the semiconductor-
oxide surface
– The majority carrier concentration > the equilibrium hole concentration
• The electron concentration (minority carrier) decreases as the negatively
charged electron are pushed deeper into the substrate
– The oxide electric field is directed towards the gate electrode
– Causing the energy bands bend up-ward near the surface 8
The MOS System under External Bias – depletion
• A small positive gate bias VG is applied to the gate
electrode
– The oxide electric field will be directed towards the substrate
– Causing the energy bands to bend downward near the surface
– The majority carrier (hole) will be repelled back into the substrate
• Leaving negatively charged fixed acceptor ions behind (depletion
region)

9
 Assume that the mobile hole charge in a thin horizontal layer parallel to
the surface is
The change in surface
dQ = − q  N A  dx
potential
dQ q NA  x
Required to displace this
ds = − x  = dx
charge sheet dQ by a distance
xd away from the surface can  Si  Si
be found by using Poisson
s xd q NA  x
 ds = 
equation
Integrating along the vertical dimension
dx
gives
F 0  Si
q  N A  xd2
s −  F =
2 Si
Thus, the depth of the depletion region 2 Si  s − F
is xd =
q NA
And the depletion region charge
density is given by
Q = − q  N A  xd = − 2q  N A   Si  s − F
10
The MOS System under External Bias – inversion
• A further increase in the positive gate bias
– Increasing surface potential the downward bending of the energy bands will increase
– The mid-gap energy level Ei becomes smaller than the Fermi level EFp on the surface
• The substrate semiconductor in this region become n-type
• The electron density is larger than the majority hole density
• Inversion layer, surface inversion
• Can be utilized for conducting current between two terminal of the MOS transistor
– The surface is said to be inverted
• The density of mobile electrons on the surface becomes equal to the density of holes in the bulk
substrate
• Requiring the surface potential has the same magnitude, but the reverse polarity, as the bulk Fermi
potential F
• Further increase gate voltage  electron concentration  but not to an increase of the depletion
depth

2   Si  2F
xdm =
q NA

11
The physical structure of a n-channel
enhancement-type MOSFET

• MOS structure
– polysilicon gate, thin oxide layer, semiconductor
• Source, drain n+-region
– The current conducting terminals of the device
• Conducting channel, channel length L, channel width W
– The device structure is completely symmetrical with respect to the drain and source
• The simple operation of this device
– Controlling the current conduction between the source and the drain, using the electric field
generated by the gate voltage as a control variable

12
Circuit symbols for enhancement-type MOSFET

• Enhancement-mode MOSFET
– No conducting region at zero gate bias
• Depletion-mode MOSFET
– A conducting channel already exists at zero gate bias
• The abbreviations used for device terminals are
– G for the gate, D for the drain, S for the source, and B for the substrate
• The small arrow always marks the source terminal

13
Formation of a depletion region
• For small gate voltage level
– The majority carriers (holes) are repelled back into
the substrate
– The surface of the p-type substrate is depleted
– Current conduction between S and D is not possible

14
Formation of an inversion layer

• As the gate-to-source voltage is further increased

– The surface potential reaches -Fp  surface inversion will be established  conducting
channel between S and D
– Allowing current flow, as log as there is a potential difference between S and D
– VGS<VT0 (threshold voltage)
• Not sufficient to establish an inversion layer
• No current between S and D
– VGS>VT0 (threshold voltage)
• Electrons are attracted to the surface
– Contributing to channel current conduction
– Further increase gate voltage
• Not affect the surface potential and the depletion region depth

15
The threshold voltage
• Four physical components of VT0
– The work function difference between gate and the channel
• GC= F(substrate)- M for metal gate
• GC= F(substrate)- F(gate) for polysilicon gate

– The gate voltage component to change the surface potential(to

achieve surface inversion) .To change the surface potential by -2F

– The gate voltage component to offset the depletion region charge

• -QB/Cox
•
The depletion region charge
Density is given as QB = − 2q  N A   Si  − 2F + VSB
 ox
Cox =
tox
– The voltage component to offset the fixed charge in the gate oxide
and in the silicon-oxide interface(due to impurities and/or lattice
imperfections at the interface)
• -Qox/Cox
•
16
 QB 0 Qox
VT 0 =  GC − 2F − − (no body effect)
Cox Cox
VT = VT 0 +   ( )
− 2F + VSB − 2F (with body effect)
2q  N A   Si
where  =
Cox
 = substrate − bias (body − effect )coefficient

17
• Compared with the p-MOSFET

– The substrate Fermi potential F is negative in NMOS, positive in pMOS

– The depletion region charge densities QB0 and QB are negative in nMOS,
positive in pMOS
– The substrate bias coefficient  is positive in nMOS, negative in pMOS
– The substrate bias voltage VSB is positive in nMOS, negative in pMOS

• Threshold voltage adjustment

• For n-channel MOS

– Implanting p-type impurity  VT increased

– Implanting n-type impurity  VT decreased
– The amount of change in the threshold voltage as a result of extra
implant
• qNI/Cox where Ni is the density of implanted impurities

18
Example 2

19
20
Circuit symbols for n-channel depletion-type MOSFETs
• Using selective ion implantation into the channel
– The threshold voltage for nMOSFET can be made
negative
– Having a conducting channel at VGS=0

21
22
Example 3

23
MOSFET operation: linear region
• The MOSFET consists
– A MOS capacitor, two pn junction adjacent to the channel
– The channel is controlled to the MOS gate
• The carrier (electron in nMOSFET)
– Entering through source, controlling by gate, leaving through drain
• To ensure that both p-n junctions are reverse-biased initially
– The substrate potential is kept lower than the other three terminal potentials
• When 0<VGS<VT0
– G-S region depleted, G-D region depleted
– No current flow
• When VGS>VT0
– Conduction channel formed
– Capable of carrying the drain current
– As VDS=0
• ID=0
– As VDS>0 and small
• ID proportional to VDS
• Flowing from S to D through the conducting channel
• The channel act as a voltage controlled resistor
• The electron velocity much lower than the drift velocity limit
• As VDSthe inversion layer charge and the channel depth at the drain end start to
decrease

24
MOSFET operation: saturation region
• For VDS=VDSAT
– The inversion charge at the drain is
reduced to zero
– Pinch off point
• For VDS>VDSAT
– A depleted surface region forms adjacent
to the drain
– As further increases VDS  this depletion
region grows toward the source
– The channel-end voltage remains
essentially constant and equal to VDSAT
– The pinch-off (depleted) section
• Absorbs most of the excess voltage drop,
VDS-VDSAT
• A high-field region forms between the
channel-end and the drain boundary
– Accelerating electrons, usually reaching
the drift velocity limit

25
MOSFET current-voltage characteristics-gradual
channel approximation (GCA)(1)

26
• Considering linear mode operation

–VS=VB=0, the VGS and VDS are the

external parameters controlling the
drain current ID

–VGS > VT0 (assume that VT0 is

constant throughout the channel) to
create a conducting inversion layer

27
– Defining
• X-direction: perpendicular to the
surface, pointing down into the
substrate

• Y-direction: parallel to the surface

–The y=0 is at the source end of
the channel
–Channel voltage with respect to
the source, Vc(y)
28
–Assume the electric field Ey is
dominant compared with Ex

• This assumption reduced the

current flow in the channel to the
y-direction only

–Let QI(y) be the total mobile

electron charge in the surface
inversion layer
• QI(y)=-Cox[VGS-Vc(y)-VT0]
29
30
 MOSFET current-voltage characteristics-gradual
channel approximation (GCA)(2)
Assuming that all mobile electrons in the inversion
layer has a constant surface mobility µn ,the
incremental resistance
dy
dR = −
W  μ  Q (y)
n I

(Minus sign is due to the negative Polarity of the

inversion layer charge Q)

The electron surface mobility depends on the

doping concentration of the channel region and its
magnitude is typically about one half of that of the
bulk electron mobility 31
 The voltage drop along dy is
I
dV = I  dR = -  dy D

W  μ  Q (y)
C D

n I


0
L
I  dy = − W  
D n

0
VDS
Q ( y )  dV
I C

I  L = W   C
D n ox

VDS
0 (V − V − V )  dV
GS C T0 C

 C W
I = D
n ox
  2  (V − V )V − V
GS T0 DS
2

DS

2 L
k W
I =   2  (V − V )V − V  where k = μ C
'

2 '

D GS T0 DS DS n ox
2 L
k W
I =  2  (V − V )V − V  where k = k 
D GS T0 DS DS
2 '

2 L
32
Example 4

33
34
MOSFET current-voltage characteristics-gradual
channel approximation (GCA)-saturation region

35
36
 For VDSVDSAT=VGS-VT0
  2  (V
GS − VT 0  VGS − VT 0 − VGS − VT 0 
 n  Cox W
I D ( sat ) = ) ( ) ( )2

2 L
 n  Cox W
=   (VGS − VT 0 )
2

2 L

The drain current becomes a function only

of VGS, beyond the saturation boundary

37
 Channel length modulation
The inversion layer charge at the source end of the channel is
QI (y = 0 ) = -Cox  (VGS -VT 0 )
and the inversion layer charge at the drain end of the channel is
QI (y = L) = -Cox  (VGS -VT 0 − VDS )
Note that at the edge of saturation, VDS = VDSAT = VGS -VT 0
The inversion layer charge at the drain end become very small
QI (y = L)  0

38
The effective channel length
L' = L − ΔL
where ΔL is the length of the channel segment with QI = 0
μnCox W
=  '  (VGS − VT 0 )
2
I D(sat)
2 L
 
 1 μC W
I D(sat) =  n ox   (VGS − VT 0 )2
 1 − ΔL  2 L
 
 L 
ΔL  VDS − VDSAT

39
 ΔL
We use 1 −  1 − λ  VDS , λ channel length
L
modulation coefficient
Assuming that λ  VDS  1
μn  Cox W
=   (VGS − VT 0 )  (1 + λVDS )
2
I D(sat)
2 L

40
41
42
Substrate bias effect
• The discussion in the previous has been done
under the assumption
– The substrate potential is equal to the source
potential, i.e. VSB=0
• On the other hand
– the source potential of an nMOS transistor can be
larger than the substrate potential, i.e. VSB>0

43
VT (VSB ) = VT 0 +   ( 2F + VSB − 2F )
 n  Cox W
I D (lin ) =
2

L

 2  (VGS − VT (VSB ) )VDS − V
2
DS 
 n  Cox
  (VGS − VT (VSB ) )  (1 +   VDS )
W
=
2
I D ( sat )
2 L

44
Current-voltage equation of n-, p-channel MOSFET
For n - channel MOSFET
I D = 0, for VGS  VT
 n  Cox W
I D ( lin ) =   2  (VGS − VT )VDS − VDS2  for VGS  VT
2 L
and VDS  VGS -VT
 n  Cox W
I D ( sat ) =   (VGS − VT )  (1 +   VDS ) for VGS  VT
2

2 L
and VDS  VGS -VT
For p - channel MOSFET
I D = 0, for VGS  VT
 p  Cox W
I D ( lin ) =   2  (VGS − VT )VDS − VDS2  for VGS  VT
2 L
and VDS  VGS -VT
 p  Cox W
I D ( sat ) =   (VGS − VT )  (1 +   VDS ) for VGS  VT
2

2 L
and VDS  VGS -VT 45
For p - channel MOSFET
I D = 0, for VGS  VT
 p  Cox W
I D ( lin ) =   2  (VGS − VT )VDS − VDS2  for VGS  VT
2 L
and VDS  VGS -VT
 p  Cox W
I D ( sat ) =   (VGS − VT )  (1 +   VDS ) for VGS  VT
2

2 L
and VDS  VGS -VT

46
Measurement of parameters- kn, VT0, and 
• The VSB is set at a constant value
– The drain current is measured for different values of VGS
– VDG=0
• VDS>VGS-VT is always satisfied  saturation mode

• Neglecting the channel length modulation effect

–

I D ( sat ) =
kn
( )
 VGS − VT 0 , I D =
2 kn
 (VGS − VT 0 )
2 2
– Obtaining the parameters kn, VT0, and 
–

VT (VSB ) − VT 0
=
2F + VSB − 2F
47
48
Measurement of parameters- 
• The voltage VGS is set to VT0+1

• The voltage VDS is chosen sufficiently large (VDS>VGS-VT0)

that the transistor operates in the saturation mode, VDS1,
VDS2
– ID(sat)=(kn/2)(VGS-VT0)2(1+VDS)
• Since VGS=VT0+1
• ID2/ID1=(1+VDS2)/ (1+VDS1)
• Which can be used to calculate the channel length
modulation coefficient 
• This is in fact equivalent to calculating the slope of
the drain current versus drain voltage curve in the
saturation region
– The slope is kn/2 49
50
Example 5

51
MOSFET scaling and small-geometry effects
• High density chip
– The sizes of the transistors are as small as possible
– The operational characteristics of MOS transistor will change with the
reduction of its dimensions

• There are two basic types of size-reduction strategies

– Full scaling (constant-field scaling)
– Constant-voltage scaling

• A new generation of manufacturing technology replaces the

previous one about
– every two or three years
– The down-scaling factor S about 1.2 to1.5

• The scaling of all dimensions by a factor of S>1 leads to the

reduction of the area occupied by the transistor by a factor of S2

52
53
54
Full scaling (constant-field scaling)
To achieve this goal, all potentials must be
scaled down proportionally, by the same
scaling factor
Assuming the surface mobility μn is not
significantly affected by the scaled doping
density
The gate oxide capacitance per unit area
 ox  ox
Cox =
'
'
=S = S  Cox
tox tox
The aspect ratio W/L unchanged  the kn will
also scaled by a factor of S
55
56
The linear mode drain current

I D' (lin) = n  2  (VGS' − VT' )  VDS' − VDS' 2 

'
k
2
S  kn 1 I D(lin)
=  2  2  (VGS − VT )  VDS − VDS  =
2

2 S S
The saturation mode drain current
'
S  kn 1 I D(sat)
I D(sat) =  (VGS − VT ) =  2  (VGS − VT ) =
' kn ' ' 2 2

2 2 S S

57
The power dissipation
1 P
P = I D  VDS = 2  I D  VDS = 2
' ' '

S S
The significant reduction of the power dissipation
is one of the most attractive features of full scaling
The power density per unit area remaining virtually
unchanged
Cg is scaled down by a factor of S  the charge - up,
and charge - down time improved
A reduction of various parasitic capacitances and
resistances
58
59
 Constant-voltage scaling

All dimensions of the MOSFETare reduced by a factor of S .

The power supply voltage and the terminal voltages remained unchanged.
The doping densities must be increased by a factor of S 2 in order to
preserve the charge - field relations
The gate oxide capacitance per unit area Cox is increased by a factor of S
 The transconductance parameter is also increased by S

60
The linear mode drain current

I D(lin) =  2  (VGS' − VT' )  VDS' − VDS' 2 

'
' kn
2
S  kn
=  2  (VGS − VT )  VDS − VDS2  = S  I D(lin)
2
The saturation mode drain current
'
S  kn
I D(sat) = (VGS − VT ) =
kn ' ' 2
 (VGS − VT ) = S  I D(sat)
' 2

2 2
The drain current density increased by a factor of S 3

61
The power dissipation
P' = I D'  VDS' = (S  I D )  VDS = S  P
The power density incresaed by a factor of S 3
To summarized, constant - voltage scaling may
be preferred over full scaling in many practical cases
because of the external voltage - level constraints.
Disadv.  increasing current density, power density
 electromigration, hot carrier degradation,
oxide breakdown, and electrical over - stress

62
63
Short-channel effects
• A MOS transistor is called a short-channel
device

– If its channel length is on the same order

of magnitude as the depletion region
thickness of the S and D junction

– The effective channel length Leff  S, D

junction depth xj

64
 Two physical phenomena arise from short-channel
effects
The limitations imposed on electron drift characteristics in
the channel
The lateral electric field Ey increased, vd reached saturation
velocity

Leff
I D ( sat ) = W  vd ( sat )   q  n( x)  dx = W  vd ( sat )  QI = W  vd ( sat )  Cox  VDSAT
0

No longer a quadratic function of VGS, virtually

independent of the channel length

65
 The carrier velocity in the channel is
also a function of Ex
Influence the scattering of carriers in
the surface
 no  no  no
 n (eff ) = = =
 (VGS − Vc ( y ) ) 1 +   (VGS − VT )
1 +   Ex  ox
1+
tox Si

The modification of the threshold voltage due to the shortening channel length

66
Short-channel effects-modification of VT
• The n+ drain and source diffusion regions in p-type substrate induce a
significant amount of depletion charge
– The long channel VT, overetimates the depletion charge support by the gate
voltage
– The bulk depletion region  asymmetric trapezoidal shape
• A significant portion of the total depletion region charge is due the S and D junction
depletion
VT 0(short channel) = VT0 - ΔVT0
 ΔL + ΔLD 
QB 0 = −1 − S   2  q  ε Si  N A  2φF
 2L 
2  ε Si 2  ε Si kT  N D  N A 
xdS =  φ0 , xdD =  (φ0 + VDS ), φ0 =  ln 
q NA q NA q  ni
2

(x j + xdD ) = xdm
2 2
+ (x j + ΔLD )
2

ΔL2D + 2  x j  ΔLD + xdm

2
− xdD
2
− 2  x j  xdD = 0
 
ΔLD = − x j + x 2j − xdm (
2
− xdD
2
) 
2x
+ 2 x j xdD  x j   1 + dD − 1
xj 
 
 2 xdS 

ΔLS  x j  1 + − 1
 x 
 j 
1 x j  2x   2x 
ΔVT 0 =  2  q  ε Si  N A  2φF    1 + dD − 1 +  1 + dS − 1
Cox 2 L  xj  
  xj 


67
68
69
VT 0(short channel) = VT0 - ΔVT0 , Depletion
region
ch arg e(trapizoidalregion)
 ΔLS + ΔLD 
QB 0 = −1 −   2  q  εSi  N A  2φF ,
 2L 
junctionDepletion Re gionDepth
2  εSi
xdS =  φ0 ,
q  NA
2  εSi
xdD =  (φ0 + VDS ),
q  NA
kT  N D  N A 
φ0 =  ln 
 ni 
2
q
70
(x j
+ xdD
2
) = x 2
dm
+ (x j + ΔLD )
2

ΔL2D + 2  x j  ΔLD + xdm2 − xdD2 − 2  x j  xdD = 0, SolvingForΔLD

 
ΔLD = − x j + x j − ( xdm − xdD ) + 2 x j xdD  x j   1 +
2 x
2 2 2 dD
− 1
 x 
 j 
 2 x 
ΔLS  x j   1 + dS
− 1
 x 
 j 
1 x j  2 x   2 x 
ΔVT 0 =  2  q  εSi  N A  2φF    1 + dD
− 1 +  1 + dS
− 1
Cox 2 L  xj  
  x j



71
Example 6 (1)

72
Example 6 (2)

73
Example 6 (3)

74
Narrow-channel effect
• Channel width W on the same
order of magnitude as the
maximum depletion region
thickness xdm
• The actual threshold voltage of
such device is larger than that
predicted by the conventional
threshold voltage
• Fringe depletion region under
field oxide
– V (narrow channel) = V + V
T0 T0 T0

1   xdm
VT0 =  2q Si N A 2F 
Cox W

= for depletion region modeled by quarter - circular arcs
2

75
Other limitations imposed by small-device geometries
• The current flow in the channel are controlled by two dimensional electric field vector
• Subthreshold conduction
– Drain-induced barrier lowering (DIBL)
– A nonzero drain current ID for VGS<VT0
– q
qDnWxc n0 kTr kT ( AVGS + BVDS )
q
I D ( subthreshold )  e e
LB
• Punch-through
– The gate voltage loses its control upon the drain current, and the current rises sharply
• Gate oxide thickness tox scaled to tox/S, is restricted by processing difficulties
– Pinholes, oxide breakdown
• Hot-carrier effect

76
MOSFET capacitances
• L=LM-2LD
– L: the actual channel length
– LM: the mask length of the
gate
– LD: the gate-drain, the gate-
source overlap
• On the order of 0.1m

77
Oxide related capacitance(1)
• The gate electrode overlap
capacitance
– CGD(overlap)=CoxWLD
– CGS(overlap)=CoxWLD
• With Cox=ox/tox
– Both capacitance do not depend
on the bias condition, they are
voltage-independent
• The capacitances result from the
interaction between the gate
voltage and the channel charge
– Cut-off mode
• Cgs=Cgd=0
• Cgb=CoxWL
– Linear mode
• Cgb=0
• CgsCgd (1/2) CoxWL
– Saturation mode
• Cgb= Cgd =0
• Cgs (2/3) CoxWL 78
Oxide related capacitance(2)
• The sum of all three voltage-dependent (distributed) gate oxide
capacitances (Cgb+Cgs+Cgd)
– A minimum value of 0.66CoxWL, in saturation mode
– A maximum value of CoxWL, in cut off and linear modes
– For simple hand calculation
• The three capacitances can be considered to be in parallel
• A constant worst-case value of CoxW(L+2LD) can be used for the sum of
MOSFET gate oxide capacitances

79
 Junction capacitance(1)

2  ε Si N A + N D
The depletion region thickness xd =  (φ0 − V )
q N A  ND
kT  N A  N D 
The built - in potential φ0 =  ln 2

q  ni 
 N N  N N
The depletion region charge Q j = A  q   A D   xd = A 2  ε Si  q  A D (φ0 − V )
 N A + ND  N A + ND
dQ j ε Si  q  N A  N D  1
The junction capacitance C j = = A    
dV 2  N A + N D  φ0 − V
AC j 0
C j(V) = m
, the parameter m is grading coefficient
 V 
1 − 
 φ0 
ε Si  q  N A  N D  1
The zero bias junction capacitance per unit area C j 0 =  
2  N A + N D  φ0
The equivalent large - signal capacitance can be defined as
ΔQ Q j(V2 ) −Q j (V1 ) 1 V2
Ceq =
ΔV
=
V2 − V1
= 
V2 − V1 1
V
C j(V)dV

A  C j 0  0  V 1− m  V 1− m 
=−  1 − 2  − 1 − 1  
(V2 − V )  (1 − m )  0   0  
For the special case of abrupt pn - junctions
2  A  C j 0  φ0  V V 
Ceq = −   1− 2 − 1− 1 
(V2 − V )  0 0 
Ceq = A  C j 0  K eq

K eq = −
2 0
V2 − V1
(
 0 − V2 − 0 − V1 ) 80
81
 2  ε Si N A + N D
The depletion region thickness x d =  (φ0 − V )
q NA  ND
kT N N 
The built - in potential φ0 =  ln A 2 D 
q  ni 
 N  ND  N  ND
The depletion region charge Q j = A  q   A   x d = A 2  ε Si  q  A (φ0 − V )
 NA + ND  NA + ND
dQ j ε Si  q  N A  N D  1
The junction capacitance C j = = A   
dV 2  N A + N D  φ0 − V
AC j 0
C j (V) = m
, the parameter m is grading coefficient
 V 
1 − 
 φ0 
ε Si  q  N A  N D  1
The zero bias junction capacitance per unit area C j 0 =   
2  N A + N D  φ0
The equivalent large - signal capacitance can be defined as
ΔQ Q j (V2 ) −Q j (V1 ) 1 V2
C eq =
ΔV
=
V2 − V1
= 
V2 − V1 V1
C j (V)dV

A  C j 0  0  V 1− m  V 1− m 
=−  1 − 2  − 1 − 1  
(V2 − V )  (1 − m )  0    0  
For the special case of abrupt pn - junctions
2  A  C j 0  φ0  V V 
C eq = −   1− 2 − 1− 1 
(V2 − V )  0  0 
C eq = A  C j 0  K eq
2 0
K eq = −
V2 − V1
(
  0 − V2 −  0 − V1 ) 82
 2  ε Si N A + N D
The depletion region thickness x d =  (φ0 − V )
q NA  ND
kT  N A  N D 
The built - in potential φ0 =  ln 2

q  ni 
 N N  N N
The depletion region charge Q j = A  q   A D   x d = A 2  ε Si  q  A D (φ0 − V )
 NA + ND  NA + ND
dQ j ε Si  q  N A  N D  1
The junction capacitance C j = = A    
dV 2  NA + ND  φ0 − V
AC j 0
C j (V) = m
, the parameter m is grading coefficient
 V 
1 − 
 φ0 
ε Si  q  N A  N D  1
The zero bias junction capacitance per unit area C j 0 =    
2  NA + ND  φ0

83
The equivalent large - signal capacitance can be defined as
ΔQ Q j (V2 ) −Q j (V1 ) 1 V2
C eq =
ΔV
=
V2 − V1
= 
V2 − V1 1V
C j (V)dV

A  C j 0  0   V2 
1− m
 V1  
1− m

=−  1 −  − 1 −  
(V2 − V )  (1 − m )  0    0  
For the special case of abrupt pn - junctions
2  A  C j 0  φ0  V2 V1 
C eq = −   1− − 1− 
(V2 − V )  0  0 
C eq = A  C j 0  K eq
2 0
K eq = −
V2 − V1
(
  0 − V2 −  0 − V1 )
84
Example 7

85
Junction capacitance(2)
The sidewalls of a typical MOSFET source or drain diffusion region
are surrounded by a p + channel - stop implant, with a higher doping density
than the substrate doping density N A
Assume the sidewall doping density is given by N A(sw) ,
the zero - bias capacitance per unit area can be found as

ε Si  q  N A(sw)  N D  1
C j 0 sw =  
 
2  N A(sw) + N D  φ0 sw
C jsw = C j 0 sw  x j
The sidewall voltage equivalence factor

K eq ( sw) = −
2 0 sw
V2 − V1
(
 0 sw − V2 − 0 sw − V1 )
The equivalent large - signal junction capacitance Ceq(sw) for
a sidewall of length (perimeter) P can be
Ceq(sw) = P  C jsw  K eq(sw)
86
Example 8 (1)

87
Example 8 (2)

88