1

EE 560 COMBINATIONAL MOS LOGIC

CIRCUITS
STATIC AND DYNAMIC CHARACTERISTICS

Kenneth R. Laker, University of Pennsylvania

 VDD 2

V1
Vout is Boolean
V2 function of inputs ,
V3 COMBINATIONAL Vout
M LOGIC CIRCUIT V1, V2, V3, ...., VN.
VN Cload “1” => VDD
“0” => 0

VDD

Load CMOS => pMOS Net complement of

or Pull-Down Net
Pull-Up Net Vout
V1
V2 Cload
M Pull-Down Net
VN
Kenneth R. Laker, University of Pennsylvania
 3
MOS LOGIC CIRCUITS WITH RESISTOR LOADS
2-INPUT NOR GATE (NR2)
VDD
VDD - Vout A
+ I = Z=A+B
RL V
L
RL B
- L
IL VA VB Vout
Vout
(W/L)1 I I LOW LOW HIGH
D2
D1
LOW HIGH LOW
VA VB
(W/L)2 HIGH LOW LOW
HIGH HIGH LOWER
CUTOFF
0
k'n,d  W 
∑
IL = m(ON) 2  L  m
2(V GS,m − V )[
T 0,n outV − (Vout ) 2
LIN]
k'n,d  W 
∑
m(ON) 2
 
L m
(VGS,m − V T 0,n )2
[ SAT ]
Kenneth R. Laker, University of Pennsylvania
 4
VDD Vout Vout = Vin - VT0,n
VDD - Vout dVout
+ I L
=
RL
=-1
RL V VOH dVin SAT
- L LIN
IL A
Vout B C
(W/L)1 ID2 dVout
ID1 =-1
VA VB dVin
(W/L)2 VOL
Vin
VIL VIH VOH
IL = ID1 + ID2 VT0,n

VOH = VDD: VA = VB = 0 => ID1 = ID2 = 0 => IL = 0

VA VB Vout
VOL:
LOW VDD LOW
VDD LOW LOW
VDD VDD LOWER
Kenneth R. Laker, University of Pennsylvania
 VDD 5
VDD
+
+ RL VL
RL VL -
- IL
IL
Vout
(W/L)1 Vout
ID1 ID2 ID1 ID2
VA VB (W/L)2 G1 = G G2 = G
VA VB

VDD

RL
CASE VA VB GEQV-NR2 (W/L)EQV-NR2
Vout
1 VDD VOL G (W/L)
2 VOL G (W/L) Vin (W/L)EQV-NOR2
VDD
3 VDD VDD 2G 2(W/L)

Kenneth R. Laker, University of Pennsylvania

 TRANSIENT ANALYSIS OF 2-INPUT NOR 6

VDD For all Input Conditions:

Cload-NR2 = Cgd1 + Cgd2 + Cdb1 + Cdb2 + Cint + Cgb
= 2Cgd + 2Cdb + Cint + Cgb
RL where Cgd1 = Cgd2 = Cgd and Cdb1 = Cdb2= Cdb

Note: Cload-NR2 > Cload-INV

Vout

# Cgd1
# Cgd2 # #
D Cdb1 D Cdb2
VA G B G B # #
VB Cint
Cgb
S S
Cgs1 Csb1 Cgs2 Csb2

Kenneth R. Laker, University of Pennsylvania

CL
 VDD 7
VDD
+
RL
-VL iC= iL - iDA- iDB RL VL
iL
Vout iL
iC iD Vout
iD2 iC
(W/L)EQV
(W/L) iD1
Vin
VA VB Cload
(W/L) Cload

Recall for the INV:

For the NR2:

Cload-INV -> Cload-NR2 (input pattern independent)
kEQV -> mkn where m = 1 or 2.
VOL-INV -> VOL -NR2 (input pattern dependent)
τPHL-INV -> τPHL-NR2 (input pattern dependent)
Kenneth R. Laker, University of Pennsylvania
 8
NR2 DESIGN STRATEGY
1. Design VOL for worst case: CASE 1 or CASE 2 - VA or VB = VDD.
Set (W/L)1 = (W/L)2 = (W/L) = (W/L)EQV-NR2.
WHERE for EQV INV

2. Design for delay for worst case: CASE 1 or CASE 2 i.e. one
input switching L->H and other input set at VOL.

Cload-NR2 = 2(Cgd + Cdb) + Cint + Cgb

For the NR2: Cload-INV -> Cload-NR2 (Case 1 or Case 2)

τPHL-INV -> τPHL-NR2 VOL-INV -> VOL -NR2 (Case 1 or Case 2)
knINV -> knEQV -NR2 (Case 1 or Case 2)
Kenneth R. Laker, University of Pennsylvania
 n INPUT NOR (NRn) 9

VDD
+
RL VL
-
IL
Vout
(W/L)1 ID1 ID2 IDn
V1 V2 (W/L)2 Vn (W/L)n

k'n,d  W 
∑
m(ON) 2  L  m
2(VGS,m [
− V ) V
T 0,n out − (Vout ) 2
] LIN
IL =
k'n,d  W 
∑
m(ON) 2  L  m
(VGS,m − V[
T 0,n )2
] SAT

Kenneth R. Laker, University of Pennsylvania

 VDD VDD 10

+ +
RL VL RL VL
- -
IL IL
Vout Vout
(W/L)1 ID1 IDn ID1 ID2 IDn
ID2
V1 V2 (W/L)2 Vn (W/L)n G1 G2 Gn
V1 V2 Vn

ASSUMING ALL nMOS DRIVERS HAVE IDENTICAL, (W/L) & VGSi = VGS
= VDD for all i = 1, 2, ..., m ≤ n; otherwise VGS = VOL VDD
k'n,d  W 

[
 ∑    2(VGS − VT 0,n ) Vout − (Vout )2
2  m(ON) L m 
] LIN RL
I DL = k'n,d   W  Vout
 ∑    (VGS − VT 0,n )2 SAT
2  m(ON) L m 
Vin (W/L)EQV-NRn

n
pattern
Kenneth R. Laker, University of Pennsylvania dependent
 11
NRn DESIGN STRATEGY
 W =  W  W
∑
 L  EQV m(ON)  L  m= m  L 
1. Design VOL for worst case: Vk = VDD, Vi = VOL for all i ≠ k.
Set (W/L)1 = (W/L)2 = -- = (W/L)n = (W/L) = (W/L)EQV-NRn.
WHERE for EQV INV

2. Design for delay for worst case: Vk = VDD, Vi = VOL for all i ≠ k
i.e. one input switching L->H and all other inputs set at VOL.

Cload-INV => Cload-NRn = n(Cgd + Cdb) + Cint + Cgb

For the NRn: Cload-INV -> Cload-NRn
τPHL-INV -> τPHL-NORn VOL-INV -> VOL -NRn
Kenneth R. Laker, University of Pennsylvania knINV -> knEQV -NRn
 12
2-INPUT NAND GATE (ND2)
VDD NOTE: VSB2 =0, VSB1 ≠0 A
+ Z = AB
B
RL
-VL
IL
Vout
VA VB Vout
(W/L)1 ID1
VA IL = ID1 = ID2
LOW LOW HIGH
(W/L)2 ID2 3 cases LOW HIGH HIGH
HIGH LOW HIGH
VB HIGH HIGH LOW

Let 1 2
CALCULATION OF VOH
WHEN VA = 0 and/or VB = 0 =>IL = ID1 = ID2 = 0
VOH = VDD FOR ALL 3 INPUT CASES
Kenneth R. Laker, University of Pennsylvania
 VDD 13
VOL: VA = VDD, VB = VDD
+
RL VL
VDD -
IL
Vout
+ Let ID1
RL V 1 2
- L G
IL ID2
Vout
G
(W/L)1 ID1 IL = ID1 = ID2
VA
(W/L)2 ID2
VB
= (W/L)1
= (W/L)2

ND2 GATE WITH TWO nMOS (W/L):

Kenneth R. Laker, University of Pennsylvania

 VDD Cgd1 = Cgd2 = Cgd 14
In Pull-Up Cload & τPLH are Cgs1 = Cgs2 = Cgs
input pattern dependent RL Csb1 = Csb2 = Csb
Cdb1 = Cdb2 = Cdb Vout

V1 = VOH ## Cgd1 Cdb1 ##

D
V1 G B
## ##
V1 = VOH -> VOL # Cgs1 Vx #
Csb1 Cint Cgb
S

V2 = VOH -> VOL # Cgd2 #

Cdb2
D
V2 G B
V2 = VOH Vx -> rises
S
PULL-UP: τPLH Vx -> low
A. Vx = HIGH (LONGER DELAY CASE)
Cload = Cgd1 + Cdb1 + Cgs1 + Csb1 + Cgd2 + Cdb2 + Cint + Cgb (worst case)
= 2Cgd + 2Cdb + Cgs + Csb + Cint + Cgb
B. Vx = LOW (SHORTER DELAY CASE)
Cload = Cgd1 + Cdb1 + Cint + Cgb = Cgd + Cdb + Cint + Cgb τPLHA > τPLHB
PULL-DOWN: VA, VB = VOL -> VDD => τPHL
Cload = 2Cgd + 2Cdb + Cgs + Csb + Cint + Cgb (worst case)
Kenneth R. Laker, University of Pennsylvania
 VDD ND2 DESIGN STRATEGY 15

+
RL
- VL Vout

(W/L)EQV-ND2 Cload-ND2
Vin
FOR DESIGN:
1. Determine RL and (W/L)EQV-ND2
2. Set (W/L)1 = (W/L)2 = (W/L) = 2(W/L)EQV-ND2
INV:
where

ND2 GATE WITH TWO nMOS (W/L):

where

Cload-ND2 = 2Cgd + 2Cdb + Cgs + Csb + Cint + Cgb (worst case)

 16
n INPUT NAND GATE (NDn)
VDD
+ n
RL V
- L
NOTE: VSB1, .., VSBN-1 ≠ 0 IL
Vout
(W/L)1 ID1
If V1 = V2 =.... =VN = Vin &
V1 VT01 ≈ VT02 ≈...≈ VT0N ≈ VT0n
(W/L)2 ID2
n n
V2

(W/L)n IDn for all i=1, n (ON)

Vn

=. (W/L)1
..
= (W/L)n
Kenneth R. Laker, University of Pennsylvania
 17
CONSERVATIVE MODEL - DESIGN
Cgd1 = Cgd2 = ...=Cgdn = Cgd
VDD
VDD Cgs1 = Cgs2 = ...=Cgsn = Cgs
Csb1 = Csb2 ...=Csbn = Csb
Cdb1 = Cdb2 ...=Cdbn = Cdb RL Vout
RL
Vout
(W/L) C1
(W/L) Cload-NDn Cload-NDn
V1
V1 distributed
(W/L)
(W/L) C2
V2
V2
(W/L)
(W/L)
Vn Cn
Vn

PULL-UP τPLH: V1 = V2 =...= Vn-1 = VOH; Vn = VDD -> VOL

Cload-ND2 = n(Cgd + Cdb) + (n - 1)(Cgs + Csb) + Cint + Cgb (worst case)

PULL-DOWN τPHL: V1 = V2 =...= Vn-1 = VOH, Vn = VOL -> VDD

Cload-ND2 = n(Cgd + Cdb) + (n - 1)(Cgs + Csb) + Cint + Cgb (worst case)
Kenneth R. Laker, University of Pennsylvania
 NDn DESIGN STRATEGY VDD
18

RL
Vout

-> Find (W/L) ratio for EQV-NDn INVERTER to (W/L)

V1
satisfy VOL SPEC, i.e. for RL find (W/L)EQV-NDn.
(W/L)
V2
-> Set all (W/L) = n(W/L)EQV-NDn.
(W/L)
WHERE for EQV INV Vn

2. Design for delay for worst case Cload-NDN.

Cload-NDn = n(Cgd + Cdb) + (n - 1) (Cgs + Csb) + + Cint + Cgb

WORST CASE
Kenneth R. Laker, University of Pennsylvania
 CMOS LOGIC GATES 19

2-INPUT NOR (NR2)

VDD

S VDD
G B

D V2
pMOS
S
G B
V1 Logic
V1
IDp Vout
D
Idp Vout
IDn
V2 nMOS
D
IdnA
D
IdnB Logic
G G V1
V2 B B
S S

nMOS Net ON, pMOS Net OFF

or
nMOS Net OFF, pMOS Net ON
Kenneth R. Laker, University of Pennsylvania
 VDD FOR THE INV 20

S
Vout A B C D E
G B
VDD LIN Vin - VT0p
D
S
V1 G B SAT Vin - VT0n
D Idp Vout SAT
VDD/2
D IdnB LIN
D
IdnA G
V2 G
B B
S S - VT0p
Vin
0 VT0n VDD/2
--> VOL = 0, VOH = VDD. VDD+VT0p VDD

DEFINITION Vth: V1 = V2 = Vout = Vth

ASSUME:
1) V1 and V2 switch simultaneously
2) Assume SUB bias effect for pMOS transistors is negligible.
3) (W/L)nA = (W/L)nB = (W/L)n
4) (W/L)pA = (W/L)pB = (W/L)p
Kenneth R. Laker, University of Pennsylvania
 VDD
CMOS NR2 VDD
21

V2 S Vth(NR2) => V1 = V2 = Vout

G
kp Vth(INV) = Vin = Vout G
S
kpEQV = kp/2
D
S D
V1 G
kp Vin Vout
D Vout D
G knEQV = 2kn
S
D D
Vin G
kn G
kn
V2 V1 S
S

Symmetrical EQUIV INV

kpEQV = knEQV or kpEQV/knEQV = 1 and VTn = |VTp| => Vth(INV) = VDD/2

Vth(NR2) = VDD/2 => kp = 4kn

Kenneth R. Laker, University of Pennsylvania
 PARASITIC CAPS FOR CMOS NR2 (CONSERVATIVE) 22

VDD Cgdn1 = Cgdn2 = Cgdn

Mp2 Cdbn1 = Cdbn2 = Cdbn
S
G B Cgdp1 = Cgdp2 = Cgdp
V2
Cgdp2 D Cdbp2 Cdbp1 = Cdbp2 = Cdbp
Cgsp1 = Cgsp2 = Cgsp
Cgsp1 S
Csbp1
G B Csbp1 = Csbp2 = Csbp
V1 C
gdp1 D Cdbp1 Vout
Mp1
Cint Cgb
Cgdn1 Cgdn2
D D
Cdbn1 G
Cdbn2
V1 G V2 B
B
Mn1 S Mn2 S

WORST CASE for PULL-UP => V1 = VDD -> 0, V2 = 0:

Cload-NR2 = Cgdn1+ Cdbn1+ Cgdn2+ Cdbn2+ Cgdp1+ Cdbp1+ Cgsp1+ Csbp1+ Cgdp2+ Cdbp2 + Cint+ Cgb
= 2Cgdn+ 2Cdbn+ 2Cgdp+ 2Cdbp1 + Cgsp+Csbp + Cint + Cgb
WORST CASE for PULL-DOWN => V1 = 0 -> VDD, V2 = VDD
Cload-NR2 = 2Cgdn+ 2Cdbn+ 2Cgdp+ 2Cdbp1 + Cgsp+Csbp + Cint + Cgb
NRn: Cload-NRn = n[Cgdn+ Cdbn+ Cgdp+ Cdbp1] + (n -1)[Cgsp+ Csbp] + Cint + Cgb
Kenneth R. Laker, University of Pennsylvania
 CMOS NR DESIGN STRATEGIES 23

NR2:
1. Symmetric Inverter Vth = VDD/2:
Vth(NR2) = VDD/2 => kp = 4kn
2. Propogation delay PHL
or :
PLH

NRn:
1. Symmetric Inverter Vth = VDD/2:
Vth(NRn) = VDD/2 => kp = n2kn
2. Propogation delay PHL
or PLH
:

Kenneth R. Laker, University of Pennsylvania

 VDD 24
CMOS ND2
V2 S V1 S VDD
G
kp G
kp Vth(ND2) => V1 = V2 = Vout
D D Vth(INV) = Vin = Vout S

Vout
G
kpEQV = 2kp
D
V1 D
Vin Vout
G
kn D
S G
kpEQV = kn/2
Vin V2 D S
G kn
S

Symmetrical EQUIV INV

kpEQV = knEQV and VTn = |VTp| => Vth(INV) = VDD/2

Vth(ND2) = VDD/2 => kn = 4kp

Kenneth R. Laker, University of Pennsylvania
 PARASITIC CAPS FOR CMOS ND2 (CONSERVATIVE) 25
VDD VDD Cgdn1 = Cgdn2 = Cgdn
Mp1 S Mp2 S
Cdbn1 = Cdbn2 = Cdbn
V1 G B V2 G B Cgdp1 = Cgdp2 = Cgdp
Cgdp1 D Cdbp1 Cgdp2 D Cdbp2 Cdbp1 = Cdbp2 = Cdbp
Vout Cgsp1 = Cgsp2 = Cgsp
Cgb Csbp1 = Csbp2 = Csbp
Cgdn1 Mn1D Cint
Cdbn1
G
V1 B
Cgsn1 S
Csbn1
Cgdn2 D Cdbn2
G
V2 B
Mn2 S

WORST CASE for PULL-UP => V1 = VDD -> 0, V2 = 0:

Cload-ND2 = Cgdp1+ Cdbp1+ Cgdp2+ Cdbp2+ Cgdn1+ Cdbn1+ Cgsn1+ Csbn1+ Cgdn2+ Cdbn2 + Cint+ Cgb
= 2Cgdp+ 2Cdbp+ 2Cgdn+ 2Cdbn + Cgsn+Csbn + Cint + Cgb
WORST CASE for PULL-DOWN => V1 = 0 -> VDD, V2 = VDD
Cload-ND2 = 2Cgdp+ 2Cdbp+ 2Cgdn+ 2Cdbn + Cgsn+Csbn + Cint + Cgb
NDn: Cload-NRn = n[Cgdn+ Cdbn+ Cgdp+ Cdbp1] + (n -1)[Cgsn+ Csbn] + Cint + Cgb
Kenneth R. Laker, University of Pennsylvania
 CMOS ND DESIGN STRATEGIES 26

ND2:
1. Symmetric Inverter Vth = VDD/2:
Vth(ND2) = VDD/2 => kn = 4kp
2. Propogation delay PHL
or :
PLH

NDn:
1. Symmetric Inverter Vth = VDD/2:
Vth(NDn) = VDD/2 => kn = n2kp
2. Propogation delay PHL
or PLH
:

Kenneth R. Laker, University of Pennsylvania

 Vout,Vin MACROMODELING 27
Vout
CL = 0
5V Vout
CL1 = 0.5 pF
3V 0.5 pF
CL2 = 1.0 pF Vout
1V input
t 1.0 pF
10 ns 20 ns 30 ns Vin
τPLH = τint,LH + [(CL2- CL1)/CL2] × τext,LH τPLH = 0.26 +CL × 2.12 ns
τPHL = τint,HL + [(CL2- CL1)/CL2] × τext,HL τPHL = 0.42 + CL × 3.88 ns
Load Conditions
τPXY
Time CL = 0 CL = 0.5 pF CL = 1.0 pF
τPLH (ns) 0.26 1.32 2.38
τint,XY slope = τext,XY τ (ns)
PHL
0.42 2.36 4.30
CL
0 τext,LH (ns/pF) 0 2.12 2.12
τint,XY = τPXY|CL = 0
τext,HL (ns/pF) 0 3.88 3.88
Kenneth R. Laker, University of Pennsylvania
 28
TYPICAL CMOS NAND AND NOR DELAYS
Delays for a Family of NAND & NOR gates
1. Wn = 6.4 µm, Ln = 1 µm, and Wp = 12.8 µm, Lp = 1 µm.
2. tinput-rise/fall = 0.1 ns and Cload = 0 -> 1 pF.

a
c b τPHXY (ns) τPHXY (ns)
e d z
g f 10.0 10.0 NR8-LH
h ND8-HL
a
c b ND8-LH NR8-HL
e d z 0 CL (pF)
g f 0
0.75
CL (pF) 0.25 0.75
h 0.25

τPHXY (ns)
5.0
z z INV-HL
INV-LH
0 CL (pF)
0.25 0.75
Kenneth R. Laker, University of Pennsylvania
 29

COLOR LEGEND
VDD VDD n-Well
S p-Well
G
VA kp n+
D
S
Polysilicon
VB G
kp Vout p+
D Vout
Gate Oxide
Field Oxide
D D GND Metal 1
VA G
kn VB G
kn VA VB Metal 2
S S
Metal 3
VDD
Contact/via

STICK DIAGRAM Vout

GND
VA VB
Kenneth R. Laker, University of Pennsylvania
 VDD COLOR LEGEND 30

n-Well
S S
G p-Well
VA kp VB
G
kp
D
n+
D

Vout Polysilicon
p+
D
VA G Gate Oxide
kn
S Field Oxide
Metal 1
D
VB G kn Metal 2
S Metal 3
VDD
Contact/via

Vout

GND
Kenneth R. Laker, University of Pennsylvania
VA VB
 COMPLEX LOGIC GATES 31

Z = A(D + E) + BC
“OR” OPS PERFORMED BY PARALLEL CONECTED DRIVERS.
“AND” OPS PERFORMED BY SERIES CONNECTED DRIVERS.
“INVERSION” IS PROVIDED BY NATURE OF MOS CIRCUIT OP.
VDD

RL
Vout

A (W/L)A B (W/L)B

D E C (W/L)C
(W/L)D (W/L)E

Kenneth R. Laker, University of Pennsylvania

 32
VDD
ON Drivers Out-GND Path
RL A-D Class 1
Vout A-E Class 1
B-C Class 1
A-D-E Class 2
A (W/L)A B (W/L)B A-D-B-C Class 3
A-E-B-C Class 3
D E C (W/L)C A-D-E-B-C Class 4
(W/L)D (W/L)E G1 < G2 < G3 < G4
VOL1 > VOL2 > VOL3 > VOL4

EQV INVERTER (for case G4 where A = B = C = D = E = 1)

 W 1 1
 L  EQV = 1 1 + 1 1
+ +
 
W  
W  
W  W +  W
 L B  L  C  L  A  L D  L E
Kenneth R. Laker, University of Pennsylvania
 33
VDD
DESIGN STRATEGY:
1. Identify all WORST CASE
RL Paths (e.g. Class 1).
Vout 2. Determine nMOS
transistor sizes such that
each Class 1 path has
A (W/L)A B (W/L)B (W/L) .
EQV

D E C (W/L)C
(W/L)D (W/L)E
 W  =  W  = 2 W 
 L A  L D  L  EQV
 W  =  W  = 2 W 
 L A  L  E  L  EQV

 W =  W = 2 W
 L B  L  C  L  EQV
Kenneth R. Laker, University of Pennsylvania
 VDD 34

OPTIMIZED LAYOUT OF COMPLEX

D FULL CMOS GATES
A E
B C
Z = A(D + E) + BC

A B
D E C
ARBITRARY STICK LAYOUT
VDD
D S S D S D
D S S D
Z

D S D S D S D S S D
GND

A E B D C
 35
OTIMIZED LAYOUT OF COMPLEX FULL CMOS GATES
VDD
VDD
D D pMOS NET
A GRAPH
A E E

B C
B C
Z
Z
Z
B
A B A nMOS NET
GRAPH
D E C D E
C
GND
Kenneth R. Laker, University of Pennsylvania
 ARBITRARY ORDERING OF GATE COLUMNS VDD 36

D S S D S D
D S S D
Z

D S D S D S D S S D

A E B D C GND
VDD VDD s
s D
D s
s
sd A s Euler path - connected
A d E E
d sequence of edges
s s s s
B C B C n, p diffusions for
d d Z d
Bs
Z Z A ds common Euler paths
d d have layouts with no
A B d d
s s
d d d D E diffusion breaks.
D C s s d
E
s s s s C
GND
Kenneth R. Laker, University of Pennsylvania
 MINIMIZE NUMBER OF DIFFUSION BREAKS 37

VDD Z
s d d
D COMMON A
s d B
EULER PATH: s s
A s E-D-A-B-C d
d x dE D x dE
d
s s s s
y Is A-D-E-C-B a C
B C s VDD
s
d d common Euler y D d
path? s s
Z GND A E
d d
s s
VDD B C
d d
Z
d d
D S D S S D S D D S
A B
Z s s
d d d
D E C
D S S D S D D S D S s s s
GND
E D A B C
Kenneth R. Laker, University of Pennsylvania
 38

ALGORYTHYM FOR LINE OF GATES LAYOUT STYLE

1. Find all Euler paths that cover the graph.
2. Find common n- and p- Euler paths.
3. If no Euler paths are found in step 2, break the gate in the
minimum number of places that to achieve step 2 with
separate common Euler paths.

Kenneth R. Laker, University of Pennsylvania

 FULL CMOS XOR GATE 39

A A + B = AB + AB VDD

B
A B

A B
Vout
A +B
A
A A
B
B B

Kenneth R. Laker, University of Pennsylvania

 40
AOI & OAI GATES
AOI -> AND-OR-INVERT (for SUM - of - PRODUCTS Realization)
OAI -> OR-AND-INVERT (for PRODUCT - of - SUMS Realization)
VDD
A1
A2 Dual pMOS
A3 Pullup Net
B1 Vout Vout
B2
C1
C2 A1
C B1 C1
3

AOI A2 C2

A3 B2 C3

Kenneth R. Laker, University of Pennsylvania

 41
OAI -> OR-AND-INVERT (for PRODUCT - of - SUMS Realization)
A1 VDD
A2
A3
B1 Dual pMOS
Vout Pullup Net
B2
Vout
C1 OAI
C1

B1 B2

A1 A2 A3

Kenneth R. Laker, University of Pennsylvania

 42
Pseudo-nMOS OAI Realization

VDD

Vout
C1

B1 B2

A1 A2 A3

Kenneth R. Laker, University of Pennsylvania

 43
CMOS Transmission Gates (TGs) & TG Logic

SYMBOLS
-s SWITCH CHARACTERISTICS

a C b a b
Input Output

s s a b Srong 0
0
-s -s
1 a b Strong 1

a b a b

s s

Kenneth R. Laker, University of Pennsylvania

 0V 44

ISDp G
VSBp = 0 VDSn = VDD - Vout
IC = IDSn + ISDp
D IC V VGSn = VDD - Vout
S B out
Vin = VDD
D B S VDSp = Vout - VDD
IDSn VGSp = - VDD
G VSBn = Vout
VDD

REGION 1 REGION 2 REGION 3

nMOS: SAT nMOS: SAT nMOS: OFF
pMOS: SAT pMOS: LIN pMOS: LIN
VDSn > VGSn - VTn VDSn > VGSn - VTn VGSn < VTn
VDSp < VGSp - VTp VDSp > VGSp - VTp VDSp > VGSp - VTp
Vout
0V |VTp| (VDD - VTn) VDD

VDD − Vout VDD − Vout

R eqn = R eqp = ReqTOT = Reqn||Reqp
I DSn I SDp
Kenneth R. Laker, University of Pennsylvania
 2( VDD − Vout ) 45

R eqn =
k n (VDD − Vout − VTn )
2
REGION 1:
2( VDD − Vout )
nMOS: SAT
pMOS: SAT R eqp =
k p ( VDD − | VTp |)
2

2( VDD − Vout )
REGION 2 R eqn =
k n (VDD − Vout − VTn )
2
nMOS: SAT
pMOS: LIN 2( VDD − Vout )
R eqp =
[
k p 2(VDD − | VTp |)(VDD − Vout ) − (VDD − Vout )
2
]
2
=
[
k p 2(VDD − | VTp |) − ( VDD − Vout ) ]
REGION 3 Reqn = ∞
nMOS: OFF 2
R eqp =
[ ]
pMOS: LIN
k p 2(VDD − | VTp |) − ( VDD − Vout )
Kenneth R. Laker, University of Pennsylvania
 46

Reqp Reqn

ReqTOT = Reqn||Reqp
Vout
0
(VDD - VTn) VDD

Kenneth R. Laker, University of Pennsylvania

 47

iSDp

Vin = VDD Vout

iC
iDSn
Cload

t=0

ReqTOT
Vin = VDD Vout
t=0 iC
Cload

Kenneth R. Laker, University of Pennsylvania

 48
TRANSMISSION GATE LAYOUTS

Simple and small,

poly used to achieve metal2 used to
but no metal lines achieve
horizontal metal1
can pass horizontal metal1
transparency
horizontally transparency
n+
Routing Gate Signals to Transmission Gate Poly

p+
Metal 1
Metal 2
Contact/via

horizontal, via vertical, via poly vertical, via metal1 straps

metal1 metal2 used to achieve vertical
Kenneth R. Laker, University of Pennsylvania metal1 transparency
 49
2-INPUT MULTIPLEXER
output = A.s + B .s
-s
A B s -s output
A x 0 0 1 0 (B)
x 1 0 1 1 (B)
s
output 0 x 1 0 0 (A)
B 1 x 1 0 1 (A)

-s
XOR (COMPLEMENTARY PASS-TRANSISTOR LOGIC OR CPL)
A
B
A F = AB + AB

Kenneth R. Laker, University of Pennsylvania

 A A B B 50

F1 (AB)
VDD

F2(AB)
Z Z
F3 (AB)

F4 (AB)

SOME OF THE FUNCTIONS REALIZED BY THE

BOOLEAN FUNCTION UNIT (CPL)
OPERATION (Z) F1 F2 F3 F4
NOR(A,B) 0 0 0 1
XOR(A,B) 0 1 1 0
NAND(A,B) 0 1 1 1
AND(A,B) 1 0 0 0
OR(A,B) 1 1 1 0
Kenneth R. Laker, University of Pennsylvania