GURUGRAM UNIVERSITY

​VLSI DESIGN 4th SEM

PLACEMENT In Chip Designing

FACULTY - Dr. SUMIT CHAUDHARY BY - AMAN KUMAR, HITEN GOYAL
and HIMANSHU
System is an arrangement to secure
certain ends, so that no time may be lost
in accomplishing them ... There must be a
place for everything, and everything in
its place ...
-Samuel Smiles, Thrift, Chapter 2, 1875
 FLOORPLANING
As the name suggests Floor Planning helps create a skeletal level framework for spatial locations of standard cells,
macros, analog IPs and all other blocks on a circuit. The goal is to optimize design layout on the given die area while
keeping close tabs on probable congestion and density violations. Typically floor planning is done to make the layout
compact wherein logically connected instances are placed in close proximity to each other as well as everything else. This
is done to make effective use of the routing resources available.
We have discussed how we determine the position of larger entities such as macros,
memories, analog blocks, and input/output (I/O) pads during floorplanning. However,
we also need to decide the locations of numerous standard cells in a design. We make
these decisions during PLACEMENT. The tool that performs placement is referred to
as a placer. The primary goal of placement is to ensure that the design becomes
routable.
OBJECTIVES OF PLACEMENT
1. Minimizing Wire Length
-Reducing the total interconnect length to improve signal propagation speed and reduce delay.
2. Optimizing Routability
- Ensuring efficient routing by avoiding congestion and enabling smooth interconnections
between components.
3. Density Management
- Balancing placement density to prevent hotspots and ensure uniform utilization of the chip area.
4. Improving Performance
- Enhancing circuit performance by minimizing delays caused by interconnects and optimizing
module positions.
5. Thermal Optimization
- Distributing heat evenly across the chip to avoid overheating and ensure reliability.
Placers use cost measures that are easier to compute, such as the total wire length (WL),
rather than directly estimate the routability of a design. Intuitively, to reduce WL, a placer
should place the connected cells nearby. Therefore, minimizing total WL often improves
routability.

Moreover, a bad placement solution can make a design unroutable or prevent meeting
timing requirements. Hence, other cost measures, such as timing and congestion, are also
considered by a placer. The placement methodology that targets improving the slack of the
timing paths is known as timing-driven placement and is widely employed for industrial
designs. The placement problem is challenging due to the large number of standard cells
that needs to be placed. Placers often need to tackle more than a million cells in an industrial
design. We need to consider this aspect of the problem while developing placement
strategies.

Typically, we simplify the placement problem by dividing it into multiple tasks: Global
Placement and Legalization, followed by Detailed Placement.
 GLOBAL PLACEMENT
During the early phases of placement, we try to find approximate cell locations and treat cells as point objects . We spread the cells
over the layout reducing the cell density and minimizing some cost metrics, such as the total WL. The cell locations are decided just
by their connectivity, and we ignore the attributes of a cell, such as its size and pin locations. This task is known as global placement.

For a given circuit and its floorplan, the placement solution depends on the following factors:

1. Location of fixed objects:

A floorplan contains fixed objects. For example, I/O ports and macros. A placer is not allowed to change the location of fixed objects.
However, it can move cells connected to the fixed objects such that the total WL gets minimized. The optimal placement solution of
movable cells will depend on the location of the fixed objects specified in the floorplan and connected to them.

2. Cell connectivity:
When a cell is connected to multiple objects, we can minimize the total WL by placing it close to them. Thus, changing the connection in a
design will change the placement solution.

3. Cost function:
The placement solution depends on the cost function that we minimize during placement.
 WL Estimates
The cost function that a global placer seeks to minimize typically depends
on the WL. Therefore, a placer needs to compute the WL of each net
multiple times while finding a solution. Ideally, the computed WL should
match the post-routing WL. However, during placement, the layout of nets
is not yet decided. Therefore, the global placer needs to estimate the WL of
each net.
There are many techniques to estimate the WL during placement. These
techniques differ in the computational efficiency and accuracy with respect
to the post-routing WL. Let us look at a few commonly used WL estimation
techniques.
WL Esitimate Techniques
There are several techniques that can be used to estimate Wirelength:

1) Half-Perimeter Wirelength (HPWL)

2) Rectilinear Steiner Minimal Tree (RSMT)
3) Fast Lookup Table Based Wirelength Estimation Technique (FLUTE)
4) Machine Learning Models
5) Rent Exponent-Based Methods
Half-Perimeter Wirelength (HPWL):
Description: HPWL is a fast and simple method used to estimate wirelength
by calculating the half-perimeter of the bounding box enclosing all pins of a
net.

Advantages: Fast computation, suitable for early design stages.

Disadvantages: Less accurate, especially for high-degree nets, with an

average error of about 8% compared to more accurate methods like RSMT.
Rectilinear Steiner Minimal Tree (RSMT)
Description: RSMT provides a more accurate estimate by finding the
shortest possible wirelength for connecting all pins in a net using rectilinear
paths.

Advantages: More accurate than HPWL, especially for low-degree nets.

Disadvantages: Computationally expensive, with a time complexity of O(n

log n) for optimal algorithms, though simpler implementations may have
O(n^2) complexity.
FLUTE (Fast Lookup Table Based
Wirelength Estimation Technique)
Description: FLUTE uses pre-computed lookup tables to estimate
wirelengths quickly and accurately, particularly for low-degree nets.

Advantages: Offers high accuracy with low computational overhead,

suitable for real-time updates during placement.
Machine Learning Models
Description: Techniques like Artificial Neural Networks (ANN), Support
Vector Machines (SVM), and Random Forests (RF) are used to predict
wirelengths based on historical data.

Advantages: Can achieve high accuracy and faster runtime compared to

traditional methods like RSMT.
Rent Exponent-Based Methods
Description: These methods estimate wirelength based on the Rent
exponent, which relates the number of terminals to the size of a circuit
partition.

Advantages: Useful for understanding circuit complexity and

wirelength distribution.
Comparision Table:
LEGALIZATION AND DETAILED PLACEMENT
After global placement, cells can overlap and occupy illegal positions. We fix
these problems during the legalization and detailed placement stages.
The location of a cell produced by a global placer can be illegal due to
the following reasons:
1. Two or more cells overlap.
2. A cell occupies illegal sites, such as between cell rows.
3. Location is not aligned to the power rails and routing tracks.

Therefore, after global placement, we need to perform legalization.

 LEGALIZATION
It removes overlap between cells and snaps a cell to a legal site with minimum impact on costs such as WL, timing,
or congestion. Note that the task of legalization is not to spread cells over the layout. Typically, the spreading of cells
is undertaken during global placement by including it in its cost function. Legalization makes only incremental
changes in the placement solution such that the new location is legal, as illustrated in Figure . It finds a legal position
for an illegally placed cell or a group of cells by making the slightest movement.

Placement (a) before legalization and (b) after legalization

 TIMING-DRIVEN PLACEMENT
TDP aims to minimize delays on timing-critical paths while balancing wirelengths
and routability. It addresses challenges like growing interconnect delays, higher
integration levels, and increasing chip operating frequencies
Approaches :-
Net-Based: Focuses on individual nets, using techniques like net weighting and net constraints to optimize critical paths indirectly.

Path-Based: Directly optimizes timing-critical paths, often employing mathematical programming frameworks such as linear programming

Applications :-
Used in FPGA designs to improve clock frequencies and reduce wirelengths.

Applied in large standard cell circuits for hierarchical placement and delay control.
 ROUTABILITY-DRIVEN PLACEMENT
The primary goal is to minimize routing congestion by optimizing the distribution of
routing demand according to available routing supply. This ensures that all nets can be
routed successfully without exceeding design constraints
Techniques :-
Minimizing Routing Demand: Focuses on reducing the total wirelength, as shorter wirelengths typically result in lower routing demand.

Distributing Routing Demand: Spreads out cells in congested regions using techniques such as rough legalization and history-based cell inflation.

Applications :-
Used in both digital and analog/mixed-signal circuits to improve manufacturability and performance.

Particularly important for designs with high pin density or extreme aspect ratios, where congestion risks are higher.
 Placement Tools in VLSI Design
Synopsys IC Compiler II

Cadence Innovus

Coloquinte Place&Route

GPU-Accelerated Deep Learning Tools

Future Trends in Chip Designing Placements
1. Artificial Intelligence (AI) Integration
AI is transforming chip design by enabling automation in complex processes, improving efficiency, and optimizing designs. AI-driven tools are
increasingly used for simulation, layout optimization, and error detection, making chip design faster and more reliable.

2. 3D Integration and Advanced Packaging

The adoption of 3D integration technologies allows stacking multiple layers of chips, improving performance, reducing form factor, and addressing
memory bottlenecks. Advanced packaging methods like heterogeneous integration are becoming critical for high-performance applications.

3. Sustainability in Chip Manufacturing

With growing environmental concerns, sustainable practices in chip design and manufacturing are gaining importance. This includes using eco-
friendly materials, reducing energy consumption during production, and improving recyclability of chips.

4. In-house Chip Design

Companies are increasingly moving toward in-house chip design to gain better control over supply chains and product customization. This trend
allows for tailored solutions that meet specific application requirements while reducing reliance on external suppliers.
 Challenges in Placement
1. Increasing Design Complexity:
- Modern VLSI designs involve billions of transistors and intricate interconnections, making placement more complex. Smaller process nodes
exacerbate this issue by requiring adherence to thousands of detailed design rules.

- Solution : Implement hierarchical design methodologies and leverage AI/ML-driven EDA tools for optimized layout and verification.

2. Timing Closure and Signal Integrity:

- Ensuring timing closure and maintaining signal integrity are critical challenges due to increased interconnect density and crosstalk in advanced
nodes.

- Solution: Employ integrated timing and power optimizations during placement, and use advanced verification techniques to validate designs
early.

3. Power Management Issues:

- Power consumption is a significant concern, especially with static and dynamic power dissipation in smaller process nodes.

- Solution: Implement low-power design techniques like clock gating and dynamic voltage scaling, and leverage AI-driven power optimization
strategies.
4. Scalability and Runtime Efficiency:
- As designs grow in complexity, the runtime and scalability of placement algorithms become critical challenges.

- Solution: Utilize parallel computing methods and advanced tool features to improve efficiency without compromising accuracy.

5. Verification and Debugging Challenges:

Verification consumes a significant portion of the design cycle, and debugging complex designs is increasingly difficult.

- Solution: Employ formal verification, hardware emulation, and digital twins to validate designs early and reduce debugging time.
 CONCLUSION
VLSI placement is a complex and critical step in the design of integrated
circuits, influenced by various techniques, tools, and future trends. The
challenges faced in placement, such as design complexity, power
management, necessitate innovative solutions like AI-driven optimizations
and advanced verification methods. As technology advances, the
integration of machine learning, hierarchical design methodologies, and
scalable algorithms will be pivotal in overcoming these challenges and
achieving efficient, high-performance placements.
Presentation by
​AMAN KUMAR
HITEN GOYAL
HIMANSHU
B.Tech VLSI 4th Sem

Thank you.