MODULE 1:

1. Explain working and electrical characteristics of MOSFET

- In n-channel MOSFETs, a p-type semiconductor (silicon) is used as a substrate or as the parent
body.
- There are two n-type wells (equal in size) that are not connected to each other by any channel
in case of enhancement type MOSFET.
- There are 2 junctions between these n-type wells and the p-type substrate. There is a depletion
region between each of the n-wells and the p-type substrate.
- Out of the two n-wells, one will act as Source and the other will act as Drain. Metal contacts are
used to connect the n-wells with source and drain terminals.
- The Gate terminal is isolated from the substrate by a thin Silicon Di-oxide (SiO2) insulation
layer also known as gate oxide, having width of approximately 1000 A° (angstrom). This layer
is made very thin as to have control over the surface by the gate electrode. Hence MOSFETs are
also known as Insulated Gate FETs (IGFETs).

- Due to presence of Silicon Di-oxide (SiO2) layer, the input impedance of MOSFET is high which
is desirable.

Operation:
- The operation can be explained with two different operating conditions:

1. Operation with VGS = 0 Volts:

- If VGS = 0 and a positive voltage is applied between the drain and source (+VDS), then due to the
absence of a channel between drain and source, there will be no flow of drain current. ID = IDSS
= IS = 0 at VGS = 0.
2. Operation when VGS is positive:
- If a positive voltage is applied between the drain and source (+V DS) and the gate terminal (as
shown in figure), then the positive potential at the gate terminal will repel the holes present in
the p-type substrate.
- But the minority carriers (electrons) in the p-type substrate will get attracted towards the positive
gate terminal and gather near the surface of SiO2 layer. This results in creation of a depletion
region near the SiO2 layer.
- Note: For an n-channel MOSFET with a p-type substrate, a positive gate voltage must be applied
to create the e– inversion layer (induced n-channel layer).
- As we increase the positive gate supply (+VGS) by keeping VDS constant, the number of
electrons gathering near the SiO2 layer will increase. The electron concentration near the SiO2
layer will increase to such an extent that it creates an induced n-channel which connects the
n-type doped regions.
- The drain current then starts flowing through this induced n-channel.
- The value of VGS at which the conduction begins is known as the ‘threshold voltage’ which is
indicated VT or VGS (TH). For n-channel E-MOSFET it is denoted by VTN.
- Here VDS < VGS – VTN and VGS > VTN. Therefore the MOSFET is operating in the linear/ohmic
region as a voltage-controlled resistor.
- In other words, for the fixed value of VDS, as we change the value of VGS, the width of the induced
n-channel will change i.e., effectively the channel resistance will change.
Effect of Increase in the Drain to Source Voltage (VDS):
- If the positive gate to source voltage (VGS) is kept constant and drain to source voltage (VDS) is
increased gradually, the gate terminal gradually becomes less positive with respect to the drain.
- Hence, less number of electrons are attracted towards gate terminal and the induced n-channel at
the drain terminal becomes narrow.

- Eventually, the n-channel width at the drain side will be reduced to a point of ‘pinch-off’ i.e. its
width will become 0 at the drain side and the MOSFET will enter saturation region.
 - This means that any further increase in VDS at the fixed value of VGS will not affect the value of
drain current (ID) to increase.
- The value of VDS at which the pinch-off condition occurs is known as ‘saturation’.
- Here VDS ≥ VGS – VTN and VGS > VTN. The VGS – VTN defines the extra voltage than the threshold
and defines the width of the induced n-channel.
- Therefore the MOSFET is operating in the saturation region.

V-I Characteristics:

The V-I characteristics of n-channel E-MOSFET can be divided into 4 regions:

1. Cutoff region:
When no positive bias voltage is applied to the gate terminal (VGS = 0), it can be said that two
back-to-back diodes in series between drain and source exist that prevent conduction of current
from D to S when VDS is applied.
Hence when VGS = 0, even if we increase the VDS, there will still be no flow of drain current and
ID = 0. The MOSFET is in cutoff region.
2. Ohmic region / Linear region / Triode region with very small VDS:
When a positive bias voltage is applied to the gate terminal more than the threshold voltage (VGS
> VTN), an n-channel will be formed between D and S. When a very small VDS (in mV) is applied,
the decrease in the width of the channel on the drain side will be very small and hence the resistance
will be negligible.
 Hence with a constant VGS, for small values of VDS, increase in the drain current ID is almost linear
with increase in voltage VDS.
Due to this characteristic, the MOSFET is said to be in linear region.
3. Non-Linear region / Triode region with comparatively larger VDS:
When a positive bias voltage is applied to the gate terminal more than the threshold voltage (VGS
> VTN), an n-channel will be formed between D and S.
When a drain to source voltage VDS higher than the value of VDS in ohmic region is applied, the
decrease in the width of the channel on the drain side will be much more (channel width will be
much smaller) and hence the resistance of the channel will increase.
Hence in this region, with a constant VGS, increase in the drain current ID w.r.t. voltage VDS is not
linear, but in a curve with increase in VDS. Due to this characteristic, the MOSFET is said to be in
non-linear region.

4. Saturation region:
When the drain to source voltage VDS is further increased and reaches to a value such that VDS ≥
VGS – VTN (where VGS – VTN is the width of the induced n-channel), then the channel at the drain
side will get completely vanished, i.e., the width of the channel on the drain side will be equal to
zero.
This act of the channel width becoming 0 at the drain side is known as pinching-off of the channel.
Hence in this region, with a constant VGS, when VDS ≥ VGS – VTN, further increase in VDS leads to
no increase (ideally) in the drain current ID.
The voltage at which the saturation occurs is given as VDS (sat) = VSG – VTN.
The reason for drain current ID still flowing even in absence of the channel is because the junction
between the n+ drain and the p-type substrate is heavily reverse biased which creates a strong
electric field capable of attracting electrons towards drain.
Due to this characteristic, the MOSFET is said to be in saturation region.
2. Find the drain current in saturation region and linear region for n-channel
EMOSFET.
- It is observed that the current (I) flowing in a semiconductor is the product of charge density
along the direction of current flow and the velocity of the charge carriers.
I=Q×v (Q = charge, v = velocity of electrons)
- Furthermore, the charge (Q) in channel can be expressed as:
Q=C×V (C = effective capacitance, V = voltage)

(a) For Linear (Non-Saturation) Region:

- Let us consider a very small portion of the n-channel of length ‘L’ at a point ‘X’ from the source,
and let the voltage at this point be VX.
- The voltage between the gate and this point will be VGS – VX. This voltage must be greater than
the threshold voltage VTN.
- Therefore, the charge in this infinitesimal (extremely small) portion of the n-channel can be
expressed as:
QX = C [VGS – VTN – VX]
- Also, the effective capacitance (C) is the product of capacitance per unit area (Cox) (of the parallel
plate capacitor formed by the gate and the channel) and the area (W) (or width of the device).
QX = W Cox [VGS – VTN – VX]
where, capacitance per unit area (Cox) = εox / tox [εox being the permittivity of silicon dioxide
and tox being the thickness of the oxide layer]
- Therefore, the drain current can be given as:
ID = – [W Cox [VGS – VTN – VX]] × v
(since the charge in nMOS is carried by electrons, a negative sign appears in this expression)
- The carrier drift velocity (v) (or velocity of electrons) is proportional to the mobility of the carriers
(µ = µn for electrons) and lateral electric field between source and drain. It can be given as:
v=µE
- The Voltage VDS produces an electric field along the channel in the negative X direction which
can be given as:
EX = – dVX
dx
- Since the electron charges, due to the presence of electric field EX, drift towards the drain with a
velocity dx/dt, the velocity of electrons can be given as:
v = dx = µn EX
dt
dx = µn [– dVX / dx] = – µn dVX
dt dx

- Therefore, the drain current (ID) at point ‘X’ becomes:

ID = W Cox [VGS – VTN – VX] × µn dVX
dx
- The constant drain current (ID) at all the points in the channel can be calculated by:
ID dx = W Cox [VGS – VTN – VX] × µn dVX … (eqn 1)
Integrating on both sides for X=0 and X=L, and correspondingly for V(0) to V(L)=VDS, we get:
𝑳 𝑽𝒅𝒔
∫𝟎 𝐈𝐝 𝐝𝐱 = ∫𝟎 𝐖 𝐂𝐨𝐱 [𝐕𝐆𝐒 – 𝐕𝐓𝐍 – 𝐕𝐱] × µ𝐧 𝐝𝐕𝐱
 L × ID = (µn Cox) W [(VGS × VDS) – (VTN × VDS ) – (VDS2/2)]
ID = (µn Cox) (W/L) [(VGS – VTN) VDS – (VDS2/2)] … (eqn 2)
ID = KN [(VGS – VTN) VDS – (VDS /2)]
2

where, [KN = β] is the device transconductance, and [µn Cox = KN’] is the process transconductance
parameter that is constant and determined by the processing technology used to fabricate the MOS
transistor.
- It is seen that the drain current (ID) is proportional to the ratio of the channel width to the channel
length, which can be selected by the designer to obtain the desired V-I characteristics.
- When the device is in cutoff region, the voltage VGS is lesser than the threshold voltage VTN, and
the device does not conduct as the n-channel is not formed. Therefore, ID in cutoff region is zero.

(b) Saturation Region:

- The peak value of the drain current can be calculated at Vsat (saturation voltage) when VDS = VGS
– VTH.
- Assuming that the ID remains constant with further increase in VDS from the Vsat, we can
differentiate (eqn 2) to zero, i.e. ∂ID/ ∂VDS = 0, to obtain the expression of the peak value of the
drain current.
- Therefore,
∂ ID = ∂ [(µn Cox) (W/L) [(VGS – VTN) VDS – (VDS2/2)]]
∂VDS ∂VDS
0 = (µn Cox) (W/L) [(VGS – VTN) (1) – (2VDS/2)]
0 = VGS – VTN – VDS
VDS = VGS – VTN = Vsat … (eqn 3)
- From (eqn 2) and (eqn 3) we get,
ID = (µn Cox) (W/L) [(VGS – VTN) VDS – (VDS2/2)]
ID = (µn Cox) (W/L) [(VGS – VTN) (VGS – VTN) – ((VGS – VTN)2/2)]
ID = (µn Cox) (W/L) [(VGS – VTN)2 – ((VGS – VTN)2/2)]
ID = (µn Cox) (W/L) (VGS – VTN)2 … (eqn 4)
2
ID = KN (VGS – VTN)2 = βN (VGS – VTN)2
2 2

Region of operation V-I Relationship for nMOS

Linear Region ID = (µn Cox) (W/L) [(VGS – VTN) VDS – VDS2]
(VGS ≥ VTN), (VDS < VGS – VTN) 2
Saturation Region ID = (µn Cox) (W/L) (VGS – VTN)2
(VGS ≥ VTN), (VDS ≥ VGS – VTN) 2
3. What is channel length modulation.

- When a MOSFET operates in saturation region (VDS ≥ VGS – VTN), the channel is pinched-off at
the drain which means, further increase in the VDS has no effect on the channel’s shape, and the
drain current ideally remains constant.
- However, in practice, the channel is affected on increasing the VDS beyond Vsat. This happens due
to the channel pinch-off point being moved slightly away from the drain towards the source,
i.e. effective channel length (L) decreases slightly as the VDS increases.
- Since the drain current (ID) is inversely proportional to the channel length (L) [as given in (eqn 4)],
the decrease in channel length tends to increase the ID with increase in VDS. This phenomenon is
known as ‘Channel Length Modulation’.

- This effect is similar to the Early effect in BJTs and is quantified using λ (CLM coefficient).
- The saturated current can be approximated by adding a factor [1 + λ· (VDS - VDS(sat))] to the peak
saturation current (ID when VDS = VGS – VTN):
ID = (µn Cox) (W/L) (VGS – VTP)2 (1 + λ·ΔVDS) … (eqn 5)
2
ID = ID(sat) (1 + λ·ΔVDS)
- To get the value of λ, we put ID = 0 in the above eqn:
0 = ID(sat) (1 + λ·ΔVDS)
0 = (1 – λ·VA)
VA = 1 / λ

I-V Curve for nMOS Device

- In short-channel MOSFETs, λ is higher, meaning more variation in ID with VDS. In long-channel

MOSFETs, λ is smaller, making the MOSFET behave closer to an ideal current source.
4. What is body effect for nMOS

- All similar type (n-channel or p-channel) MOSFETs are fabricated on a common substrate.
Therefore, the substrate voltage of all the devices is normally equal.
- In order to keep the substrate-to-channel junctions in the cut off condition, the substrate is
normally connected to the most negative power supply in nMOS.
- But in a MOSFET circuit, multiple MOS transistors may require to be connected in series. This
may result to an increase in source-to-substrate (body) voltage (VSB), as we proceed vertically
along the series chain.

- Under normal conditions, when VGS > VTN, the depletion width remains constant and the charge
carriers are pulled into the channel from the source. However, as the substrate-bias voltage is
increased, the width of the substrate-to-channel depletion layer also increases, resulting in an
increase in the density of the trapped carriers in the depletion layer.

- The resultant effect is that the substrate voltage adds to the channel-to-substrate junction potential,
which increases the gate-to-channel voltage drop. This increases the threshold voltage (VT2 > VT1
for the MOSFETs in series).
- This change (increase) in the threshold voltage with respect to the voltage difference substrate
between source of the MOSFET is known as the body bias effect.
- The threshold voltage in the presence of body effect is given by:

where, VT = threshold voltage in the presence of body effect (when VSB > 0)
VT0 = threshold voltage absence body effect (when VSB = 0)
γ = body coefficient (depends on oxide and depletion capacitance)
ϕF = Fermi potential (0.3 to 0.4V approx. for silicon) (denotes doping level)
[ϕF is -ve for nMOS and +ve for pMOS]
 - For the charge neutrality to hold, the channel charge must decrease (which can be achieved by VB
> 0), but to keep the source and drain junctions remain reverse biased, we apply body voltage VB
< 0, which results in higher VT (i.e., the body effect).
- In simple terms, if the source is also grounded like the body (substrate) which is typically
grounded, then VSB = 0V (no body effect). However, if the source is at a higher potential than
the body, i.e., VSB > 0V (body effect), the depletion region widens, requiring a higher gate voltage
to turn ON the transistor. This leads to an increase in the threshold voltage VT.

5. What are short channel effects explain.

- A MOSFET is called a short channel device, if its effective channel length (L) is approximately equal
to the source and drain junction depth (xjS and xjD).
- As the channel length L is reduced to increase both the operation speed and the number of components
per chip, short-channel effects arise.

- The short-channel effects are attributed to two physical phenomena:

1. Limitation imposed on electron drift characteristics in the channel
2. Modification of the threshold voltage (VT) due to the shortening channel length.
- In particular five different short-channel effects can be distinguished:
1) Drain-induced Barrier Lowering:
- In long channel MOSFETs, VGS is solely responsible for the formation of depletion region
beneath the gate (i.e., QB).
- When VGS < VT, the inversion layer is not completely formed, and carriers in the channel face a
potential barrier that blocks the flow of current (ID). When VGS > VT, it reduces the potential barrier
and allows the flow of current (ID).
- But in short channel MOSFETs, the drain and the source bias (VDS) are also responsible for
the formation of depletion region below the gate.
- This implies that for the same amount of VDS less gate voltage (VGS) is required to deplete the QB.
Thus, the potential barrier for electron injection from source to drain decreases. This is known as
Drain-Induced Barrier Lowering (DIBL).
- The reduction in potential barrier allows current flow between source and drain even if VGS < VT.
The channel current flowing under this condition is known as sub-threshold current [in DIBL weak
inversion takes place].

2) Punch-through:
- In short channel MOSFETs, if the channel length (L) becomes extremely short, when a high VDS
is applied, the depletion region from the drain can merge with the depletion region from the
source. This is known as punch-through.
- It may be possible that when VDS is applied, the MOSFET may turn ON even when zero to very
little VGS is applied. Also, this does not allow the device to turned off even if VDS is decreased
significantly.

3) Surface Scattering:
- In short-channel MOSFETs, when the gate voltage (VGS) increases, it creates a strong electric
field perpendicular (vertical) to the silicon surface. This forces the electrons to come close to
the Si-O2 interface, where they interact with surface roughness and oxide charges.
- Since the interface between silicon and silicon dioxide (Si-O2) is not perfectly smooth, electrons
moving swiftly near this rough Si-O2 interface collide with irregularities, scattering in
random directions.
- Instead of flowing smoothly, carriers (electrons) get deflected, experiencing increased
resistance. This effect is more pronounced for higher gate voltages, which pull carriers closer to
the rough interface.
- This phenomenon in short channel MOSFETs is known as surface scattering.

Vertical Electric Field due to VGS and Carrier Surface Scattering

4) Velocity Saturation:
- In long-channel MOSFETs, carrier velocity (v) increases linearly with electric field (E) as the
drift velocity (vd) follows the Ohm’s law [Vd = μ E].
- But in short-channel MOSFETs, due to surface scattering, at high electric fields, the carrier
velocity saturates at ‘Vd(sat)’ (saturation velocity) instead of increasing further.
- This happens because, for short-channel MOSFETs the channel length (L) is very small, and
hence the electric field [E = Vd / L] is very high.
- As the electric field increases, due to scattering and increased resistance, the drift velocity (Vd)
tends to increase more slowly, and cannot exceed a certain value resulting in velocity saturation.

- In short-channel MOSFETs the velocity of the carriers can be given as:

Vd = μE for for E ≤ EC
1 + E/EC
Vd = Vsat for for E > EC
where, E = VDS / L,
E = applied electric field
EC = electric field for which velocity saturation occurs

5) Impact Ionization:
- In short-channel MOSFETs, when the drain-to-source voltage (VDS) is high, the electric field near
the drain is very strong. This strong field accelerates charge carriers (electrons in nMOS, holes
in pMOS) to very high energies.
 - These high-energy carriers (hot carriers) get injected speedily from the source through the
substrate to the drain, and collide with the silicon atoms, breaking covalent bonds and
generating electron-hole pairs.
- This process of generation of electron-hole pairs due to high VDS is called impact ionization.
- Due to this, the extra carriers may increase drain current, causing device instability. The electrons
may also escape the drain fields and affect other devices.
- Some of the generated holes travel to the substrate and increase the body effect, shifting the
threshold voltage (VT).

6) Hot Electrons:
- In short-channel MOSFETs, when the drain-to-source voltage (VDS) is high, the electric field near
the drain is very strong. This strong field accelerates charge carriers (electrons in nMOS, holes in
pMOS) to very high energies.
- When electrons gain high kinetic energy due to a strong electric field, they become ‘hot’ (high-
energy carriers).
- If these hot electrons have enough kinetic energy, they can penetrate the gate oxide (Si-O2) and
get trapped
- This will lead to oxide charging, shifting of the threshold voltage (VT) and reduction in the
transistor’s lifespan, thus degrading the MOSFET performance over time.

❖ Mitigation Techniques of Different Short-Channel Effects:

- To reduce the effect of DIBL and punch-through:
i) Increase substrate doping to control depletion region expansion.
ii) Use Lightly Doped Drain (LDD) structures to reduce the peak electric field and avoid weak
inversion.
iii) Reducing oxide thickness (thin Gate-Oxides) strengthening the gate control and making the
threshold voltage less sensitive to drain voltage variations.
iv) Implementing High-k (high permittivity) dielectrics to increase gate capacitance without requiring
an extremely thin oxide layer. This enhances gate control over the channel.
- To reduce the effect of surface scattering and velocity saturation:
i) Use strained silicon to enhance carrier mobility.
ii) Reduce vertical electric field by optimizing gate oxide thickness.
iii) Improve interface quality to minimize surface roughness scattering.
iv) Use higher mobility materials (e.g., GaAs, SiGe).
- To reduce the effect of impact ionization and hot electrons:
i) Reduce the VDS preventing electrons from gaining excessive energy.
ii) Use Lightly Doped Drain (LDD) structures to reduce the peak electric field.
6. What is effect of scaling on MOSFET.
- Although scaling has resulted in significant benefits like reduction in power dissipation, increase in
switching speed and reduction in strip size, there are practical limitations of the miniaturization
process.
1) Effect due to silicon dioxide thickness: On scaling Gate-oxide thickness (tox), eventually a stage
will reach when the oxide will lose its dielectric property and will have to be replaced by some
other dielectric material.
2) The minimum size of transistor is dependent on accuracy and resolution of lithography techniques.
Hence there is limitation imposed on the scaling process.
3) Subthreshold current: In smaller devices, in addition to VGS, VDS also has a great influence on the
carrier flow in the channel. In short channel MOSFETS, if VDS is increased, less VGS is required
to deplete the potential barrier, and electrons start to get injected from source to drain.
Thus, the carriers in the channel can be increased by increasing the VDS and the potential barrier
can also be reduced even when the VGS is less than the VT. This results to the device operating in
the weak inversion layer and conduction of sub-threshold current.
4) Affects reliability: Scaling process inevitably results in noise problems which degrades the
reliability of high-density chip layouts.

7. Explain types of scaling.

8. Difference between types of scaling.
Similar answer for Q7 and Q8.

- MOSFET scaling refers to the process of reducing the physical dimensions of a MOSFET while
maintaining or improving its performance.
- Scaling is crucial for increasing transistor density, improving speed, reducing die cost, and
reducing power consumption in MOS integrated circuits.
- Scaling is done with symmetric reduction of overall dimensions of the device while keeping its
geometric ratios preserved.
- The scaled device is obtained by dividing all horizontal and vertical dimensions of the large size
transistor by a constant scaling factor ‘S’ (S ≥ 1, generally S = 1.2 to 1.5 for next generation).
- There are some physical limitations that eventually restrict the extent of scaling that is practically
achievable. Due to scaling, some variations in the MOSFET characteristics are expected as well.
- There are two major types of scaling models:
(1) Contant-Field / Full Scaling:
- In this model, all dimensions of the MOSFET are reduced proportionally by a scaling factor
‘S’, while maintaining constant electric field strength.
- The effect on various parameters due to constant-field scaling are:
Parameter Scaling Factor Scaled value
Threshold voltage (VT) 1/S VT* = VT / S
Channel length (L) 1/S L* = L / S
Channel width (W) 1/S W* = W / S
Gate-oxide thickness (tox) 1/S tox* = tox / S
Gate-oxide capacitance
S Cox* = Cox · S
per unit area (Cox)
Junction depth (xj) 1/S xj* = xj / S
 Doping concentration (N) S N* = N · S
Supply voltage (VDD) 1/S VDD* = VDD / S
ID(linear)* = (µn Cox*) (W*/L*)
[(VGS* – VTN*) VDS* –
(VDS2 */2)]
= (µn S Cox) (S·W/S·L)
[(VGS/S – VTN/S)
VDS/S – (VDS2/2·S2)]
= [S/S2] (µn Cox) (W/L)
[(VGS – VTN) VDS –
Drain current (ID) [linear
1/S (VDS2/2)]
& sat]
= ID(linear) / S
ID(sat)* = (µn Cox* / 2) (W*/L*)
(VGS* – VTN*)2
= (µn S Cox/2) (S·W/S·L)
(VGS/S – VTN/S)2
= [S/S2] (µn Cox/2) (W/L)
(VGS – VTN)2
= ID(sat) / S
Channel resistance (RON) Constant RON* = RON
Pdiss* = (VDD / S) × (ID / S)
Power Dissipation (Pdiss) 1/S2
= Pdiss / S2
Pd* = (Pdiss/S2) / [(L/S) × (W/S)]
Power Density (Pd or
Constant = Pdiss / (L×W)
Power/Area)
= Pd
Gate delay (Td) 1/S Td* = Td / S
Electric field (E) Constant E* = E

(2) Contant-Voltage Scaling:

- In this model, all dimensions of the MOSFET are reduced proportionally by a scaling factor
‘S’ (as done in full-scaling), but the power supply voltages and the terminal voltages remain
unchanged.
- The effect on various parameters due to constant-voltage scaling are:
Parameter Scaling Factor Scaled value
Threshold voltage (VT) Constant VT* = VT
Channel length (L) 1/S L* = L / S
Channel width (W) 1/S W* = W / S
Gate-oxide thickness (tox) 1/S tox* = tox / S
Gate-oxide capacitance
S Cox* = Cox · S
per unit area (Cox)
Junction depth (xj) 1/S xj* = xj / S
Doping concentration (N) S N* = N · S
Supply voltage (VDD) Constant VDD* = VDD
ID(linear)* = (µn Cox*) (W*/L*)
[(VGS – VTN) VDS –
Drain current (ID) [linear (VDS2/2)]
S
& sat] = (µn S Cox) (S·W/S·L)
[(VGS – VTN) VDS –
(VDS2/2)]
 = [S] (µn Cox) (W/L)
[(VGS – VTN) VDS –
(VDS2/2)]
= ID(linear) · S
ID(sat)* = (µn Cox* / 2) (W*/L*)
(VGS – VTN)2
= (µn S Cox/2) (S·W/S·L)
(VGS – VTN)2
= [S] (µn Cox/2) (W/L)
(VGS – VTN)2
= ID(sat) · S
Channel resistance (RON) 1/S RON* = RON / S
Pdiss* = VDD × (S · ID)
Power Dissipation (Pdiss) S
= Pdiss · S
Pd* = (S·Pdiss) / [(L/S) × (W/S)]
Power Density (Pd or
S3 = [S3] (Pdiss) / (L×W)
Power/Area)
= S 3 · Pd
Gate delay (Td) 1/S2 Td* = Td / S2
Electric field (E) S3 E* = S3 · E
- Constant-voltage scaling model may be preferred over full-scaling in many practical cases
because of the external voltage level constraints.
- However, this model increases the drain current (ID) by a factor of S and Power Density by a factor
of S3, eventually causing reliability problems.
- Therefore, the General Scaling model, in which the voltages and dimensions are scaled with
different factors is more ideal for today’s situation.

9. Write short note on MOSFET capacitance.

- The V-I characteristics of MOSFET gives the details about the DC response of MOS circuits under
various operating conditions. Similarly, in order to examine the transient (AC) response of
MOSFETs, we have to examine the nature and the amount of parasitic capacitances associated
with the MOS transistor.
- MOSFETs have several on-chip capacitances that are the functions of their layout geometrics (W, L,
tox, etc.). These capacitances are lumped (not distributed) and are complex to calculate.
- These capacitances impact their performance, especially in high-speed and analog applications. The
key capacitances are:

where, C1 (CGSov) and C2 (CGDov) – overlap capacitances (gate-source and gate-drain)

C3 (CG) – gate to channel capacitance
 C4 (CSB) and C5 (CDB) – source-substrate & drain-substrate junction capacitances
C6 (Cd) – depletion capacitance between channel and substrate (body)
- These parasitic capacitances can be classified into two major groups:
1) Oxide Capacitances [CGB (total), CGD (total) and CGS (total)]:
(i) Overlap Capacitances [C1 (CGSov) and C2 (CGDov)]:
CGSov = CGDov = Cox · W · L [W = channel width, L = channel length]
and Cox = εox / tox
(capacitance/unit area) = (permittivity of Si-O2) / (thickness of Si-O2)
(ii) Channel Capacitance:
Capacitance due to the formation of inversion layer is called channel capacitance. It creates channel
charge necessary for operation.
When MOSFET is operating in different modes, these capacitances values are different.
(a) During cutoff mode, there is no conducting channel that links source and drain. Hence, gate-
source and gate-drain capacitances are 0.
CGScc = CGDcc = 0 (but overlap capacitance is present)
Only the capacitance between gate and substrate is present.
CGBcc = Cox · W · L (but overlap capacitance is absent)
(b) During linear mode, the channel is present between source and drain. The channel is wider
towards the source that at the drain, as the drain voltage is higher than the source voltage.
The inversion layer shields the gate from the substrate electrically. Hence, gate-substrate
capacitance is 0.
CGBcc = 0 (overlap capacitance is also absent)
Only the gate-source and gate-drain capacitances are present.
CGScc + CGDcc = Cox · W · L
Since the gate-source and gate-drain capacitances are in parallel and equal,
CGScc = CGDcc ≈ (1/2) Cox · W · L (overlap capacitance is also present)
(c) During saturation mode, the inversion layer is present but it does not extend to the drain it is
pinched-off. The channel is only towards the source.
Therefore, gate-drain capacitance is zero. The inversion layer shields the gate from the substrate
electrically. Hence, gate-substrate capacitance is also zero.
CGBcc = 0 (overlap capacitance is also absent)
and CGDcc = 0 (but overlap capacitance is present)
The gate-drain capacitance is present,
CGScc ≈ (2/3) Cox · W · L (overlap capacitance is also present)

Combining these distributed capacitance values of channel capacitance with the overlap capacitance,
we get:
Capacitance Cut-off Liner Saturation
CGB (total) = CGBcc Cox WL 0 0
CGD (total) = CGDov + CGDcc Cox WL Cox WL + ½ Cox WL Cox WL
CGS (total) = CGSov + CGScc Cox WL Cox WL + ½ Cox WL Cox WL + 2/3 Cox WL
2) Junction Capacitances [C4 (Csb) and C5 (Cdb)]:
- The capacitances due to normally reverse biased source-substrate and drain-substrate junctions are
known as junction capacitances.
- To calculate the depletion capacitance of the reverse bias abrupt p-n junction [C6 (Cd) i.e., depletion
capacitance between channel and substrate (body)], consider:

where, xd = depletion region thickness

εsi = permittivity of silicon
q = charge of an electron
NA = acceptor doping concentration (P-type region)
ND = donor doping concentration (N-type region)
ϕ0 = built-in potential of the junction
V = applied reverse-bias voltage
and, built-in potential of the junction (ϕ0) can be given as:

- The junction is forward biased for positive bias voltage and reverse biased for negative bias
voltage.
- The depletion region charge stored in this area can be written in terms of depletion region thickness
(xd) as:

… eqn (1)
where, Qj = Charge stored in the depletion region
A = Cross-sectional area of the junction
- The junction capacitance associated with the depletion is defined as:
- The expression of junction capacitance can be obtained by differentiating the above equation with
respect to the bias voltage,

… eqn (2)
- A more generalized model where ‘Cj0’ is the junction capacitance at zero bias can be given as,

… eqn (3)
where, m is the grading coefficient
[m=1/2 for an abrupt junction m=1/3 for a linearly graded junction]
- When the gate terminal voltage (VGS) of MOSFET is changed during dynamic operation,
instantaneous values of all the junction capacitances will also change accordingly. Hence, the zero
bias junction capacitance per unit area ‘Cj0’ is a function of external bias voltage. It is defined as:

- The equivalent average large signal capacitance when bias voltage changes from V1 to V2 can be
given as,

- Substituting eqn (1) in the above expression, we get,

- This can be written in simpler form with dimensionless coefficient Keq as,

where,
 - ‘Keq’ is the equivalent factor that determines the voltage-dependent variation of the junction
capacitance. It varies between 0 and 1 and simplifies the calculation by normalizing capacitance
variations.

10.Explain fabrication process of

a) N channel MOSFET
1. Generation of p-type wafer

2. Formation of gate-oxide layer

3. Placement of photoresist

4. Exposure to UV light (negative photoresist used below)

5. Etching to create window in the oxide layer

6. Placement of thin oxide and polysilicon layer

7. Etching of unwanted oxide and polysilicon layer to form gate

8. Ion Implantation to form n-wells and formation of additional insulating oxide layer

9. Adding of Dielectric and deposition of Interconnect Layers (Metallization) and final insulation

b) CMOS
- CMOS fabrication involves creating both NMOS and PMOS transistors on a single silicon
wafer.
- Since the substrate requirement for the complementary transistors is different, ‘well technology’
is used to fabricate CMOS.
- If p-type substrate is used, then the nMOS transistor is implemented directly on the p-type substrate
while the pMOS transistor is fabricated in a specifically created n-type region, known as an n-well.
- If n-type substrate is used, then the pMOS transistor is implemented directly on the n-type substrate
while the nMOS transistor is fabricated in a specifically created p-type region, known as an p-well.
- The two transistors are isolated from each other by a thick oxide also known as field-oxide.
1. Generation of wafer (n-type substrate is used hence pMOS transistor is implemented directly while
nMOS transistor is fabricated in a specifically created p-well)

2. Formation of gate-oxide layer

3. Formation of thicker sacrificial Silicon Nitride layer

4. Placement of photoresist, exposure to UV light and plasma etching to create window in the oxide
layer

5. Isolation - trenches are filled with Si-O2 which is called as the field oxide (LOCOS)

6. Etching of excessive and unwanted field-oxide

7. Ion Implantation to generate a p-well to act as a substrate for nMOS fabrication

8. Doping n-type impurity to increase the doping level of the substrate to adjust the threshold voltage
of pMOS transistor

9. Placement of thin oxide and polysilicon layer using a mask

 10. Ion Implantation to generate p-wells and n-wells to dope the source and drain regions of the pMOS
(p+) and nMOS (n+) transistors respectively

11. Adding of Dielectric and deposition of Interconnect Layers (Metallization) and final insulation
(over glass). [Interconnect metals may be added in 2 levels or more. In modern processes, upto
eight metal levels are used]

11.Note down lambda based design rules.

Layer Type of Rule Value

R1] Minimum active area width 3λ
Active area
R2] Minimum active area spacing 3λ
R3] Minimum polysilicon width 2λ
R4] Minimum polysilicon spacing 2λ
R5] Minimum gate extension of poly over active 2λ
Polysilicon R6] Minimum poly-active edge spacing (polysilicon 1λ
outside active area)
R7] Minimum poly-active edge spacing (polysilicon 3λ
inside active area)
R8] Minimum metal width 3λ
Metal
R9] Minimum metal spacing 3λ
R10] Poly contact size 2λ
R11] Minimum poly contact spacing 2λ
R12] Minimum poly contact to poly edge spacing 1λ
Contact R13] Minimum poly contact to metal edge spacing 1λ
R14] Minimum poly contact to active edge spacing 3λ
R15] Active contact size 2λ
2λ
 R16] Minimum active contact spacing (on the same
active region) 1λ
R17] Minimum active contact to active edge spacing 1λ
R18] Minimum active contact to metal edge spacing 3λ
R19] Minimum active contact to poly edge spacing 6λ
R20] Minimum active contact spacing (on different
active regions)

12.Draw stick diagram and Layout of CMOS inverter

Module 2:
1. Draw and explain working of resistive load inverter
2. Explain working of CMOS inverter with labelled VTC characteristics
3. What is noise margin? What is VIL/VIH for CMOS inverter
4. Derive threshold voltage (Vth) for CMOS inverter. What is condition for symmetric CMOS inverter?
5. Find VIL, VIH, Vth and noise margin for following: