Combinational Circuit Design

and Simulation Using Gates

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 Design steps
• Set up a truth table which specifies the output(s) as a function of the input
variables – (problem analysis)
• Derive the algebraic expressions for the output functions – (Modeling)
• Simplify algebraic expressions functions using Karnaugh maps, the Quine-
McCluskey method, or a similar procedure. – (Optimization)
• Map the logic functions in the algebraic equation to logic gates and realize
the logic circuit –(Implementation)

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 Design steps
• Simulation and Verification
• Prototyping :- building the circuit –physical implementation
• Technology Mapping
• Circuit transformation

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 Implementation
• Minimum two-level AND-OR, NAND-NAND, OR-NAND, and NOR-OR
circuits can be realized using the minimum sum of products as a starting
point
• Minimum two-level OR-AND, NOR-NOR, AND-NOR, and NAND-AND
circuits can be realized using the minimum product of sums as a starting
point
• In practical logic design problems, the maximum number of inputs on each
gate (or the fan-in) is limited  multi-level realization
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 Implementation
• Propagation delay needs to be considered: the propagation delay for a 0 to 1
output change may be different than the delay for a 1 to 0 change

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 Simulation and Testing of Logic Circuits
• Logic circuits may be tested either by actually building them or by simulating
them on a computer

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 Basic Combinational Logic Circuits
• AND-OR Logic: X=AB +CD

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 Basic Combinational Logic Circuits
• AND-OR-Invert Logic

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 Basic Combinational Logic Circuits
• Exclusive-OR Logic

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 Basic Combinational Logic Circuits
• Exclusive-NOR Logic:

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 Implementing Combinational Logic
• From a Boolean Expression to a Logic Circuit

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 Implementing Combinational Logic
• From a Boolean Expression to a Logic Circuit

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• From a Truth Table to a Logic Circuit

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The NAND Gate as a Universal Logic Element

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The NOR Gate as a Universal Logic Element

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 The Half-Adder
• The half-adder accepts two binary digits on its inputs and produces two binary
digits on its outputs—a sum bit and a carry bit

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The Half-Adder

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 The Half-Adder
• NAND implementation methods • 𝑌 = 𝐴 𝐴. 𝐵 + 𝐵 𝐴. 𝐵
• Boolean equivalence:
• 𝑌 = 𝐴(𝐴. 𝐵) . 𝐵(𝐴. 𝐵)
• ҧ
𝑌 = 𝐴𝐵ത + 𝐴𝐵
• 𝑌 = 𝐴𝐵ത + 𝐴𝐵 ҧ +0+0
• 𝑌 = 𝐴𝐵ത + 𝐴𝐵ҧ + 𝐴𝐴ҧ + 𝐵𝐵
ത
• 𝑌 = 𝐴 𝐴ҧ + 𝐵ത + 𝐵 𝐴ҧ + 𝐵ത
• 𝑌 = 𝐴 𝐴. 𝐵 + 𝐵 𝐴. 𝐵
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The Half-Adder

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 The Full-Adder
• The full-adder accepts two input bits and an input carry and generates a sum
output and an output carry

𝐶𝑜𝑢𝑡 = 𝐴𝐵 + 𝐶(𝐴 + 𝐵)

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The Full-Adder

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The Full-Adder

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The Full-Adder

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The Full-Adder

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2-bit parallel adder

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Four-Bit Parallel Adders

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Adder Expansion

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Controlled Inverter

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Adder–Subtractor

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 Comparators
• Equality: the exclusive-NOR gate can be used as a basic comparator

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Comparators

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Two-bit magnitude comparator

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 Decoders
• A decoder is a digital circuit that detects the presence of a specified
combination of bits (code) on its inputs
• An n input lines to handle n bits and from one to 2n output lines

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 The Basic Binary Decoder
• determine when a binary 1001 occurs

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3-to-8 (1 of 8) line decoder

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3-to-8 (1 of 8) line decoder

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Cascading Decoder Circuits

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 Encoders
• The process of converting from familiar symbols or numbers to a coded
format is called encoding
• An encoder essentially performs a “reverse” decoder function

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Decimal-to-BCD Encoder

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 Decimal-to-BCD Priority Encoder
• A priority encoder also offers additional flexibility
• the encoder will produce a BCD output corresponding to the highest-order
decimal digit input that is active and will ignore any other lower-order active
inputs

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 An Application
• Numeric keypad

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 Multiplexers (Data Selectors)
• A multiplexer (MUX) is a device that allows digital information from
several sources to be routed onto a single line for transmission over that line
to a common destination
• The basic multiplexer has:
• several data-input lines
• a single output line.
• data-select inputs
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2-to-1 MUX

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A 4-to-1 multiplexer

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A 8-to-1 multiplexer

Commercially available as 74150

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 Half Adder Using 2:1 Multiplexers
A B Co S A 0

2:1
0 0 0 0 B 1
0
0 1 0 1

2:1
S
0 1
1 0 0 1
B 1
1 1 1 0 Co

2:1
A 0

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 Nibble multiplexer

Commercially available
as 74157
Check the datasheets 49
 Demultiplexers
• A demultiplexer is a combinational logic circuit with an input line, 2n output
lines and n select lines
• It routes the information present on the input line to any of the output lines

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1-to-4 lines Demultiplexer

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1-to-8 lines Demultiplexer

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Seven-segment display decoder

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 Seven-segment display decoder

A =0, 1, 2, 5, 7, 8, 9
B = 0, 1, 2, 4, 7, 8, 9
.
.
.
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Binary-to-Gray and Gray-to-Binary Convertor

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 Majority function
• The majority function M(x, y, z) is equal to 1 when two or three of its
arguments equal 1.

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 Minority function
• The minority function m(x, y, z) is equal to 1 when two or three of its arguments
equal 0.

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