<br>

Page l of 440

SYLLABUS
ANNAUNIVERSITY, CHENNAI
EMBEDDED SYSTEMS AND IoT DESIGN

g
UNIT I 8051 MICROCONTROLLER [CHAPTERS 1,2, 3J 9

in
Microontröllers for an Embedded System 8051 - Architecture - Addressing Modes

er
-
Instruction Set Program and Data Memory - Stacks - Interrupts - Timers/Counters -
-

e
Serial Ports Programming.

in
UNIT II
EMBEDDED SYSTEMS [CHAPTERS 4, 5, 61 9

ng
Embedded System Design Process Model Train Controller ARM Processor
-
Instruction Set Preliminarics CPU – Programming Input and Output - Supervisor Mode
fE -
Exceptions and Trap -
Models for programs Assembly, Linking and Loading
- Program Level Performance Analysis.
O
Compilation Techniques

PROCESSES AND OPERATING SYSTEMS [CHAPTERS - 7,8, 9] 9

e

UNIT II
Structure ofa real- time system - Task Assignment and Scheduling - Multiple Tasks and
g
le

Multiple Processes - Multirate Systems -

Pre emptive real -
time Operating systems
-
ol

Priority based scheduling - Interprocess Communication Mechanisms Distributed

- - -
C

Embedded Systems MPSoCs and Shared Memory Multiprocessors Design Exanple

Audio Player, Engine Control Unit and Video Accelerator.
u

-
ad

UNIT IV IOT ARCHITÉCTURE AND PROTOCOLS [CHAPTERS 10,11j 9

- -
Internet - of Things - Physical Design, Logical Design loT Enabling Technologies
-
iln

Domain Specific loTs - IoT and M2M

- loT System Management with NETCONF -
- - Domuin Model -
m

–
YANG – IoT Platform Design Methodology IoT Reference Model
-
loT Reference Architecture loT Protocols MQTT,
XMPP,
Ta

Communication Model
Modbus, CANBUS and BACNet.

UNIT V IOT SYSTEM DESIGN

[CHAPTERS -12] 9

Basic building blocks of an loT device

- Raspberry Pi - Board - Linux on Raspberry Pi -
Interfaces - Programming with Python - Case Studies: Home Automation, Suart Cities,
Environment andAgriculture.
TOTAL: 45 PERIODS
<br>

Page 2 of 440

CONTENTS
UNIT -I

g
Chapter 1

in
8051 MICROCONTROLLER

er
1.1-1.35
INTRODUCTION...

e
1.1 1.1

in
1.1.1 8051 Microcontrollers Fanily 1.2

ng
1.1.2 Comparison of Microcontroller with Microprocessor... 1.4
1.1.3 8051 Microcontroller Pin Diagram and Pin Descriptions 1.5
1.2
fE
MICROCONTROLLERS FOR AN EMBEDDED SYSTEM... 1.8
O
1.2.1 Applications of Embedded Products Using Microcontrollers.... 1.9
1.3 8051 ARCHITECTURE. 1.10
g e

1.3.1 Introduction. 1.10

.. 1.11
le

1.3.2 Functional Blocks

ol

1.4 INSIDE THE 8051 1.13

C

1.4.1 Registers... 1.13

Program Status Word (PSW) Register.
u

1.4.2 1.14
ad

1.5 ADDRESSING MODES 1.16

1.5.1 Introduction. 1.16
iln

1.5.2 Types of Addressing modes 1.17

m

1.6 SOLVED EXAMPLES... 1.23

Ta

1.7 TWO MARKS QUESTIONS AND ANSWERS. 1.26

1.8 REVIEW QUESTIONS. 1.34:

Chapter2
8051 INSTRUCTION SET..... ..2.1-2.56
2.1 INSTRUCTION SET OF 8051.. 2.1
2.1
2.1.1 Introduction.
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C.2 Embedded Systems and loT Design

2.2 DATATRANSFER INSTRUCTIONS 2.2

2.2.1 MOV Instructions: MOV dest-bye, source-byte.. 2.2
2.2.2 Instructions to Access External ROMProgram Memory.. .8

2.2.3 Instructions to Access External Data Memory... 2.10

2.2.4 Data Transfer with Stack (PUSH and POP) Instructions .2.11

g
2.2.5 Data Exchange Instructions 2.12

in
ARITHMETIC INSTRUCTIONS. 2.13

er
2.3
2.3.1 ADD A, Ssource byte. -2.14

e
in
2.3.2 ADDC A, source byte 2.15

ng
2.3.3 SUBB A, source byte. 2.17

2.3.4 INC byte. fE 2.19

2.3.5 DEC byte 2.20

O
2.3.6 INC DPTR. 2.21
e

2.3.7 MULAB.... 2.22

g

2.3.8 DIV AB 2.22

le

2.3.9 Decimal Arithmetic: DA A... 2.23

ol

2.4 LOGICAL INSTRUCTIONS (OR) BIT LEVEL LOGICAL

C

INSTRUCTIONS 2.24
u

2.4.1 ANL dest-byte, source-byte. 2.24

ad

ORL dest-byte, source-byte 2.27

2.4.2
2.30
iln

2.4.3 XRL dest-byte, source-byte.

2.32
m

2.4.4 CLR...
2.33
Ta

-2.4.5 CPL.
2.34
2.4.6 Rotate and Swap Instructions
.. 2.38
2.5 BIT- ORIENTED INSTRUCTIONS
2.38
2.5.1 CLR Bit
2.38
2.5.2 SETB bit...
2.39
ANL C, - bit...
2.5.3 Source
*.. 2.39
2.5.4 ORL C, source-bit.... 2.40
2.5.5 MOVdest-bit, source-bi..
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Contents |C3

2.6 BRANCH INSTRUCTIONS (OR) JUMP AND CALL INSTRUCTIONS (OR)

PROGRAM AND MACHINE CONTROL INSTRUCTIONS (OR) PROGRAM
BRANCHING INSTRUCTIONS... 2.41
2.6.1 CALL Instructions 2.41

2.6.2 RETURN Instruction. 2.42

g
2.6.3 JUMP Instructions 2.43

in
2.7 TWO MARKS QUESTIONS AND ANSWERS. 2.49

er
2.8 REVIEW QUESTIONS.... 2.56

e
in
ng
Chapter 3
fE ....
PROGRAM AND DATA MEMORY 3.1-3.44
PROGRAM AND DATAMEMORY: 8051 MICROCONTROLLER
O
3.1
EXTERNAL MEMORIES... 3.1
MEMORY ORGANIZATION:INTERNAL AND
e

2 3.1
3.1.1 Introduction...
g

Microcontroller.. 3.2
2 3.1.2 Program Memory (ROM) of 8051
le

3.3
3 3.1.3 Data Memory (RAM).
ol

Microcontroller.. 3.6
3.1.4 Interfacing External Memory with 8051
C

4 3.7
3.2 STACKS.
3.7
u

24 Introduction
3.2.1
3.8
ad

27:
3.2.2 PUSH and POP Operation:
3.9
30 3.2.3 Other Instructions.
iln

INTERRUPTS IN 8051
32 3.3 8051 INTERRUPTS (OR)
.... 3.9
m

MICROCONTROLLER
33 3.9
Introduction..
Ta

3.3.1
.34 3.10
3.3.2 Interrupt Service Routine (1SR)...
.3.11
.38 Steps in Executing,an
Interrupt.
3.3.3 3.12
!.38 Vèctored Interrupts.
3.3.4 Six Interrupts in the 8051: .
3.13
2.38 an Interrupt...
3.3.5 Enabling and Disabling 3.14
2.39 8051/52.
3.3.6 Interrupt Priority in the
3.15
2.39 3.4 PROGRAMMIG 8051 TIMERS: TIMERS
2.40
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CA| Embedded Systems and loT Design

3.4.1 Introduction. 3.15

Structure of TMOD (Timer Mode) Register
..,.. 3.16
3.4.2
3.4.3 TCON (Timer/Counter) Register 3.18

3.4.4 Mode 0: 13-bit Timer Mode 3.19

Mode 1 Programming. 3.19
3.4.5

g
Mode 2 Programming. 3.21
3.4.6

in
COUNTER PROGRAMMING 3.22

er
3.5
3.5.1 CIT bit in TMOD Register. 3.22

e
TCON Register: Timer/ Counter Control Register... 3.25

in
3.5.2
GATE = 1 in
TMOD.. 3.27

ng
3.5.3
3.6 8051 SERIAL PORT PROGRAMMING. 3.28
3.6.1 8051 Connection to RS232
fE 3.28
Baud Rate in 8051 3.29
O
3.6.2
3.6.3 SBUF Register.. 3.30
e

3.6.4 SCON (Serial Control) Register. 3.30

g

Programming the 8085 to Transfer Data Serially..

le

3.6.5 3.33
ol

3.6.6 Programming the 8051 to Receive Data Serially: 3.34

C

3.6.7 Doubling the Baud Rate in the 8051 3.34

3.7 SOLVED EXAMPLES. 3.36
u
ad

3.8 TWO MARKS QUESTIONS AND ANSWERS. 3.39

3.9 REVIEW QUESTIONS.. 3.43
iln
m

UNIT -II
Ta

Chapter 4
EMBEDDED COMPUTING ,4.1-4.34
4.1 EMBEDDED SYSTEM DESIGN PROCESS 4.1
4.1.1 Introduction... 4.1
4.1.2 Steps. .4.2
4.1.3 Requirements 4.3
4.1.4 Specification 4.7
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Contents
C.5
4.1.5 Architecture Design
4.7
4.1.6 Designing Hardware and Software Components.
4.9
4.1.7 System Integration...
4.9
4.1.8 Fomalisms for System Design
4.10
4.1.9 Structural Description ..
4.10

g
4.1.10 Behavioral Description

in
4.15
4.2 DESIGN EXAMPLE: MODEL TRAIN CONTROLLER ....

er
4.18
4.2.1 Introduction..

e
4.18
4.2.2 Requirements.

in
4.20
4.2.3 Digital Command Control (DCC)....

ng
4.20
4.2.4 Conceptual Specification. 4.22
4.2.5 Detailed Specification
fE 4.25
4.3 TWO MARKS QUESTIONS AND ANSWERs.
O
4.31
4.4 REVIEW QUESTIONS.
4.33
g e

Chapter5
le
ol

ARM INSTRUCTION SETS... ...5.1-5.33

C

5.1 ARM PROCESSOR 5.1

u

5.1.1 Introduction. 5.1

ad

5.1.2 Processor and Memory Organization... 5.2

iln

5.1.2 Data Operations 5.2

5.1:3 Flow of Control 5.12
m

5.1.4 Advanced ARM Features 5.16

Ta

5.2 PRELIMINARIES 5.17

5.2.1 Computer Architecture Taxonomy. 5.17
5.2.2 Assembly Languages. 5.21
5.2.3 VLIW ProcessorS 5.23
5.3 TWO MARKS QUESTIONS AND ANSWERS. 5.26
5.4 REVIEW QUESTIONS.... 5.33
<br>

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C.6| Embedded Systems and loTDesign

Chapter 6
CPUS 6.1-6.41
6.1 PROGRAMMING INPUT AND OUTPUT 6.1
6.1.1 Input and Output Devices... ...
6.1

g
Input and Output Primitives

in
6.1.2 6.2
Busy-Wait /O.

er
6.1.3 6.2
6.1.4 Interrupts.... 6.3

e
in
6.2 SUPERVISOR MODE. 6.8

ng
6.2.1 ARM Operating Modes.
6.8
6.3 EXCEPTIONS 6.9
6.3.1 Introduction..
fE 6.9
6.3.2 Exceptions and Modes.
O
6.10
6.4. TRAPS 6.11
e

6.5 MODELS OF PROGRAMS....

..
g

6.11
le

6.5.1 Introduction ..6.11

ol

6.5.2 Data Flow Graphs (DFGs)..

6.12
C

6.5.3 Control /Data Flow Graphs (CDFG)

6.13
6.6 ASSEMBLY, LINKING AND LOADING.
u

6.15
ad

6.6.1 Introduction.
6.15
6.6.2 Assemblers.
6.18
iln

6.6.3 Linking
6.19
m

6.6.4 Object Code Design... 6.21

Ta

6.7 COMPILATION TECHNIQUES

6.22
6.7.1 The Compilation Process 6.22
6.7.2 Basic Compilation Methods. 6.23
6.7.3 Compiler Optimizations. 6.25
6.8 PROGRAM-LEVEL PERFORMANCE ANALYSIS. 6.29
6.8.1 Introduction ... 6.29
6.8.2 Measuring Execution Speed.. 6.30
6.8.3 Elements of Program Performance 6.30
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of 440

C'ontents C.7
6.8.4 Measurement-Driven Performance Analysis... 6.31
6.9 TWO MARKS QUESTIONS AND ANSWERS.
6.33
6.10 REVIEW QUESTIONS. ...
6.41

UNIT - II

g
in
er
Chapter 7

e
PROCESSES AND OPERATING SYSTEMS.... 7.1-7.26

in
ng
7.1 STRUCTURE OFAREAL-TIME SYSTEM. 7.1
7.1.1 Introduction. 7.1
7.1.2 Structure of Embedded System
fE 7.2
O
7.1.3 Structure of Embedded Real-time System.. 7.3
7.2 TASK ASSIGNMENT AND SCHEDULING 7.5
e

Introduction ..
g

7.2.1 .7.5
le

7.2.2 Task Assignment.. 7.5

ol

7.2.3 Scheduling.. 7.6

C

7.2.4 Classifications of Task Scheduling Algorithms: 7.7

u

7.2.5 Advantages... 7.8

ad

7.3 MULTIPLE TASKS AND MULTIPLE PROCESSES 7.9

iln

7.3.1 Introduction.. 7.9

m

7.3.2 Tasks and Processes 7.9

Ta

7.4 MULTIRATE SYSTEMS 7.11

7.4.1 Introduction. ....7.11

7.4.2 Timing Requirements on Processes 7.12
7.4.3 CPU Usage Metrics. 7.15
7.4.4 Process State and Scheduling 7.15
7.4.5 Running Periodic Processes 7.16
7.5 PREEMPTIVE REAL-TIME OPERATING SYSTEMS 7.18

7.5.1 Introduction... 7.18

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C.8| Embedded Systems and loT Design

7.5.2 Two Basic Concepts. 7.18

7.5.3 Processes and Context 7.19
7.5.4 Processes and Object-Oriented Design: UMI Active Objects .....7.20
7.6 TWO MARKS QUESTIONS AND ANSWERS. 7.21
7.7 REVIEW QUESTIONS... 7.25

g
in
er
Chapter 8

e
in
NETWORKS AND MULTIPROCESSORS ...8.1-8.32

ng
8.1 PRIORITY-BASED SCHEDULING 8.1
8.1.1 Introduction... fE 8.1
8.1.2 Rate-Monotonic Scheduling (RMS).. 8.2
O
8.1.3 Earliest-Deadline-First (EDF) Scheduling 8.5
8.1.4 Shared Resources. 8.6
g e

8.1.5 Priority Inversion... 8.8

le

8.2 INTERPROCESS COMMUNICATION MECHANISMS 8.8

ol

8.2.1 Introduction. 8.8

C

8.2.2 Shared Memory Communication... 8.8

u

8.2.3 Message Passing 8.9

ad

8.2.4 Signals. 8.10

8.2.5 Mailboxes. .8.11
iln

8.3 DISTRIBUTED EMBEDDED SYSTEMS: NETWORKS FOR loT ...... 8.11

m

..... .8.11
8.3.1 Introduction.
Ta

8.3.2 Network Abstractions: The OSI Model. 8.12

8.3.3 CAN Bus. 8.14
8.3.4 Distributed Computing in Cars and Airplanes 8:17
8.3.5 PC Bus. 8.18

8.3.6 Ethernet. 8.21

8.3.7 Internet Protocol ((P) ... 8.23

TWO MARKS QUESTIONS AND ANSWERS. 8.27

8.4
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Contents C.9
8.5 REVIEW QUESTIONS.
8.32

Chapter9
MPSOCs AND SHARED MEMORY MULTIPROCESSORS...9.1-9.28

g
MPSoCs AND SHARED MEMORY MULTIPROCESSORS
9.1
.. 9.1

in
9.1.1 Introduction 9.1

er
9.1.2 Heterogeneous Shared Memory Multiprocessors. 9.2

e
9.1.3 Accelerators. 9.2

in
9.1.4 Accelerator Performance Analysis : .... 9,4
Scheduling and Allocation ...

ng
9.1.5 9.7
9.2 DESIGN EXAMPLE: AUDIO PLAYER fE 9.8
9.2.1 Theory of Operation and Requirements... 9.8
O
9.2.2 Specification .9.11
...
9.2.3 System Architecture.
e

9.12
g

9.2.4 Component Design and Testing 9.13

le

9.2.5 System Integration and Debugging. 9.14

ol

9.3 ENGINE CONTROL UNIT (ECU).... 9.14

C

...
9.3.1 Theory of Operation and Requirements. 9.14
u

9.3.2 Specification 9.15

ad

9.3.3 System Architecture. 9.16

Component Design and Testing..
iln

9.3.4 9.18
9.3.5 System Integration and Testing. 9.18
m

9.4 VIDEO ACCELERATOR 9.19

Ta

9.4.1 Video Compression 9.19

9.4.2 Requirements 9.22

9.4.3 Specification 9.22

9.4.4 Architecture 9.23

9.5 TWO MARKS QUESTIONS AND ANSWERS. 9.25

9.6 REVIEW QUESTIONS... 9.28

<br>

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C.10| Embedded Systems and loT Design:

UNIT - IV
Chapter 10
INTERNET OF THINGS (IoTs) 10.1-10.37

g
10.1 INTRODUCTION. 10.1

in
10,1.1 Applications 10.1

er
10.1.2 Definition and Characteristics of loT
10.3

e
10.2 PHYSICAL DESIGN OF IloT. 10.4

in
10.2.1 Things in loT. 10.4

ng
10.2.2 loT Protocols.. 10.5
10.3 LOGICAL DESIGN OF loT. fE 10.11
10.3.1 loT Functional Blocks 10.11
O
10.3.2 loT Communication Models.
10.12
e

10.3.3 loT Communication APls. 10.14

g

10.4 loT ENABLING TECHNOLOGIES 10.18

le

10.4.1 Wireless Sensor Networks (WSNs) 10.18

ol

10.4.2 Cloud Computing.

10.19
C

10.4.3 Big Data Analytics...

10.21
u

10.4.4 Communication Protocols

10.22
ad

10.4.5 Embedded System..

10.22
10.5 DOMAIN SPECIFIC loTs...
iln

10.22
10.5:1 Introduction ....
10.22
m

10.5.2 Home Automation ...

10.23
Ta

10.5.3 Smart Cities.

10.25
10.5.4 Environment
10.27
10.5.6 Energy ...
10.28
10.5.7 Retail.
10.30
10.5.8 Logistics...
10.31
.10.5.9 Agriculture.
10.32
10.5.10 Industry
10.32
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Contents
C.l1
10.5.11 Health &Lifestyle...
10.33
10.6 TWO MARKS QUESTIONS AND ANSWERS.
10.33
10.7 REVIEW QUESTIONS.
10.37

Chapter 11

g
.. 11.1- 11.40

in
MACHINE -TO- MACHINE (M2M)

er
11.1 loT AND M2M
Introduction..
11.1

e
11.1.1

in
11.1
11.1.2 M2M Architecture.

ng
.11.1
.
11.1.3 Difference between loT and M2M.. 11.3
11.1.4 SDN and NFV for loT
fE 11.4
O
11.2 loT SYSTEM MANAGEMeNT WITH NETCONF-YANG 11.9
11.2.1 Need for loT Systems Management 11.9
g e

11.2.2 Network Configuration Protocol (NETCONF) 11.10

le

11.2.3 Yet Another Next Generation (YANG) 11.13

ol

11.2.4 loT Systens Managements with NETCONF-YANG 11.15

C

11.3 loT PLATFORMS DESIGN METHODOLOGY..... 11.17

..
u

11.4 loT REFERENCE ARCHITECTURE AND REFERENCE MODEL 11.20

ad

11.4.1 Introduction. 11.20

loT Reference Architecture...
iln

11.4.2 11.21
11.4.3 loTReference Model: Domain Model 11.25
m

11.4.4 Communication Mödels in loT. 11.28

Ta

11.5 loT PROTOCOLS. 11.28

11.5.1 MQTT 11.28
11.5.2 XMPP. 11.30
11.5.3 MODBUS 11.32
11.5.4 CANBUS with BACNet. 11.33
11.6 TWO MARKSQUESTIONS AND ANSWERS. 11.34
11.7 REVIEWN QUESTIONS... 11.39
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C.12 Embedded Systems and loT Design

UNIT -V

CHAPTER 12
IoT PHYSICAL DEVICES. 12.1-12.11
DEVICE. 12.1
BASIC BUILDING BLOCKS OF AN loT

g
12.1

in
Pi. 12.3
12.2 RASPBERRY

er
12.3
12.3 RASPBERRY PiBOARD

e
12.5
12.4 LINUX ON RASPBERRY Pi....

in
12.5
12.4.1 Introduction.

ng
12.5
12.4.2 Installation...
12.7
12.5 RASPBERRY Pi INTERFACES fE 12.9
12.6 PROGRAMMING RASPBERRY Pi WITH PYTHON
O
12.9
12.6.1 Controlling LED with Raspberry Pi....
12.10
e

12.7 CASE STUDIES.

.... 12.10
g

12.7.1 Home Automation

le

12.10
12.7.2 Smart Cities.
ol

12.10
12.7.3 Environment
C

12.10
12.7.4 Agriculture.
12.10
u

TWO MARKS QUESTIONS AND

ANSWERS.
12.8
ad

12.11
12.9 REVIEW QUESTIONS..
iln

Model Anna University Question Papers

m
Ta
<br>

Page 14 of 440

UNIT-I
Chapter 1

g
in
8051 MICROCONTROLLER

e er
in
1.1 INTRODUCTION

ng
A Microprocessor:
The microprocessor is fE
general purpose digital computer central processing
a

unit. They can address megabytes of memory and operates on 8, 16, or

32 bit
O
data. It consists of an ALU, accumulator, working registers, program counter,
stack pointer, clock and interrupt circuits.
g e
le

Arithmetic
Working
Accumulator and logic
registers(s)
ol

unit
C
u
ad
iln
m

Stack Interrupt
Ta

Timing and pointer circuit

clock circuits

Program
counter

Fig 1.1General architecture of a

microprocessor
Fig 1.1 shows the general architecture of a microprocessor. The microprocessor
alone is not a conplete digital computer. In order to make it, one should add
memory devices and I/O devices.
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1.2 Embedded Systems and 10T Design

In addition,special purpose devices, such as interrupt controller, programmable
timers, programmable IO devices, DMA controllers may be added to inprove
is capability, performance as well as flexibility of a microcomputer system. In
order to overcome these drawbacks in microprocessor, the microcontrollers were
developed.

g
in
1.1.1 8051 Microcontrollers Family

er
a Definition:

e
in
The microcontroller incorporates all the features that are found in

ng
microprocessor, but they are designed to work as a true single-chip system
that is, it can integrate all the devices needed for a system on a single-chip
fE
which is optimized for specific applications.
O
The basic functional units of a microprocessor will be ALU,set of
registers,
timing and control unit. The microcontroller will have these functional
e

blocks and in addition it may have VO ports, a programmable timer, RAM

g
le

and EPROM/EEPROM.
ol

Some microcontrollers may even have internal ADC and DAC.

C

The first 8 bit microcontroller called 8048 was introduced by Intel in 1976 which
u

control general tasks. The 8051 is the original member of the 8051 family. Intel
ad

refers to it as MCS-51.
The 805l was designed for 8-bit nathematical and single bit Boolean
iln

operations. These families provide separate program and data nmemory which
m

may be internal or external.

Ta

s Features of 8051 Microcontroller:

The features of 8051 microcontrollers are as follows:
4K bytes on-chip program memory (ROM).
128 bytes on-chip data memory (RAM).
- Four register banks.
128 user defined sofiware flags.
8-bit bidirectional data bus.
<br>

Page 16 of 440

8051 Microcontroller
1.3|
16-bit unidirectional address bus.
- 32 bidirectional VO lines organized as
four 8-bit ports.
16 bit timners (usually 2, but may have more or less).
16-bit program counter and data pointer.
Interrupt structure with two priority levels.

g
in
- On chip oscillator and clock circuits.

er
Full duplex serial data transmitter/receiver.
Direct bit and byte addressability.

e
in
Binary or decimal arithmetic.

ng
Signed-overflow detection and parity computation.

Feature
ROM
fE Quality
4K bytes
O
RAM 128 bytes
Timer 2
e

I/O pins 32
g

Serial port
le

Interrupt sources 6
ol

Table 1.lFeatures of the 8051

C

The other two members in the 8051 family of microcontrollers are 8052 and
u

8031.
ad

Feature 8051 8052 8031

ROM (bytes) 4K 8K OK
iln

RAM (bytes) 128 256 128

m

Timers 2 3
Ta

I/O pins 32 32 32
Serial port 1 1

Interrupt sources 6 8 6

Table 1.2 Comparison of 8051 family menmbers

M Advantages

The advantages of microcontroller are,

() The built-in peripherals have small access tme and the speed is more.
<br>

Page 17 of 440

1.4 Embedded Systems and 10T Design

(ti) Reduced hardware due to single chip microcomputer system.

(ii) Less hardware that reduces PCB size and increases reliability of the system.
(iv) Low system cost.

1.1.2 Comparison of Microcontroller with Microprocessor

g
in
Sr.NO Microprocessor Microcontroller

er
1. The functional blocks of a The microcontroller includes the
microprocessor are the ALU, functional blocks of a

e
in
registers, timing and control unit. microprocessor and in addition has
a memory, I/O interfacing circuit

ng
and peripheral devices such as
fE ADC, DAC, timer etc.
2. It has several instructions to move It has one or two instructions to
O
data between memory and CPU. move data between memory and
CPU.
e

The microprocessors are used for Microcontrollers are used for

g

3.
designing general purpose digital
le

designing application specific

computing system (or computers). dedicated systems
ol

4. It has one or two bit handling It has many bit handling

C

instructions. instructions.
u

5. Memory and I/O devices access Less access time for built-in
ad

time is more. memory and I/O devices.

It requires more hardware.
iln

6. Itrequires less hardware that

reduces the PCB size and increases
m

the
reliability.
Ta

7. More flexible in design. Less flexible in design.

8. It has different ICs for memory and It has in-built memory and I/Os.
I/Os.
9. It has single memory map for data It has a separate memory map for
and code. data and code.
10. Less number of pins are More number pins are
multifunctioned. mulifunctioned.
<br>

Page 18 of 440

8051 Microcontroller
| 1.5|
1.1.3 8051 Microcontroller Pin Diagram and Pin Descriptions
The S0S1 miccontroller is a popular 8-bit microcontroller
widely used in
cmbeddcd systems. It has a 40-pin Dual In-line Package
(DIP) that provides
various inputs and outputs for communication with external devices.

g
in
(P1,0 1

er
40
P1.1 C2 PO.0 (AD0)
39

e
P1.2 3 P0.1 (AD1)

in
38

Port 1
P1.3 4 37 P0.2 (AD2)

ng
P1.4 5 36 P0.3 (AD3)
P1.5
P1.6
6 fE 35 PO.4 (AD4) Port 0
7 34 PO.5 (AD5)
O
P1.7 C8 33 P0.6 (AD6)
RST
e

32 PO.7 (AD7)
8051
g

(RXD) P3.0 10 31 EAVpP

MC
le

(TXD) P3.1 11
30 ALE/PROG
ol

(INTO) P3.2 12 29 D PSEN

C

(INT1) P3.3 13 28 P2.7 (A15)

Port 3
(T0) P3.4 14 27 P2.6 (A14)
u
ad

(T1) P3.5 15 26 O P2.5 (A13)

(WR) P3.6 16 25 P2.4 (A12)
iln

(RD) P3.7 17 24 O P2.3 (A11) Port 2

m

XTAL2 O18 23 P2.2 (A10)

XTAL1 O
19 P2.1 (A9)
Ta

22
GND 20 21 P2.0 (A8)

Fig 1.2 Pin diagram of 8051

Pin 1 to Pin
(Port- 1):
&

Pin -%is assigned to port 1

for simple I/Ooperations. These ports are work as a
bidirectional port tihat means all the pins of port work us input pius or output
1

pins.
<br>

Page 19 of 440

|1.6
Embedded Systems and 10T Design
as an
() iflogic I (one) is applied to the l/O port it will act input pin.
as an output pin.
(i) If logic 0 (zero) is applied to the l/O port it will act
Pin-9 (RST):
to its initial
It isReset pin, which is used to reset the 8051 microcontrollers
a

g
values when logic 1 is applied to this pin. It is an active-high input pin.

in
er
Pin 10 to Pin 17: Port-3
assigned to port 3 which is also a bidirectional I/O port like

e
-
Pin 10 17 are

in
port 1. This port performs some special functions like interrupts, control

ng
pins
signals, timer inpt, serial communication etc. The detail function of cach
arcgiven in 1able 1.3: fE
Pin No Symbol Use
O
10 RXD Serial data receive pin.
Serial data transmit pin.
e

11 TXD
g

12 INTO External interrupt 0 input.

le

1
External interrupt input.
ol

13 INTI
C

14 TO External timer 0 input.

External timer 1
input.
u

15 TI
ad

16 WR Extermal memory write signal.

iln

17 RD External memory read signal.

m

Table 1.3
Ta

Pin 18 and Pin 19 (XTAL2 and XTAL1):

These pins are used for interfacing external oscillator. Mostly, a quartz crystal
oscillator is connected here to get the system clock.
Pin 20 (GND):

Pin 20 is the ground pinwhich is connected to the

power supply.
v (negative terminal) ol e
<br>

Page 20 of 440

8051 Microcontroller
:
Pin 21 to Pin 28 Port 2
Pin 21 to Pin 28 are port 2 pins which is also a bidirectional
Input /0utput port
i.e., all pins of port 2 work as a input pin or as a output pins. But, this is only
possible when we are not using any external memory.

If we use external memory, then these pins will work as high order address bus

g
(A8 to Al5).

in
er
Pin 29 (PSEN)

e
PSEN stands for Program Store Enable. It is an active-low output
pin which is

in
used to read an external memory.

ng
Pin 30 (ALE/PROG)
fE
ALE stands for Address Latch Enable. It is an active-high input pin which is
O
used to distinguish between memory chips when multiple memory chips are
e

used.
g

It is also used to de-multiplex the multiplexed address and data signals available
le

at port 0.
ol
C

Pin 31 (EAVpp)
u

It is the External Access (EA) enable pin which allows external program
ad

memory. It is an input pin and connected from Vcc or GND.

iln

If we want to access the program from external program memory, it must be

connected with GND. If we want to use on-chip memory, it must be high
m

(connected with Vcc).

Ta

Pin 32 to Pin 39: Port 0

Pin 32 to Pin 39 are port 0 pins. When we don't use any external memory, these
pins are used as a bidirectional pin like port 2 and port 3.
When ALE or pin 30 is at 1, then this port is used as a data bus. And when the
ALE pin is at 0, then this port is used as a lower order address bus (ADO
to AD7).
<br>

Page 21 of 440

1.8 Embedded Systems and I0T Design

Pin 40 (Vcc):

This pin is used to provide (+5V) power supply to the 8051 microcontroller
circuit.

g
1.2 MICROCONTROLLERS FOR AN EMBEDDED SYSTEM

in
Embedded System:

er
An embedded system is combination of computer hardvare and sofhvare
a

e
a comnbination
designed for a specifc function. It is a computer system which is

in
memory, and input/output peripheral devices
of a computer processor, computer

ng
that has a dedicated function within a larger mechanical or electronic systen.

General
Data bus
fE
Purpose
O
Micro Serial
Processor I/O Timer
RAM ROM COM
e

Port Port
g
le

CPU
Address bus
ol
C

(a) General-purpose microprocessor system

u
ad

Microcontroller
iln

CPU RAM ROM

m

Serial
Ta

I/O Timer COM

Port

(b) Microcontrollers

Fig 1.3
Microprocessors and microcontrollers are widely used in embedded system
products.
<br>

Page 22 of 440

805) Microcontroller 1.9

An embedded product uses a microprocessor or microcontroller to
do one and
one task only. There is only one application
sofiware that is typically burned
into ROM.

Example:
Aprinter is an example of embedded system since the processor inside it

g
performs only one task: getting the data and printing.

in
4 A Pentium-based PC, in contrast with the embedded system, can be used for any

er
number of applications such as word processor, print server, bank teller

e
terminal, video game player, network server, or internet terminal. It has RAM

in
memory and an operating system that loads a variety

ng
of applications into RAM
and lets the CPUto run them.
fE
A PC contains or is connected to various embedded products. Each one
peripheral has a microcontroller inside it that performs only one task.
O
Very often the terms embedded processor and microcontroller are used
e

interchangeably. One of the most critical needs of an embedded system is to

g

decrease power consumption and space.

le
ol

In high-performance embedded processors, the trend is to integrate more

C

functions on the CPU chip and let designer decide which features he/she wants to
use.
u
ad

1.2.1 Applications of Embedded Products Using Microcontrollers

iln

() Home
m

Appliances, intercom, lelephones, security systems, garage door openers,

Ta

answering machines, fax machines, home computers, TVs, cable TV tuner, VCR,
camcorder, remote controls, video games, cellular phones, musical instruments,
sewing machines, lighting control, paging, camera, pinball machines, toys,
exercise equipment.
(ii) office
Telephones, computers, securiy systems, fax machines, microwave, copier, laser
printer, color printer, paging.
<br>

Page 23 of 440

1.10 Embedded Systems and 10T Desip

(ii) Auto
Trip computer, engine control. air bag, ABS, instrumentation, security system

transmission control, entertainment, climate control, cellular phone, keyless

entry.

g
1.3 8051 ARCHITECTURE

in
er
1.3.1 Introduction

e
8051 miicrocontroller is designed by Intel in 1981. It is an 8-bit microcontroller

in
which is built with 40 pins Dual Inline Package (DIP), 4K byte of on-chip ROM

ng
storage, 128 bytes of RAM storage, two 16-bit timers, one serial port, and four
ports all on a single chip. fE
It consists offour parallel 8-bit ports, which are programmable as well as
O
addressable as per the requirement. An on-chip crystal oscillator is integrated in
the microcontroller having a crystal frequency of 12 MHz.
g e

External
le

Interrupts
ol

INTO. INT1 On-Chip

ROM
C

for ON-CHIP
Interrupt ETC
program RAM
control TIMER O
code
u

Counter
TIMER
1J Inputs
ad
iln

System bus
CPU
m
Ta

OSC BUS 4 1/0 SERIAL

Control PORTS PORT

30 PF:
30PF TXD RXD
Address/Data

4 to 30 MHz

Fig 1.4 Architecture (or) Functional block diagram of 8051 microcontroller

<br>

Page 24 of 440

8051 Microcontroller 1.11|

& All the supporting devices are connected to the CPU by using system
bus which
consists of an 8-bit data bus, a 16-bitaddress bus and a
bus control signals.
All other devices like program memory, ports, data memory,
serial interface,
interrupt control, timers, and the CPU are all interfaced together
through the
system bus.

g
in
1.3.2 Functional Blocks

er
The basic functional blocks (or) components present internally
inside 8051

e
microcontroller architecture are as follows:

in
(0) CPU(Central Processing Unit):

ng
CPUacts as. a mind of any processing machine. It synchronizes and manages
fE
all processes that are carried out in microcontroller. User has no power to
control the functioning of CPU.
O
It interprets the program stored in ROM and carries out from storage and then
e

perförms it as a projected duty. CPU manages the different types of registers

g
le

available in 8051 microcontroller.

ol

(ii) Interrupts:
C

Interrupts is a sub-routine call that is given by the microcontroller when some

other program with high priority is requesting for acquiring the system buses,
u
ad

then interrupts occur in current running program.

Interrupts provide a method to postpone or delay the current process, to
iln

performs a sub-routine task and then restart the standard program.

m

a Types of interrupt in 8051 Microcontroller:

Ta

The five sources of interrupts in 8051 Microcontroller are,

(i) Timer 0 overflow interrupt - TFO
(ii) Timer 1 overflow interrupt - TF1
(iii) External hardware interrupt - INTO
(iv), External hardware interrupt - INTI
(v) Serial communication interrupt - RXD/TXD
<br>

Page 25 of 440

1.12| Embedded Systems and IOT Design

The timer and serial interrupts are internally produced by the microcontroler.
devices
whereas the external interrupts are produced by additional interfacing
or switches that are externally connected with the microcontroller. These
external interrupts can be level triggered or edge triggered.

(iii) Memory:

g
a program which guides the

in
For the operation of microcontroller, it requires
microcontroller to perform the specific tasks. For that, it uses a chip
mnemory

er
for the storage of the program.

e
in
Microcontroller also required meimory for storage of data and operands for

ng
the short duration. It uses code or program memory of 4 KB that is, it has
4 KB ROM and it also comprises of data memory (RAM) of 128, bytes.
fE
(iv) Bus:
O
Bus is a group of wires which uses as a communication channel to data
transfer. The different bus configuration includes 8, 16 or more cables.
e

Therefore, a bus can bear & bits, 16 bits all together.

g
le

Two types of buses are used in 8051 microcontroller:

ol

(a) Address Bus:

C

It consists of 16 bit address bus which is gencrally be used for

u

transferring the data from CPU to memory.

ad

(b) Data Bus:

iln

It consists of 8 bits data bus which is generally be used for transferring

m

the data from one peripherals to other periplherals.

Ta

(v) Oscillator:

Microcontroller is a digital circuit therefore it needs a timer for their

operation. To perform timer operation inside microcontroller it required
externally connected (or) on-chip oscillator.
Microcontroller is used inside an embedded system for managing the function
the
of devices. Therefore, 8051 uses
the two 16 bit counters and timers. For
inside
operation of this timers and counters, the oscillator is used
microcontroller.
<br>

Page 26 of 440

8051 Microcontroller
|1.13|
1.4 INSIDE THE 8051
1.4.1 Registers
# Registers are used to store information temporarily, while the information could
be a byte of data to be processed, or an address pointing to the
data to be
fetched.

g
in
In the Fig 1.5, the 8 bits ofa register are shown from MSB D7 to the LSB DO.
With an 8-bit data type, any data larger than 8 bits must be broken into 8-bit

er
chunks before it is processed.

e
in
most least

ng
significant bit significant bit

fE
D7 D6 D5 D4 D3 D2 D1 DO
O
Fig 1.5 8-bit register
e

The most widely used registers of the 8051 are A (accumulator), B, RO, R1, R2,
g
le

R3, R4, RS, R6, R7, DPTR (data pointer), and PC (program counter).
ol

A
C
u
ad

RO
iln

R1
m

R2
Ta

R3

R4

R5

R6

R7

Fig I.6 Some 8-bit Registers of

the 8051
<br>

Page 27 of 440

1.14| Embedded Systems and 10T Design

All of the above- registers are 8-bits, except DPTR and PC. The
accumulator

(register A) is used for all arithmetic and logic instructions.

a Program Counter (PC):

to the address of the next
The Program Counter (PC) is a register that points
is incremented
instruction to be executed. As each instruction is executed, the PC

g
in
to point to the address of the next instruction to be executed.

er
A Data Pointer (DTPR):

e
It is used by the 8051 to access external memory using the address indicated by

in
DPTR register which is 16 bit, it can also be accessed as wo 8-bit registers,

ng
DPH and DPL, where DPH is high byte and DPL is the low byte.

DPTR DPH
fE DPL
O
PC PC (program counter)
g e
le

Fig 1.7
ol

1,4.2 Program Status WNord (PSW) Register

C

a, The Program Status Word (PSW) register lso referred to as the flag register
which is an 8 bit register but only 6 bits are used by the 8051.
u
ad

PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 PSW.1 PSW.0

iln

CY AC FO RS1 RS0 OV P
m

Register bank Select bit 0

Ta

Register bank Select bit 1

RS1 RSO Register

Bank Register Bank Status
oo 0 Register Bank 0 is selected
1 1 1
Register Bank is selected
1
2 Register Bank 2 is selected
1 1
3 Register Bank 3 is selected
<br>

Page 28 of 440

8051 Microcontroller 1.15|

Bit Position Function

CY PSW.7 Carry flag
AC PSW.6 Auxiliary carry flag.
FO PSW.5 Available to the user for general purpose.

g
in
RS1 PSW.4 Register bank selector bit 1.

er
RS0 PSW.3 Register bank selector bit 0.

e
in
OV PSW.2 Overflow flag.

ng
PSW.1 User-definable bit.
P PSW.0 fE
Parity flag. Set/cleared by hardware each instruction
cycle to indicate an odd/even number of 1 bits in the
O
accumulator.
e

Fig 1.8Bits of
the PSW Register
g

A Flags:
le

The two unused bits are called as user-definable flags and the remaining four
ol

flags are called as conditional flags which indicate some conditions that resulted
C

after an instruction was executed.

u
ad

i) Carry(cY) Flag:
This flag is set whenever there is a carry out from the D7 bit. This flag bit is
iln

affected after an 8-bit addition or subtraction.

m

It can also be set to

l or 0 directly by an instruction such as SETBC" and
Ta

"CLR C" where "SETB C" stands for set bit carry" and "CLR C" for
"clear carry".
(i) Auxiliary Carry (AC) Flag:
If there is a carry from D3 to D4 during an ADD or SUB operation, this bit is set;
otherwise, it is cleared. This flag is used by the instructions that perform BCD
arithmetic.
<br>

Page 29 of 440

1.16| Embedded Systems and I0T D

Desiga

(iii) Parity (P) Flag:

This parity flag reflects the number of 1s in the accumulator (A) register only,
() Ifthe A register contains an odd number of ls, then P =1.
(b) IfA has even nuniber of ls, then P =0.
(iv) Overflow (ov)Flag:

g
This flag is set whenever the result of a signed number operation is too large

in
causing the high-order bit to overflow into the sign bit.

er
In general, the carry flag is used to detect the errors in unsigned arithmetic

e
operations and the overflow flag is only uscd to detect the crrors in signed

in
arithmetic operations.

ng
The PSW3 and PSW4 are designed as RS0 and RSI, respcctivcly as the bank
fE
selection bits. They arc used to selcct the bank registers of 8051. The PSW.5 and
PSW.1 bits are general-purpose status flag bits and can be used by the
O
programmer for any purpose.
g e

1.5 ADDRESSING MODES

le

1.5.1 Introduction
ol

Definition:
C

The CPUcan access data in various ways, whiclh are called addressing
u

modes.
ad

Addressing mode is a way to uddress an operand. Operand means source

data that is the data we are operating upOn. It can be a direct address o
iln

memory (or) any register names (or) any numerical duta ctc.
m

-Mode Operation Address OR

Ta

Code -| Data

ADDRESSING
MODE OPCODE OPERAND

Part - 1
Part- 2 Part-3

Machine Instructions

Fig 1.9 Instruction format

<br>

Page 30 of 440

8051 Microcontroller
1.17
Each assembly language statement is split into an
opcode and an operand. The
opcode is the instruction that is executed by the
CPUand the operand is the data
or memory location used to execute that instruction.
1.5.2 Types of Addressing modes
There are five different ways to execute the instructions.
Therefore, 8051

g
provides a total of five distinct addressing modes as follows:

in
(i) Immediate addressing mode,

er
(ii) Register direct addressing mode,

e
(ii) Direct addressing mode,

in
ng
(iv) Register indirect addressing mode, and
(v) Indexed addressing mode.
fE
The direct, register indirect and indexed addressing modes are used for accessing
O
memories.
(1) Immediate Addressing Mode
g e

In this immediate addressing mode, the source operand is a constant. When

le

an instruction is assembled, the operand comes immediately after the opcode.

ol

n these instructions, the # symbol is used for immediate data.

C

This addressing mode can be used to load information into any of the registers
u

including the DPTR register which stands for Data Pointer and it points the
ad

external data memory location.

iln

Examples
i) MOV A, # 55H ;load 55H into A[move the data 55 H (that is
m

in hex) immediately to register A].

Ta

R4, #
62 ;
(ii) MOV load the decimal value 62 into register R4.
We can also use immediate addressing mode to send data to 8051 ports.
Example: MOV P1, # 55H
(2) Register Addressing Mode
In the register addressing mode, the data to be operated is available inside
the register(s). We use the register name directly as source operand. Therefore
<br>

Page 31 of 440

Embedded Systems and 10T Design

1.18
various registers of the
the operation is performed within the

microprocessor.
Destination register Source register

g
in
Examples

er
MOV A, RO ; copy the contents of R0 into A.

e
in
; copy the contents of A
into R2.
MV R2, A

ng
of R5 to contents
A.
; add the contents of
ADD A, R5

ADD A, R7 add the contents of R7 to contents

.; fE of A.

MV R6, A ;save accumulator in R6.

O

(3) Direct Addressing Mode

e

an
location (source data) is given as
g

In this type, the address of the data

internal RAM and Special Function
le

operand. This operation is only for

8-bit.
ol

because it provides an address ofonly

Registers (SFRs)
C

The RAM has been assigned

addresses from 00 to 7FH.
u

Memory
ad
iln

Destination register
Address of memory
m

within the instruction

Data from
Ta

selected memory
location

Examples
A.
MOV A, 25H ; data from 25H location is given to register
an address.
Here # is not used, because it is
MOV 3OH, A move A register data to 30H location.
<br>

Page 32 of 440

8051 Microcontroller
1.19|
(1) SFR Registers and their Addresses

a Definition
A Special Function Register
(or Special Purpose Registers) are the special
registers_ closely tied to some special function or
status ofthe processor, they
might not be directly writable by normal
instructions (like add, move, etc.).

g
Instead, some special registers in some processor
architectures require

in
special instructions to modify
the.

er
This SFRs are located immediately above the 128
bytes of RAM and

e
responsible for the operation of ALU, timer, serial port, parallel ports

in
and
interrupt control.

ng
Some SFRs available in 8051 are:

(a) Accumulator (A).

fE
O
(b) B Register.
e

() Program Status Word (PS).

g

(d) DPTR
le

(data pointer).
ol

(e) Stack Pointer.

C

) Interrupt Priority Control Register.

u

The SFR can be accessed by their names or by their addresses which is much
ad

easier.
iln

Examples:
RegisterA has address EOH, and register B has address FOH.
m
Ta

MOV OEOH, #55H ;is the same as

A, #55H
; 1which means load 55H intoA (4 = S5H)
MOY

MOV OFOH, #25H : is the same as

B, #25H ; which means load 25H into B (B = 25H)
MOV
<br>

Page 33 of 440

|1.20| Embedded Systems and 10T Desig

SFR Addresses:
to These
A special function register can have an address between 8OH FFH.
to 7FH are the addresser
addresses are above 80H, as the addresses from 00
of RAM memory inside the 8051.
The unused locations of 80H to FFH are reserved and must not be used by

g
the 8051programmer.

in
Address

er
Symbol Name
OEOH

e
ACC* Accumulator

in
OFOH
B* B register

ng
PSW* Program status word ODOH

SP Stack pointer 81H

DPTR Data pointer 2 bytes
fE
O
DPL Low byte 82H
DPH High byte 83H
e

80H
g

PO* Port 0
le

P]* Port 1
90H
ol

P2* Port 2 OAOH

C

P3* Port 3 OBOH

IP* Interrupt priority control OBSH

u
ad

IE* Interrupt enable control 0ASH

TMOD Timer/counter mode control 89H
iln

TCON* Timer/counter control 88H

m

T2CON* Timer/counter 2 control 0C8H

Ta

T2MOD Timer/counter mode control 0C9H

THO Timer/counter O high byte 8CH
-TLO Timer/couhter 0 low byte 8AH
THI Timer/counter 1 high byte 8DH
TLI Timer/counter 1 low byte SBH
TH2 Timer/counter 2 high byte 0CDH
TL2 Timer/counter 2 low byte 0CCH
RCAP2H TIC2 capture register high byte 0CBH
<br>

Page 34 of 440

8051 Microcontroller
1.21

Symbol Name Address

RCAP2L T/C 2 capture register low byte 0CAH
SCON* Serial control 98H
SBUF Serial data buffer 99H
PCON Power control 87H

g
*Bit addressable

in
Table 1l.4 8051 SFR addresses

er
(ii) Stack and Direct Addressing Mode

e
Only direct addressing mode is allowed for pushing or popping the stack.

in
PUSH A is
invalid.

ng
Pushing the accumulator onto the stack must be coded as PUSH 0EOH.

(4)
fE
Register Indirect Addressing Mode:
O
In the register indirect addressing mode, a register is used as a pointer to the
e

data. If the data is inside the CPU, only registers RO and RI are used as a
g

pointers, they must bepreceded by the "@" sign.

le
ol

R2-R7 cannot be used to hold the address of an operand located in RAM

C

when using this addressing mode.

Memory
u
ad

Register
iln

Destination register Contents of register are

m

used to point memory

Ta

Data from
selected memory
location

Examples:

MOV A, @RO ; move contents of RAMlocation

; whose address is held by R0 into A

Here the value inside RO is considered as an address, which holds the data to be
transferred to an accumulator.
<br>

Page 35 of 440

1,22 Embedded Systems and 10T Desian

MOV @RI, B ; move contents of B

into RAM location
;whose address is held by Rl.

M Advantages
The advantages of register indirect addressing mode which make it a popular

g
addressing mode in computer architecture are,

in
() Dynamic use of data:

er
It makes accessing data dynamic rather than static as in the case of direct

e
addressing mode. Looping is not possible in direct addressing mode.

in
(i) Efficient use of memory,

ng
(üi) Flexibility in addressing, and
(iv) Easy implementation. fE
O
Limitations
The limitations of register indirect addressing mode are,
e

) RO and RI are the only registers that can be used as pointers in register
g
le

inirect addressing mode.

ol

() RO and RI are & bits wide and their use is limited to access any information
C

in the internal RAM. When accessing externally connected RAM or on-chip

u

ROM, we need 16-bit pointer. In such case, the DPTR register is used.
ad

(5) Indexed Addressing Mode: On-chip ROM Access

iln

Indexed addressing mode is widely used in accessing data elements of look-up

table entries located in the program ROM space (program memory) of the
m

or
8051. The destination operand is always the register A. Either the DPTR
Ta

PCcan be used as an index register.

Examples:
"MOVC A, @A+DPTR"

The 16-bit register DPTR and register A are added to form the address of the
data element stored in on-chip ROM. Because the data elements are stored i
<br>

Page 36 of 440

8051 Microcontroller
1.23
the program (code) space ROM of the 8051. The instruction MOVC is
used
instead of MOV and "C" means code.

"MOVC A, @A+PC"
The only difference is, instead of adding DPTR with accumulator,
here data

g
inside program counter (PC) is added with accumulator to obtain
the target

in
address.

e er
1,6 SOLVED EXAMPLES

in
Example-1

ng
Show the status of the CY, AC
and P
flag after the addition
fE of 38H and 2FH in
the following instructions.
O
MOV A,
#38H
e

ADD A, #2FH ;after the addition A =67H, CY

=0
g
le

Solution:
ol

38 00111000
C

+2F 00101111
u

67 01100111
ad

CY=0, there is no carry beyond the D7 bit.

iln

AC= 1, there is a cary from the D3 to the D4 bit.

m

P=1,the accumulator has an odd number of 1s (it has five ls).

Ta

Example-2
Show the status of the CY, ACand Pflag after the addition of 9CH and 64H in
the following instructions.

MOV A, #9CH
;
ADD A, #64H after the addition A = 00H, CY = 1
<br>

Page 37 of 440

1.24|
Embedded Systems and 10T Desig

Solution:
9C 10011100

+ 64 01100100

100 00000000

g
in
carry beyond the D7 bit.
CY=1,there is a

er
a carry from the D3 to the D4 bit.
AC=1, there is

e
even number of ls (it has zero 1s).
P=0, the accumulator has an

in
ng
Example-3
fE
Show the status of the CY, AC and Pflag after the addition of 88H and 93H i
the following instructions.
O
MOV A, #88H
e

=
;after the addition A = 1BH, CY
1
g

ADD A, #93H
le

Solution:
ol

88 10001000
C

+93 10010011
u
ad

11B 00011011

CY=1,there is a carry beyond the D7 bit.

iln

to the D4 bit.
AC =0, there is no carry from the D3
m

P=0, the accumulator has an even number of 1s (it has four

1s).
Ta

Example-4
Write code to send 55H to ports Pl and P2 using
(a) their námes (b) their addresses.
Solution:
(a) MOV A, #55H ;A=55H
MOV Pl, A ;Pl= 55H
<br>

Page 38 of 440

1.25
805I Microcontroller
MOV P2, A ;
P2 = 55H
(b) From Table 1.4, Pl address 8OH; P2 address AOH
MOV A, #5SH ;A=55H
MOV 80H, A ; Pl=5SH

MOV OAOH, A ;P2= 55H

g
in
Example-5

er
Show the code to push R5 and A onto the stack and then pop them back them

e
into R2 and B, where B =A and R2 = RS

in
ng
Solution:
PUSH 05 push R5 onto stack fE
PUSH 0EOH push register A onto stack
O
POP OFOH pop top of stack into B
e

now register B = register A

g

;
le

POP 02 pop top of stack into R2

ol

;now R2=R6
C
u

Example-6
ad

Write a programto clear 16 RAM locations starting at RAM address 60H

iln

Solution:
;A-0
m

CLR A
Ta

MOV R1,#60H
;
load pointer. Rl=60H

R7,#16 ;load counter, R7=16

MOV
@R1,A ;clear RAM R1points to
AGAIN: MOV
; increment Rl pointer
INC RI
DJNZ R7,AGAIN ;
loop until counter =zero
<br>

Page 39 of 440

Embedded Systems and 10T Design

1.26
AND ANSWERS
1.7 TWO MARKS QUESTIONS
1. What is microprocessor? unit.
a general purpose digital computer central processing
The microprocessor is
It
megabytes of memory and operates on 8, 16, or 32 bit data.
They can address
working registers, program counter,
stack
consists of an ALU, accumulator,

g
in
pointer, clock and interrupt circuits.

er
2. Define microcontroller.
in
the features that are found

e
The microcontroller incorporates all

in
as a true single-chip system that
microprocessor, but they are designed to work

ng
a system on a single-chip which is
is, it can integrate all the devices needed for
optimized for specific applications. fE set of registers,
The basic functional units of a microprocessor will be ALU,
O
functional blocks
timing and control unit. The microcontroller will have these
a programmable timer, RAM and
and in addition it may have I/O ports,
g e

EPROM/EEPROM.
le

List the features of 8051 nicrocontroller.

ol

[MAYIJUNE-06, 16 & NOVDEC-06, 22|

C

[OR]
What are the main features of 8051 microcontroller? [NOVIDEC-2017]
u
ad

[OR]
State any four inbuilt features of 8051 microcontroller. NOVDEC-2018]
iln

The feätures of 8051 microcontrollers are as follows:

m

4KB bytes on-chip program memory (ROM).

Ta

128 bytes on-chip data memory (RAM).

Four register banks.
128 user defined software flags.
8-bit bidirectional data bus.
16-bit unidirectional address bus.
32 bidirectional I/O lines organized as four
8-bit ports.
16 bit timers.
<br>

Page 40 of 440

OUJL LVLLUr UCUurouer

1.27
4- Compare (or) Differentiate microcontrollers
and microprocessors in system
design. [APRMAY-2011, 18 & NOV/DEC-2010, 11, 13, 16,
21)
Sr.NO Microprocessor Microcontroller
1. The functional blocks of a The microcontroller includes
the
microprocessor are the ALU, functional
blocks of
registers, timing and control unit.

g
microprocessor and in addition has

in
a memory, VO interfacing circuit
and peripheral devices such as

er
ADC, DAC, timer etc.

e
2
It has several instructions to move It has one or two instructions to

in
data between memory and CPU. move data between memory -and

ng
CPU.
3. The microprocessors are used for fE
Microcontrollers are used for
designing general purpose digital designing application specific
O
computing system (or computers). dedicated systems
4. It has one or two bit handling It has many bit handling
e

instructions. instructions.
g

Memory and I/0 devices access Less access time for built-in
le

5.
time is more. memory and I/O devices.
ol

5. What is the size of the on-chip program memory and on-chip data memory of
C

8051 microcontroller? [APRMAY-2011]

u

[OR]
ad

Give the memory size af 805l microcontroller. [APRMAY-2010]

iln

[OR]
Write the RAM and ROM capacity in 8051 microcontrollers.
m

[NOVDEC-2022)
Ta

4K bytes on-chip program memory (ROM).

- 128 bytes on-chip data memory (RAM).
6. Write the advantages of microcontroller. [NOVDEC-2007|
[OR]
What are the advantages of using a microcontroller in place of a
microprocessor? [APRMAY-2011]
<br>

Page 41 of 440

1.28 Embedded Systems and 10T Design

are,
The advantages of microcontroller
i) The built-in peripherals have small access time and the speed is more.
(ii) Reduced hardware due to single chip microcomputer system.

(ii) Less hardware that reduces PCB size and increases reliability of the system.

g
(iv) Low system cost.

in
er
7. What is the significance of PSEN and EA pins in 805l microcontroller?

e
NOVIDEC-2010, 19)

in
Pin 29 (PSEN)

ng
PSEN stands for Program Store Enable. It is an active-low output pin which is
used to read an external memory.
fE
O
Pin 31 (EA/Vpp)
e

It is the External Access (EA) enable pin which allows external program
g

memory. It is an input pin and connected from Vcc or GND.

le

If we want to access the program from external program memory, it must be

ol

connected with GND. If we want to use on-chip memory, it must be high

C

(connected with Vcc).

u

8. Write the functions of signals ALE/PR0G. (NOVIDEC-2010]

ad

Pin 30 (ALE/PROG)
iln

ALE stands for Address Latch Enable. It is an active-high input pin which is
m

used to distinguish between memory chips when multiple memory chips are
Ta

used.
It is also used to de-multiplex the multiplexed address and data
signals available
at port 0.
9. Define embedded system.
An embedded system is a combination
of computer hardware and software
designed for a specific function. It is a computer system
which is a combinatto
of a computer processor, computer memory, and input/output peripheral
that has a dedicated function within'a larger device
mechanical or electronic systen.
<br>

Page 42 of 440

8051 Microcontroller
1.29|
10. State any four applications of microcontrollers.
[NOVDEC-2018,22]
The main applications of microcontrollers are,

(i) Home appliances.

(ii) Computers.
(ii) Telephones.

g
(iv) Security systems.

in
Fax machines.

er
(v)
(vi) Laser printers.

e
in
I1. How the microcontrollers respond to any interrupt request?
[APRMAY-2018]

ng
Interrupts is a sub-routine call is that is given by the microcontroller when some
other program with high priority is requesting for acquiring the system buses,
fE
then interrupts occur in current running program.
Interrupts provide a method to postpone or delay the current process, to performs
O
a sub-routine task and then restart the standard program.
e

12. What are the interrupts

g

of 8051? [NOVDEC-2019]
le

[ORJ
ol

Name the interrupts of 805I microcontroller. [APRMAY-2019)

C

The five sources of interrupts in 8051 Microcontroller are,

Timer 0 overflow interrupt - TFO
u
ad

(ii) Timer 1
overflow interrupt - TF1
(iii) External hardware interrupt - INTO
iln

(iv) External hardware interrupt - INTI

m

(v) Serial communication interrupt - RXD/TXD.

Ta

13. Write tlhe function of Register.

Registers are used to store information temporarily, while the information could
be a byte of data to be processed, or an address pointing to the data to be fetched.
14. What is Program Counter (P)?
The Program Counter (PC) is a register that points to the address of the ncxt
instruction to be executed. As each instruction is executed, the PC is incremented
to point to the address of the next instruction to be executed.
<br>

Page 43 of 440

Embedded Systems and IOT Desip

1.30.

15. Write the function

of
Data pointer.
memory using h
(DTPR) is used by the 8051 to access external
Data Pointer as tue
indicated by DPTR register which is 16 bit, it can also be accessed
address
DPH and DPL, where DPH is high byte and DPL is the low byte
registers,
8-bit

g
16. Draw the PSW register.

in
[OR]

er
What is the flag register format of 8051 microcontroller?
NOVDEC- 2010)

e
PSW.1 PSW.0

in
PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2

ng
CY AC FO RS1 RSO OV P

fE
+Register bank Select bit 0
O
1
Register bank Select bit
e

17. What are the flags available in 8051? [APRMAY-2009)

g
le

The flags available in 8051 are

ol

() -Carry (CY) flag.

C

(ii) Auxiliary Carry (AC) flag.

u

(ii) Parity (P) flag.

ad

(iv) Overflow (0V) flag.

iln

18. List tlhe 8051 instructions that always clear the carry flug. (APR/MAY-2019)
m

Carry flag can also be set to or 0 directly by an instruction such as " SETB
1 C
Ta

and « CLR C" where "SETB C" stands for set bit carry" and "CLR C" to
*clear carry".

19. How do you select a register

bank in 8051 microcontroller?

[APRMAY-2010, 11, 13 & NOV/DEC-201|

The
PSW3 and PSW4 are designed as bank
RSO and RS1 respectively as the
selection bits. They are used to select
the bank registers of 8051.
<br>

Page 44 of 440

8051 Microcontroller
1.31|

RS1 RSO Register

Bank Register Bank Status
0 0 Register Bank 0 is selected
0 1
1 Register Bank 1
is selected

2 Register Bank 2 is selected

g
1 1

in
3 Register Bank 3 is selected

er
20. Define addressing node.
The CPUcan access data in various ways, 'which are called addressing

e
modes.

in
Addressing mode is a way to address an operand. Operand means source data

ng
that is the data we are operating upon. It can be adirect address of memory (or)
any register names (or) any numerical data etc.
21. What are
fE
the different ways of operand addressing in 8051.
O
NOVDEC- 2007, 09, 10 & APRMAY-2011, 17]
e

[OR]
g

What are tlhe addressing modes supported by 80S1? [APR/MAY-2019]

le

There are five different ways to execute the instructions. Therefore, 8051
ol

provides a totai of five distinct addressing modes as follows:

C

(i) Immediate addressing mode,

u

(ii) Register direct addressing mode,

ad

(iii) Direct addressing mode,

iln

(iv) Register indirect addressing mode, and

m

(v) Indexed addressing mode.

Ta

22. What is immediate addressing mode?

In this immediate addressing mode, the source operand is a constant. When an

instruction assembled, the operand comes immediately after the opcode. In
is

these instructions, the # symbol is used for immediate data.

This addressing mode can be used to load information into. any of the registers
including the DPTR register which stands for Data Pointer and it points the
external data memory location.
<br>

Page 45 of 440

Embedded Systems and 10T Design

|1.32|
Examples
;load 55H into A [move the data 55 H (that is
(i) MOV A, # 55H
in hex) immediately to register AJ.
;
(iü) MOV R4, #62 load the decimalvalue 62 into register R4.

g
in
23. Write the function of register addressing mode.

er
In the register addressing mode, the data to be operated is available inside the
register(s). We use the register name directly as source operand. Therefore the

e
in
operation is performed within the various registers of the microprocessor.

ng
Examples

MO A, R0 ; copy the contents of

R0 fE
into A.
MOV R2, A ; copy the contents of A
into R2.
O
24. Give the significance
of SFRs in 8051 microcontroller.
e

A
Special Function Register
(or Special Purpose Registers) are
g

registers closely tied to some the special

special function or status
le

might not be directly writable of the processor, they

by normal instructions
ol

Instead, some special registers (like add, move, etc.).

in some processor architectures
C

instructions to modify them. require special

This SFRs are located
u

immediately above
the 128 bytes of RAM
ad

for the operation of ALU, and responsible

timer, serial port, parallel
ports and interrupt
25. Name the SFRs control.
iln

available in 8051.
m

[OR]
List any four SFRs.
Ta

Some SFRs available [APRMAY-2017]

in 8051 are:
() Accumulator (A).
(ii) B Register.
(ii) Program Status Word
(PSW).
(iv) DPTR (data
pointer).
(v) Stack Pointer.
(vi) Interrupt Priority
Control Register.
<br>

Page 46 of 440

1.33|
8051Microcontroller

26. Whatis Register indirect addressing mode?

In the register indirect addressing mode, a register is used as a pointer to the data.
If the data is inside the CPU, only registers ROand Riare used as a pointers,
they must be preceded by the "@" sign.

Example:

g
MOV A, @RO ;move contents ofRAMlocation

in
A
;whöse address is held by RO into

er
are the advantages of the register indirect addressing mode in 8051

e
27. What
(NOV/DEC -2016]

in
microcontroller?
a popular
The advantages of register indirect addressing mode which make it

ng
addressing mode in computer architecture are,
fE
() Dynamic use of data:
as case of direct
O
It makes accessing data dynamic rather than static in the
addressing mode. Looping is not possible in direct addressing mode.
g e

(i) Efficient use of memory,

le

(ii) Flexibility in addressing, and

ol

(iv) Easy implementation.

C

List the limitations of register indirect addressing mode.

u

28.
are,
The limitations of register indirect addressing mode
ad

(1) RO and R1 are the only registers that can be used as pointers in register
iln

indirect addressing mode.

m

(i) RO and R1 are 8 bits wide and their use is limited to access any information
Ta

or on-chip
in the internal RAM. When accessing externally connected RAM
case, the DPTR register is used.
ROM, we need 16-bit pointer. In such
29` What happens when the 8051 microcontroller instruction
"MOVC A @A+DPTR" is executed?

NOVVDEC-2007 & APRMAY-2023]

"MOVC A, @A+DPTR"
<br>

Page 47 of 440

Embedded Systems and IOT Design

1.34|
are added to form the address of the data
The 16-bit register DPTR and register A
data elements are stored in the
element stored in on-chip ROM. Because the
MOVC is used instead
program (code) space ROM of the 8051. The instruction
of MOV and “C means code.

g
1.8 REVIEW QUESTIONS

in
microcontroller. [APRMAY-2011, 2012]
1. Explain the features of 805l

er
[ÄPR/MAY-2011]
2. Compare microcontrollers and microprocessors.

e
Draw the pin diagram of 80S1 microcontroller and explain the functions of

in
3.
[MA Y/JUNE -2003, l1, 13 NOVDEC-06,11]

ng
each pin.
4. Briefly discuss the ports of 805landits functions in detail. [APRMAY-2018]
5.
fE
Explain the pinouts of 8051 microcontroller. [NOVDEC-2011]
O
6. With a neat sketch of a schematic diagram, explain the functions of various
signals of 8051. [NOVDEC -2010]
e

7. Discuss in detail about the microcontrollers of an embedded system.

g
le

8. List the applications of embedded products using microcontrollers.

ol

9. Eyplain the architecture of $051 microcontroller with a neat diagram.

C

[NOVDEC- 08, 10, 16, 19, 20 & APRMAY- 0, 08, 11, 16, 17, 18, 21]
u

10. Witha functional block diagram, briefly discuss the architecture of the 8051
ad

microcontroller. [NOVDEC- 2021, 22]

iln

11. Discuss briefly the various registers used in 8051 nicrocontroller.

m

[MAYIJUNE -2008, 13]

Ta

12. Write short notes on register set of 8051 microcontroller.

[APR/MAY-2011 & NOVDEC- 2011]
13. Describe the inportance of the Program Counter, Data pointer, Program Statis
Word, Special Function Registers in 8051. [APRMAY-2019)
14. Give the details of PSW of 8051. [APRMAY-2010/
15. Explain the different addressing mode
of 8051.
NOVDEC- 2019, 20,22 & APR/MAY-2003, 16, 21/
<br>

Page 48 of 440

8051 Microcontroller 1.35

16. Discuss on the diferent types of addressing modes supported by the 8051
microcontroller with examples. [NOVDEC -2021]
17. Classify the addressing modes of 8051 microcontroller. [APRMAY-2017
18. State the merits and denerits of accessing memory using various addressing
modes. [NOVIDEC-2021]

g
in
19. Write a short note on SFR (Special Function Registers).

er
[NOVDEC- 2010 & MAYIJUNE- 2007]

e
in
ng
fE
O
g e
le
ol
C
u
ad
iln
m
Ta
<br>

Page 49 of 440

UNIT -I
Chapter

g
in
er
8051 INSTRUCTION SET

e
in
2.1.INSTRUCTION SET OF 8051

ng
2.1.1 Introduction fE
The process of writing a program for the microcontroller mainly consists of
O
giving instructions (commands) in the specific oder in which they should be
executed in the order to carry out a specific task.
e

The commands to the microcontroller are known as a microcontroller's

g
le

instruction set. The instruction groups of the 8051 microcontroller instruction set
ol

is also called as MCS-51 instruction set.

an operation code (op-code) followed by
C

A computer instruction is made up of

type of
either zero, one or two bytes of operands. The op-code identifies the
u

source and
operation to be performed while the operands identify the
ad

destination of the data.

iln

a Types of Instructions:
m

The instructions of 8051 microcontroller can be classified into five diferent

Ta

groups as follows:

() Data transfer instructions.

(i) Arithmetic instructions.
(ii) Logical instructions.
(iv) Program branch instructions.

() Boolean or Bit manipulation instructions.

<br>

Page 50 of 440

2.2 Embedded Systems and IOT Design

Like 8085, some instruction has two operands: first operand is the destination,
and second operand is source.

Mnemonics:
In computer assembler (or assembly) language, a mnemonic is an abbreviation
for an operation which specifies the type of operation to be performed and they

g
in
are translated by the. assembler. All mnemonics of the instruction are of one byte

er
size.

e
Example:

in
AND AC, 37 ; means AND the AC register with 37.

ng
A Format: fE
The format of instruction is as follows:
O
MNEMONIC DESTINATION OPERAND, SOURCE OPERAND
g e

There are 49 instruction mnemonics in the 8051

microcontroller instruction set
le

and they are divided into five groups.

ol

2.2 DATA TRANSFER INSTRUCTIONS

C
u

Definition:
ad

The data transfer instructions are associated with transfer

of data between
iln

registers or external program memory or

external data memory.. These
nstructions are used to copy the content
m

of source operand to the destination

operand.
Ta

2.2.1 MOV Instructions: MOV dest-bye,

source-byte
Mnemonic: MOV <dest -
byte>, <src- byte>
Function: Move
byte variable.
Flags: None.
This instruction copies a bvte from
are
the source location to the destination. Tnee
fifteen possible combinations
for this ínstruction:
<br>

Page 51 of 440

8051 Instruction set 2.3

(1) Register A as the Destination:

Mnemonic Description Byte Cycle

MOV A, Rn Move register to accumulator 1 1

MOV A, direct Move direct byte to accumulator 2

g
MOV A, @Ri Move indirect RAM to accumulator

in
1 1

MOV A, #data

er
Move immediate data to accumulator 2

e
(i) MOV A, Rn

in
Copy the contents ofregister Rn to A.

ng
Example: MOV A, RI
fE
This instruction will copy the contents of register RIof the selected register bank
O
to an accumulator A.

(ii) MOVA, direct

g e

Copy the contents of direct address given in the instruction toan accumulator A.
le

Example: MOV A, 40H ;A= data in 40H

ol

This instruction will copy the contents from memory location whose address is
C

40H to the accumulator.

u

(ii) MOV A, @Ri

(i=0 or 1)
ad

Copy the contents of memory location whose address is specified in the register
iln

Riofthe selected bank to the accumulator A.

m

Examples:
Ta

MOV A, @RO ;A= data pointed to by R0.

MOV A, @RI ;A =data pointed to by R1.
(iv) MOVA, #data
Copy the immediate data to an accumulator.

Example: MOV A, #31H

This instruction will move the data 3 1H immediately to the accumulator.
<br>

Page 52 of 440

Embedded Systems and IOT Design

2.4
After execution
Before execution
Accumulator Data Accumulator
Data
31 40 31 31:

g
H is copied to the accumulator

in
The data 31

er
Fig 2.1

e
(2) Register A is the Source:

in
ng
Mnemonic Description Byte Cycle

MOV Rn, A fE
Move accumulator to register. 1 1
O
MOVdirect, A Move accumulator to direct byte. 2 1
e

MOV @Ri, A Move accumulator to indirect RAM. 1 1

g
le

() MOV Rn, A
ol

Copy the contents of accumulator to the register Rn of the selected register bank.
C

Example: MOV RS, A

u
ad

Let us consider, the content of register A = 40H.

iln

Before execution After execution

Accumulator Accumulator
m

40.
40
Ta

R7 R6 R5 R4 R3 R2 R1 RO R7 R6 R5 R4 R3 R2 R1 RO

A0 Bank 0 40 Bank 0

The contents of accumulator are copied to register R5

Fig 2.2
(ii) MOV direct, A
Copy the data from an accumulator to direct address.
<br>

Page 53 of 440

8051 Instruction set

2.5
Example: MOV 80H, A

80H is the address of port 0. This instruction will copy the contents of an
accumulator to the port 0.
(iüi) MOV @ Ri, A

g
Copy data fromaccumulator to the memory location pointed by Ri.

in
er
Example: MOV@ R0, A

e
This instruction will copy the contents of an accumulator to the nmemory location

in
whose address is pointed by the RO register of the selected register bank.

ng
(3) Register Rn is the Destination:
fE
Mnemonic Description Byte Cycle
O
MOV Rn, A Move accumulator to register. 1 1
g e

MOV Rn, direct Move direct byte to register. 2 2

le

MOV Rn, #data Move immediate data to register. 2 1

ol
C

() MOV Rn, direct

Copy the contents from direct address specified in the instruction to register Rn
u
ad

of the selected register bank.

iln

Example: MOV R3, 30H

This instruction will copy the contents from address 30H to the register R3 of the
m

selected register bank.

Ta

() MOV Rn, # data

Copy the immediate data to the register Rn of
the selected register bank

Example: MOV R7, #20H

This instruction willcopy immnediate data 20H to the register R7 of the selected
register bank.
<br>

Page 54 of 440

2.6
Embedded Systems and 1OT Design
After execution
Before execution
Data
Data
20 20

R7 R6 R5 R4 R3 R2 R1 RO R7 R6 R5 R4 R3 R2 R1 RO

A0 Bank 0 20 Bank 0

g
in
The data is copied to register R7

e er
Fig 2.3

in
(4) The Destination is a Direct Address:

ng
Mnemonic Description
fE Byte Cycle
MOV direct, A Move accumulator to direct byte 2 1
O
MOV direct, Rn Move register to direct byte 2 2
MOV direct, direct
e

Move direct byte to direct byte 3 2

g

MOV direct, @Ri Move indirect RAM to direct byte 2 2

le

MV direct, #data Move immediate data to direct byte

ol

3 2
C

() MOV direct, Rn
Copy the contents of
register Rn to the direct address.
u
ad

Example: MOV 30H, RS

iln

This instruction will copy the contents of register R5

of the selectèd register bank
to the memory location whose address is 30H.
m
Ta

(ii) MOV direct, direct

Copy the data from source direct address to destination direct
address.
Example: MOV 20H, 30H

This instruction will copy the contents of memory location

whose address is 30H
to the memory location whose address is 20H.

(iiü) MOV direct, @ Ri

Copy the data from address specified in register Ri to direct address.
<br>

Page 55 of 440

8051 Instruction ser |2.7|

Example: MOV 20H, (@ RI

This instruction will copy the contents of memory location whose address is
given in RI register of sclected register bank to the memory location whose
address is 20H.

g
(iv) MOV dircct, # data

in
er
Copy the immediate data to direct address.

e
Example: MOV 30H, # 10H

in
This instruction will copy immediate data 10H to the memory location whose

ng
address is 301H.
fE
(4)Destination is an Indirect Address held by RO or R1:
O
Mnemonic Description Byte Cycle
e

MOV @Ri, A Move accumulator to indircct RAM 1 1

g

MOV @Ri, direct Move direct byte to indirect RAM 2 2

le

Move immediate data to indirect RAM 2

ol

MOV @Ri, #data

C

(i) MOV @ Ri, direct

Copy the data from direct address to memory location pointed by Ri.
u
ad

Example: MOV @ R0, 30H

iln

This instruction will copy the data from memory location whose address is 30H
to the memory location pointed by register RO of selected register bank.
m
Ta

(i) MOV @Ri, # data

Copy an immediate data o memory location pointed by the Ri register of

selected register bank.

Example: MOV R0, # 30H
This instruction will copy immediate data 30H to the memory location pointed by
RO register of selected register bank.
<br>

Page 56 of 440

Embedded Systems and IOT Design

|2.8|

(5) MOV DPTR, # data 16

Byte Cycle
Mnemonic Description
a constant 3 2
MOV DPTR, #datal6 Load data pointer with 16-bit

g
Function: Load data pointer.

in
er
Flags: None.
pointer) register with a 16-bit

e
loads the 16-bit DPTR (data
This instruction

in
immediate value.

ng
Operation: MOV
(DPTR)+# datajs -0
fE
DPH # datajs -8
O
DPL # data,-o
g e

Example: MOV DPTR, # 2476H

le

into the Data pointer, DPH

This instruction will load the immediate data 2476H
ol

willhold 24H while DPL will hold 76H.

C
u

Before execution After execution

ad

DPH DPL Data DPH DPL Data

DPTR DPTR 24 76 2476
40 30 2476
iln
m
Ta

The data 2476 H will be located to the data pointer

Fig 2.4

2.2.2 Instructions to Access External ROM/Program Memnory

Mnemonic: MOVC A, @A+<base-register>

Function : Move code byte

Flags : None
<br>

Page 57 of 440

8051 Instruction set 2.9|

Mnemonic Deseription Byte Cycle

MOVC A, @A + DPTR Move code byte relative to

DPTR to accumulator 2

g
MOVC A, @A + PC Move code byte relative to PC to

in
1
2
accumulator

er
(1) MOVC A, @A + DPTR
-

e
Operation: (A) ((A) + (DPTR))

in
This instruction moves a byte of data that is located in program (code)

ng
ROM into register A. This allows us to put strings of data, such as look-.
fE
up table elements, in the code space and read them into the CPU.
The address of the desired byte in the code space (on-chip. ROM) is
O
formed by adding the original value of the accumulator to the 16-bit
e

DPTR register.
g
le

Example:
ol

(DPTR) 100OH, (A) = 8H

=
Let
C

A + DPTR 8H + 1000H, the contents of memory location (1008H) = 22H.

=
u

After execution of this instruction (A) 22H.

ad

(2) MOVCA, @ A + PC
-
iln

Operation: (PC) (PC) + 1

-
m

(A) ((A) + (PC))

Ta

program (code)
The instruction moves a byte of data that is located in the
area to A. The address of the desired byte of data is formed by adding the
is used
PC register to the original value of the accumulator. Here, the PC
instead DPTR to generate the data address.
of
Example:
Let (PC) = 4000H, and (A)= 50H.Initially the 16 bit address is computed as,
<br>

Page 58 of 440

2.10| Embedded Systems and 10T Design

(PC) = (PC) + 1

= 4000H + 1H =4001H

(A) + (PC) 50H+ 4001H = 4051H

This instruction will copy the contents of memor location 405111 to the

g
in
accumulator.

er
2.2.3 Instructions to Access External Data Memory

e
in
MOVX dest-byte, source-byte

ng
Function: Move external

Flags: None.
fE
O
This instruction transfers data betwcen cxternal memory and
register A. The
8051has 64 K bytes of data space in addition to the
64 Kbytes of code space.
e

This data space must be connccted externally and this instruction

g

allows us to
le

access externally conncctcd memory.

ol

(1) The l6- bit external memory address is held by the

DPTR register.
C

(a) MOVX A;@ DPTR

u

This instruction moves a byte from external nemory

ad

whose address is
pointed to by DPTR into the accumulator.
iln

(b) MOVX @ DPTR, A

m

This instruction moves the contents of the accumulator to

the cxtermal
Ta

memory location whose address is held by DPTR.

(2) The -bit address of external memory is held by RO or R1.

(a) MOVX A,@ Ri ;where i =0 or I

This instruction moves a byte from external memory whose S-bit address is
pointed to by the register Ri into the accumulator.
<br>

Page 59 of 440

8051: Instruction set

|2.11
(b) MOVX @ Ri, A
This instruction moves the contents
of the accumulator to the external
memory location whose
8-bit address is pointed to by the register Ri
into
the accumulator.

g
in
2.2.4 Data Transfer with Stack (PUSH
and POP) Instructions

er
Mnemonic Description Byte Cycle

e
in
PUSH direct Push direct byte onto stack 2 2

ng
POP direct Pop direct byte from stack 2 2
(1) PUSH direct
fE
O
Function: Push onto the stack.
Flags: None
e
g

Operation: (SP) 4- (SP) + 1

-
le

(SP)) (direct)
ol

This copies the indicated byte of data onto the stack and increments SP by 1. This
C

instruction supports only direct addressing mode.

u

Example: PUSH 03 ;03 is the RAM address of R3 of bank 0.

ad

(2) POP direct

iln

Function: POP from the stack.

m

Flags: None
Ta

Operation: (direct) (SP))

(SP) -(SP) -1
This copies the byte of data pointed to by SP (Stack Pointer) to the location
whose direct address is indicated, and decrements SP by 1. This instruction
Supports only direct addressing mode.

Example: POP 03 ;03 is the RAM address of R3 of bank 0.

<br>

Page 60 of 440

2.12| Embedded Systems and 1OT Design:

2.2.5 Data Exchange Instructions

Description Byte Cycle
Mnemonic
with byte variable. 1/2
- 1
XCH A,<byte>Exchange accumulator

g
1
Exchange register with accumulator.
1

in
XCH A, Rn

er
1
XCH A, direct Exchange direct byte with accumulator. 2

e
in
1
Exchange indirect RAM with accumulator.
1
XCH A, @Ri

ng
Exchange low -order nibble indirect RAM 1 1
XCHD A, @Ri fE
with A.
O
(1) XCHA, Byte
e

Function :
Exchange Accumulator (A) with a byte variable.
g

Flags: None.
le

This instruction swaps the contents of register A and the source byte. The sourc
ol

byte can be any register of RAM location.

C

Example:
u
ad

MOV A, #65H ;A=65H

MOV R2, #97H ;R2 = 97H
iln

XCH A, R2 now A
=97H and R2 =65H
m

(2) Addressing Modes:

Ta

For the XCH A, byte" instruction

there are a total of three addressing modes:
(i) Register Mode:

Mnemonic: XCH A, Rn
Exchanges the register with
the accumulator.
Example: XCH A, R3
<br>

Page 61 of 440

8051 Instruction set

|2.13|
(i) Direct Mode:
Mnemonic: XCHA, direct
Exchanges the direct byte with the accumulator.

Example: XCH A, 40H ; exchange A with data in RAM location 40H.

g
() Register - Indirect Mode:

in
er
Mnemonic: XCH A, @Rn

e
Exchanges the indirect RAM with the accumulator.

in
ng
Examples: XCH A, @RO XCH A with data pointed to by RO.

(3) XCHD A, @ Ri fE
Mnemonic: XCHD A@Ri
O
Function: Exchange digits
e

Flags: None
g
le

The XCHD instruction exchanges only the lower nibble of accumulator

-
ol

(bits 3 0) with the lower nibble of the RAM location pointed to by Ri (bits 3 –0)
while leaving the upper nibbles (bits 7-4) of each registers remain unchanged.
C

Operation: (A)g-o) (Rig-o))

u
ad

Example: XCHD A, @R0

iln

Let RO contain address 37H, accumulator contain address 25H, and the interhal
RAM location 37H contain 27H.
m

After execution of the XCHD instruction, we have A =27 H and RAM location
Ta

37 H has 25H.

2,3 ARITHMETIC INSTRUCTIONS

Arithmetic instructions perform several' basic operations such as addition,
subtraction, division, multiplication etc. After execution, the result is stored in
the first operand.
<br>

Page 62 of 440

Embedded Systems and 10T Desin

|2.14

2.3.1. ADD A, SOurce byte

Description Byte Cycle
Mnemonic
Add immediate data to 2 .
1
ADD A, #data accumulator
1

ADD A,Rn Add register to accumulator

g
1
ADD A,direct Add direct byte to accumulator 2

in
Add indirect RAM to 1 1

er
ADD A,@Ri .accumulator

e
in
:
Mnemonic ADD A, <source-byte>

ng
Function : Add

Flags
:
OV, AC, CY fE
This instruction adds the source byte to the accumulator (A), and places the
O
result in A. Since register A is one byte in size, the source operands must also
be one byte.
g e

The ADD instruction is used for both signed and unsigned numbers.
le

(1)Addressing Modes:
ol

The following addressing modes are supported for the ADD instruction:
C

(i) Immediate Mode

u
ad

:
Mnemonic ADD A, # data

+ (A) +# data
iln

Function (A)
This instruction will add the immediate
m

8-bit data with data in the accumulator.

Example : ADD A, # 25H
Ta

(i) Register Mode

Mnemonic :ADD A, Rn

Function : (A) ¢- (A) + (Rn)

Thisinstruction will add the
byte in register Rn of bank
with the byte in the accumulator. the selected register
<br>

Page 63 of 440

8051 Instruction set

2.15|
:
Example ADD A, R3
(iii)Direct Mode
:
Mnemonic ADD A, dircct
Function : (A) <-(A) +
(direct)

g
This instruction adds the direct byte to the accumulator.

in
er
Example ADD A, 30H :
Add A data in RAM location 30H.

e
(iv) Register-indirect Mode

in
:
Mnemonic ADD A, @ Ri where
i=0 or
i=1 only

ng
Function (A) + (A) + (Ri))
fE
This instruction will add the contents of memory location whose address is
pointed by register Ri of the selected register bank with the contents of the
O
accumulator. The result of addition is stored in the accumulator.
e

Examples:
g
le

ADD A @ RO ;add to A data pointed to by RO.

ol

ADD A @ RI ;add to A data pointed to by R1.

C

2.3.2 ADDC A, source byte

u
ad

Mnemonic Description Byte Cycle

Add register to accumulator
iln

ADDC A, Rn 1
with carry flag.
m

Add direct byte to accumulator

ADDC A, direct 2 1
with carry flag.
Ta

Add indirect RAM to 1

ADDC A,@ Ri 1
accumulator with carry flag.
Add immediate data to
ADDC A, # data accumulator with carry flag.
2

Mnemonic :
ADDCA, <source-byte>
Function
:
Add with carry flag.
<br>

Page 64 of 440

|2.16| Enbedded Systems and 10T Design

Operation
:
A+A)
+
<source-byte> + CY
:
Flags OV, AC, CY
This instruction will add the source byte to A, in addition to the CY flag
(A=A+byte + CY).
(a) If CY - lprior to this instruction CY is also added to A.

g
in
(b) If CY = 0prior to the instruction, source is added to destination plus 0

er
which is used in multibyte additions.

e
(1) ADDC A, Rn

in
Operation :A¢(A) + (Rn) + (CY)

ng
This instruction will add the contents
of accumulator with the contents of
register Rn of the selected register bank and carry flag.
fE The result of addition is
stored in accumulator.
O
Example ADDC A, R2
Adds the contents of A, R2 and carry
e

(CY) flag and stored result in A

g

(2) ADDC A, direct

le

Operation : A+(A) + (direct) + (CY)

ol

Adds the direct byte to the

accumulator with a carry
C

flag.
Example :
ADDCA, 10H
u

Adds the contents

of A, memory location whose address
ad

flag and stores result in A. is 10 H and the carry

iln

- (3)
ADDC A, @ Ri
m

:
Operation A+ (A) + (Ri) + (C)
Ta

Adds the indirect RAM to

the accumulator with a carry
flag.
Example :
ADDCA, @ RO

(4) ADDC A, # data

Operation : A+A) + # data + (CY)
A dds the immediate
data to the accumulator with a carry
flag.
<br>

Page 65 of 440

8051 Instruction set

|2.17|
Example : ADDC A, #20H
Adds the contents of A and carry flag and 2OH and stores
result in A.
2.3.3 SUBB A, source byte
Mnemonic Deseription Byte Cycle

g
SUBB A, #data Subtract immediate data from

in
A with borrow. 2

er
SUBB A, Rn Subtract register from A with
1 1

e
borrow.

in
Subtract direct byte from A
SUBB A, direct 2 1

ng
with borow.
SUBB A,@Ri Subtract indirect RAM from A
with borrow fE 1

Mnemonic : SUBBA, <src-byte>

O
Function :
Subtract with borrow.
e

: OV, AC, CY
g

Flags
le

This instruction subtracts the source byte and the carry lag from the
ol

accumulator and puts the result in the accumulator.

C

The steps for subtraction performed by the internal hardware of the CPU are
as follows:
u

(i) Take the 2's complement of the source byte.

ad

(ii) Add this to register

A.
iln

(iii) Invert the carry.

m

This instruction sets the carry flag (C) according to the following:
Ta

Sr.No Condition CY Status

dest > source 0 Result is positive'
(ii) dest = source Result is
0.
(ii) dest < source 1 Result is 'negative' in 2'scomplement.
<br>

Page 66 of 440

2.18 Embedded Systems and 10T Design

There is no SUB instruction in the 8051. Therefore, we perform the SUR

instruction by making CY = 0 and then using SUBB: A = (A- byte -CY)
Example:
MOV A, #45H
CLR

g
in
SUBB A, # 23H :45H-23H -0=22H
(1) Addressing Modes

er
The following four addressing modes are supported

e
for the SUBB:

in
(i) Immediate Mode

ng
Mnemonic : SUBB A, #
data
Operation : (A)-(A)- (CY)-#data fE
Subtracts the immediate data
from the accumulator with a borrow.
O
.Example : SUBB A, #25H
;A=A-25H– CY
e

(ii) Register Mode

g
le

Mnemonics : SUBB A, Rn
ol

Operation : (A) <- (A)-(C)- (Rn)

C

Subtracts the register from

the accumulator with a borrow.
u

Example : sUBB A, R3
;A=A-R3-CY
ad

(ii) Direct Mode

iln

Mnemoniçs: SUBB A, direct

m

Operation : (A)+(A)-(C)- (direct)

Ta

Subtracts the direct byte

from the accumulator with a
borrow.
Example :SUBB A,
30H ;A- data at
-
(30H) CY
(iv) Register-indirect Mode

Mnemonics: SUBB A, @ Rn
Operation : (A) + (A)- (Rn) -CY
Subtracts the indirect RAM from the accumulator
with a borrow.
<br>

Page 67 of 440

8051.Instruction set
2.19
Example : SUBB A,@RO
;A- data at (R0) -CY
2.3.4 INC byte
Mnemonic Description Byte Cycle
INC A Increment Accumulator 1 1

INC Rn

g
Increment Register 1 1

in
INC direct Increment direct byte 2 1

er
INC @Ri Increment indirect RAM 1 1

e
Mnemonic INC <byte>

in
Function :
Increment

ng
:
Flags None
Operation :
<byte=<byte>+1 fE
This instruction adds 1 to the register or memory location specified by the
O
operand. This instruction supports the following addressing modes.
e

(1) Accumulator (A)

g
le

:
Mnemonic INCA
ol

Operation <A><A>+ 1
C

Increments the accumulator by 1.

u

(2) Register Mode

ad

Mnemonic :
INC Rn
iln

.(Rn) ¢- (Rn) +
1
Operation
m

Increments the register by 1.

Ta

Example :
INC RI
(3) Direct Mode

Mnemonic :
INC direct
Operation (direct) 4- (direct) +1
This instruction will increment the contents of memory location whose direct
address is specified in the instruction by 1.
<br>

Page 68 of 440

2.20|
Embedded Systems and IOT Design

:
INC 30H ;Increment byte in RAM location 30H.
Example

(4) Register-indirect Mode

Mnemonic INC@ Ri (i=0 or 1)

Operation : (Ri) - (Ri) + 1

g
Increments the indirect RAM by 1.

in
Example INC @ RO Increment byte pointed to by RO.

e er
2.3.5 DEC byte

in
Mnemonic Description Byte Cycle

ng
1 1
DEC Á Decrement Accumulator
DEC Rn' Decrement Register
fE 1. 1
O
1
DEC direct Decrement direct byte 2
1 1
DEC @Ri Decrement indirect RAM
g e

Mnemonic DEC <byte >

le
ol

Function Decrement
C

Flags None
u

>
Operation <byte <byte >-1
ad

This instruction subtracts 1 from the byte operand and CY (carry/borow) is

iln

unchanged. This instruction supports,four addressing modes:

m

(1)Accumulator (A)
Ta

Mnemonics DEC A

Operation (A) + (A)-1

(2) Register Mode

Mnemonics DEC Rn

Operation (Rn) - (Rn)- 1

<br>

Page 69 of 440

8051Instruction set
|2.21
Example DEC R1
Decrements contents of RI by 1

(3) Direct Mode

Mnemonics DEC <Direct>.

g
in
Operation (direct) ¢- (direct)- 1

er
Example DEC 40H ;Decrement byte in RAM location 40H by 1.

e
(4) Register - indirect Mode

in
Mnemonics

ng
DEC@ Ri ;where i = 0 or lonly.
– 1
Operation (Ri)) –(Ri)) fE
This instruction will decrement the content of memory location pointed by the
O
register Ri by 1
e

Example DEC @ RO ;
Decrement byte pointed to by RO.
g
le

2.3.6 INC DPTR

ol

Mnemonic Description Byte Cycle

C

INC DPTR Increment Data Pointer 1

2
u
ad

Mnemonics INC DPTR

iln

Function Increment data pointer

m

Flags None
Ta

Operation (DPTR) + (DPTR)+ 1

1. DPTR
instruction increments the 16- bit registers DPTR (data pointer) by
This version
Register that can be incremented. There is no decrement
is the only 16 bit
of this instruction.
;
DPTR= 16FFH
Example MOV DPTR, #16FFH
; now DPTR = 1700H
INC DPTR
<br>

Page 70 of 440

|2.22 Embedded Systems and 1OT Design

Before execution
After execution
DPL DPH DPL
DPH
DPTR 17 00
DPTR 16 FF

g
The contents of DPTR are incremented by 1

in
Fig 2.5

e er
2.3.7 MUL AB

in
Mnemonic Description Byte Cycle

ng
MUL AB Multiply A and B 4
Mnemonics MUL AB
fE
O
Function Multiply AxB
Flags Ov, CY
e

-
g

Operation (A) 1-10 (A) x (B)

le
ol

This multiplies an unsigned byte A

in by an unsigned byte
C

in register B. The
result is placed in A and B where A
has the lower byte and B has
the higher
u

byte.
ad

This instruction always clears

the CY flag and OV is changed
according to the
iln

product.
m

Example:
Ta

MOV A, #5
MOV B, #7
MUL AB ;A=35= 23H, B=00

2.3.8 DIV AB
Mnemonic Description Byte Cycle
DIV AB Divide A by B
<br>

Page 71 of 440

8051 Instruction set

2.23|
Mnemonics DIV AB
Function Divide
Flags CY and OV
Operation A (quotient) - A +B

g
in
B (remainder)

er
This instruction divides a byte accumulator
by the byte in register B. It is

e
assumed that both registers A and B contains an
unsigned byte.

in
After the division, the quotient will be in register A and the

ng
remainder in
register B.

Example
fE
O
MOV A, #35
e

MOV B, #10
g

B = 5
;A=3and
le

DIV AB
ol

-
2.3.9 DecimalI Arithmetic: DA A
C

Mnemonic Deseription Byte Cycle

u

Decimal Adjust Accumulator 1

ad

DA A
Mnemonic :
DA .A
iln

Function : Decimal-adjust accumulator after addition

m

Flags CY
Ta

to convert the result

This instruction is used after addition of BCD members
cases.
back to BCD. The data is adjusted in the following two possible
of A, ifit is greater than 9 or ifAC=1.
) It adds 6 to the lower 4 bits
greater than 9 or ifCY = 1.
(ii) It alsO adds 6 to the upper4 bits ofA if it is
Operation:
or [AC =1]
() IF [(As-) >9]
<br>

Page 72 of 440

2.24| Embedded Systems and IOT Design

Then [(As-o)- (Ag-o + 6]

=
If [(A7-) >9] or 1]
CY
[
(ii)

Then [(A,-4)= (A,-4) + 6]

g
Example:

in
MOV A, #47H ;A=0100 0111

er
ADD A, #38H ;A=47H+38H =7FH, invalid BCD

e
in
DA A ;A=1000 0101 = 85H, valid BCD

ng
47H
+ 38H fE
7FH (invalid BCD)
O
+ 6H (after DA A)
e

85H
g

(valid BCD)
le

In the above example, the lower nibble was greater

than 9, DA added 6 to A.
ol

2.4 LOGICAL INSTRUCTIONS (OR)

C

BIT LEVEL LOGICAL INSTRUCTIONS

u

A Logical instructions can

ad

perform logical operations upon

of tworegisters corresponding bits
like AND, OR, XOR, NOT,
Rotate, Clear and Svap.
iln

performed on bytes data on a They are

of bit-by-bit basis. Afler execution,
the result is
m

stored in the frst operand.

Ta

2.4.1 ANL dest-byte, source-byte

Mnemonic Description
Byte Cycle
ANL AND immediate data to
A, #data
accumulator 2
ANL A, Rn AND register to accumulator
AND direct byte to
ANL A, direct
accumulator 2
<br>

Page 73 of 440

t InsIuctionset
|2.25|
ANL
A,@Ri AND indirect RAM to
accumulator 1 1

ANL direct, #data AND immediate data to

direct
byte 3 2
ANL direct, A AND accumulator to direct
byte 2 1

g
Mnemonic ANL <dest-byte>, <sre-byte>

in
er
Function Logical AND for byte variables

e
Flags None affected.

in
This instruction performsa logical AND on

ng
the operands, bit by bit and storing
the result in the destination. Both the source
and destination values. are byte-size
only.
fE
O
A B
AAND B
g e

1
le

1. 0
ol

1
C

Example:
u

MOV A, #39H ;A=39H

ad

ANL. A, #09H ;A39H ANDed with 09

iln

39 0011 1001
m

09 0000 1001
Ta

09 0000 1001

for the ANL instruction there are a total of six addressing modes. Out of six, in
Jour of them, the accumulator must be the destination.
(1) Immediate
Mode
Mnemonic :
ANL A, #data
<br>

Page 74 of 440

|2.26 Embedded Systems and 10T Desig

Operation (A) +(A) A (data)

Example ANL A, #25H

(2) Register Mode

: ANL A, Rn

g
Mnemonic

in
Operation : (A)+(A) a (Rn)

er
Example ANL A, R3

e
in
(3) Direct Mode

ng
Mnemonic : ANL A, direct

Operation (A) +
(A)a (direct)
fE
:
Example ANL A, 30H ;ANDA with data in RAM location 30H.
O
(4) Register-indirect Mode
e

Mnemonic : ANL A, @ Ri
g
le

:
Operation (A) +(A) ^ (Ri)
ol

Example ANL A, @ RO ;AND A with data pointed to by RO.

C

tp In the next two addressing modes the destinàtion is a direct address (a RAN
u

location or one of the SFR registers) while the source is either A or immediatt
ad

data.
iln

(5) ANL Direct, #data

Mnemonic ANL Direct, #data
m

-
Ta

Operation :
(direct) (direct) a (#data)
Example :
ANL 32H, #44H
Assume that RAM location 32H has
the value 67H.
44H 0100 0100
67H 0110 0111
44H. 0100 0101
<br>

Page 75 of 440

8051 Instruction set

2.27|
Therefore, it has 44H.

(6) ANL direct, A

Mnemonic: ANL direct, A

:
Operation (direct) (direct) a

g
(A)

in
Example:

er
MOV B, #44H ;B=44H

e
in
MOV A, #67H ;A=67H

ng
ANL 0FOH, A
;A AND B (B is located at RAM FOH)
fE
; after the operation B = 44H
O
2.4.2 ORL dest-byte, source-byte
e

Mnemonic Deseription Byte Cycle

g

ORL A, #data OR immediate data to accumulator 2

le

ORL A, Rn OR Register to accumulator 1

ol

ORL A, direct OR direct byte to accumulator 1

C

ORL A, @Ri OR indirect RAM to accumulator 1 1

u

ORL direct, # data OR immediate data to direct byte 3 1

ad

ORL direct A OR accumulator to direct byte 2 1

iln

Mnemonic : ORL <dest-byte>, <src-byte>

m

Function : Logical OR for byte variable.

Ta

Flags :
None

Operation <dest-byte> <-<dest-byte>

V
<src-byte>

* This performs a logical OR on the byte operands, bit by bit, and stores the result in
the destination.

A B A OR B

0
<br>

Page 76 of 440

|2.28 Embedded Systems and 10T Design

1 1

1 0 1

1 1

g
Example

in
MOV A, #32H ;A=32H

er
MOV R4, #50H ; R4= 50H

e
ORL

in
;
A, R4 (A=72H)

ng
32H 0011 0010
50H 0101 0000 fE
72H 0111 0010
O
For the ORL instruction there are a total of six addressing
modes. Out of six, in
e

four of them, the accumulator must be the destination.

g

(1) Immediate Mode

le

:
Mnemonic ORL A, #data
ol

(A)<- (A)V (#data)

C

Operation
:,
u

Example. ORL A, #25H

ad

(2) Register Mode

iln

Mnemonic ORL A, Rn
m

Operation : (A)+ (A) V (Rn)

Ta

Example :
ORL A, R3

(3) Direct Mode

Mnemonic : ORL A, direct

Operation (A) <- (A) V (direct byte)

:
Example ORL A, 30H :0R A with
data located in RAM 30H.
<br>

Page 77 of 440

R051-Tnstruction set..
2.29
14) Register-indirect Mode
Mnemonic :
ORL A, @Rn
Operation (A) -(A) V (Ri)
Example : ORL A, @RO ; OR A with data
pointed to by RO.

g
A In the next two addressing modes the
destination is a direct address (a RAM

in
location or one o
the. SFR registers) while the source is either A or immediate

er
data.

e
in
(5) ORL direct, #data

ng
Mnemonic :ORL direct, #data

Operation : (direct byte) - fE

(direct byte) V (#data)

Example :
O
six, in
ORL 32H, #44H ;OR 44H with contents of RAM location 32H
g e

MOV A, 32H :Move content of RAM location 32H to A.

le

44H 0100 0100

ol
C

67H 0110 0111

u

67H 0110 0111

ad

Therefore, A willhave 67H.

iln

(6) ORL direct, A

m

Mnemonic
:
ORL direct,
Ta

Operation : (direct) + (direct) V

(A).

Example
44H
MOV B, #44H ;B=
MOV A, #67H ;A=67H
FOH
ORL OFOH, A ;
ORA and B. (Bis at RAM
; After the operation B =67H
<br>

Page 78 of 440

Embedded Systems and IOT Design

2.30

2.4.3 XRL dest-byte, source-byte Byte Cycle

Mnemonic Deseription
Exclusive-OR immediate 2
1

XRL. A, #data data to accumulator

Exclusive-OR Register to 1

g
XRL A, Rn accumulator

in
Exclusive-OR direct byte to 2
1

er
XRL A, direct accumulator

e
Exclusive-OR indirect RAM 1 1

in
XRL A, @Ri to accumulator

ng
Exclusive-OR immediate 3 2
XRL. direct, #data data to direct byte

XRL direct, A
fE
Exclusive-OR accumulator 2
1

to direct byte
O
Mnemonic : XRL <dest-byte>,.<src-byte>
e

: Logical exclusive-OR for byte variables.

g

Function
le

:
Flags Noné
ol
C

Operation <dest-byte>t<dest-byte> @ <sro-byte>

u

# This performs a logical exclusive-OR on the byte operands, bit by bit, storing the
ad

result in the destination.

iln

A B A XORB
m

0
Ta

1
1

1
0
1 1

Example:

MOV A, #39H A=39H

XRL A, #09H ;A=39H ORed with 09
<br>

Page 79 of 440

8051Instruction set 2.31

39H 0011 1001
09H 0000 1001
30 0011 0000
4 For the XRL instruction, there are total of sixaddressing modes. In four of them,

g
the accummlator must be the destination.

in
(1) Immediate Mode

er
Mnemonic : XRL A, #data

e
in
Operation (A) + (A) (#data)

ng
Example : XRL A, #25H

(2) Register Mode

fE
Mnemonic :XRL A, Rn
O
Operation : (A)+(A) >
(Rn)
g e

Example : XRL A, R3
le

.(3) Direct Mode

ol
C

Mhemonic :
XRL A, direct
u

:
(A) ¢-(A) (direct)
Operation
ad

Example : XRL A, 30H ;XRLA with data in RAM location 30H.

iln

(4) Register-indirect Mode

m

Mnemonic : XRL A, @Rn

Ta

Operation (A) + (A) > (Rn))

A, @RO ;XRLA with data pointed to by RO.
Example :XRL
is a direct dddress (a RAM
* In the next two addressing modes the destination
location or one of the SFR registers) while the
source is either A or immediate
data.
<br>

Page 80 of 440

|2.32 Embedded Systems and IOT Desigh

(5) XRL direct, #data

Mnemonic : XRL direct, #data

: (direct) (direct) (# data)

Operation
value 67H.
Example: Assume that RAM location 32H has the

g
32H, #44H

in
XRL
A, 32H ; move content of RAM
location 32H to A.

er
MOV

e
44H 0100 0100

in
0110 0111

ng
67H
23H 0010 0011
fE
Therefore A will have 23H.
O
(6) XRL direct, A
e

:
Mnemonic XRL direct, A
g
le

Operation :
(direct) (direct) (A)
ol

Example
C

MOV B, #44H ;B=44H

u

MOV A, #67H ;A=67H

ad

XRL 0FOH,A ; OR register A and B

iln

;
(register B is located at RAM location FOH)
m

;
after the operation B =23H
Ta

2.4.4 CLR
Mnemonic perands Description Byte Cycle

CLR A Clear accumulator 1 1

CLR bit Clear direct bit 2 1

<br>

Page 81 of 440

8051 Instruction set

2.33
(1)CLR A
Mnemonic : CLRA
Function :
Clear accumulator
:
Flags None are affected

g
Operation .: A
0

in
This instruction clears register A and all bits
of the accumulator are set to 0.

er
Before execution

e
After execution
Accumulator Accumulator.

in
77

ng
Accumulator 00
is cleared

Fig 2.6
fE
O
(2) CLR bit
Function: Clear bit
g e

This instruction clears a single bit. The bit can be the carry flag, or any bit
le

addressable location in the 80S1.

ol

=
Example: CLR P1.7 ;CLEAR P1.7 (P1.7 0)
C

2.4.5 CPL
u
ad

Mnemonic Deseription Byte Cycle

iln

CPL A
Complement accumulator 1 1
m

CPL bit omplement bit 2 1

Ta

(1) CPLA
Mnemonic : CPLA
Function Complement accumulator
Flags None are affected

Operation : A +
<br>

Page 82 of 440

Embedded Systems and IOT Design

2.34|
1
(accumulator). The result is the
This, complements the contents of register A
become ls and ls become Os.
complement of the accumulator. That is: 0s
:
Example
Let A = 57H0101 0111

g
Complement = 1010 1000 48H

in
Before execution After execution

er
Accumulator Accumulator

e
57 48

in
Complemented

ng
Fig 2.7

(2) CPL bit

fE
Mnemonic : CPL bit
O
Function : Complement bit.
g e

Operation :(bit) <- (bit)

le

This instruction complements a

single bit. The bit can be any bit addressable
ol

location in the 8051.

C

2.4.6 Rotate and Swap Instructions

u

Mnemonic Deseription Byte Cycle

ad

RL A Rotate accumulator left 1 1

iln

Rotate accumulator left through

RLC A 1
carry.
m

RR A Rotate accumulator right

Ta

RRC A
Rotate accumulator right through
Carry.
SWAP A Swap nibbles within the 1
1
accumulator
(1) RLA
Mnemonic : RL A

Function : Rotate the accumulator

left
<br>

Page 83 of 440

8051 Instruction set

2.35
:
Flags None
Operation :
(Dn+1) - (Dn) where n=0 to 6
(D0) 4-(D7)
This instruction will rotate the eight bits in the
accumulator by one bit to the left.

g
Bit 7 is rotated into the bit 0 position.

in
er
D7 D6 D5 D4 D3 D2 D1 DO

e
in
ng
MSB LSB

:
Fig 2.8 fE
Example
O
MOV A, #69H ;A=01101001
e

; Now
RL A A= 11010010
g
le

(2) RLC A
ol

:
Mnemonic RLCA
C

Function :
Rotate the accumulator left through carry
u

:
Flags CY
ad

Operation :
(Dn+1)¢- (Dn) wheren=0 to 6
iln

(D0) (CY)
m

(CY) +(D7)
This instruction will rotate the eight bits in the accumulator and the carry flag
Ta

together by one bit to the left. Bit 7 will move into carry and original carry will
move to it
0' positions.

D7 DO

MSB LSB

Fig 2.9
<br>

Page 84 of 440

Embedded Systems and 10T Design

2.36|

Example:
CLR C ;CY=0
A, #99H ;A=10011001
MOV
; Now A=00110010and CY=1
RLC A
; Now A=01100101 and CY=0

g
RLC A

in
er
(3) RRA
: RR A

e
Mnemonic

in
: Rotate accumulator right
Function

ng
: None
Flags
Operation
fE
:(Dn) -(Dn+1) where n =0 to 6

(D7) + (D0)
O
one position to the
This instruction will rotate the eight bits in the accumulator by
e

right. Bit O is rotated into 7th position.

g
le

D5 D4 D3 D2 D1 DO
ol

D7 D6
C
u

MSB LSB
ad

Fig 2.10
iln

Example:
m

-;
MOV A, #66H A=01100110
Ta

; =
RR A Now A
00110011
RR A ; Now A= 10011001

(4) RRCA
Mnemonic RRC A
Function : Rotate the accumnulator right
through carry
:
Flags CY
<br>

Page 85 of 440

805IInsTUction set
2.37
Operation : (Dn) (Dn+1), where n
=0to 6
(D7) - (C)
. (CY)+ DO
This instruction will rotate
the eight bits in accumulator

g
together by one bit position to and the carry flag
the right. Bit 0 moves into

in
original carry flag contents move the carry flag,
into bit 7.

er
D7 D6 D5 D4 D3

e
D2 D1 DO

in
ng
fE Carry
flag

Fig 2.11
O
the Example:
e

SETB C ;CY =1
g

MOV
le

A, #99H ;A=10011001
ol

RRC A ;Now A=11001100 and CY =

1.
C

(5) SWAP A
u

Mnemonic :
SWAPA
ad

Function : Swap nibbles within the accumulator

Flags : None
iln

Operation :(D3- DO)

> (D7-D4)
m
Ta

D7 D4 D3 DO

Higher Lower
nibble nibble

Fig 2.12
<br>

Page 86 of 440

Embedded Systems and IOT Design

|2.38
(D3 – D0) with the upper
This SWAP instruction interchanges the lower nibble
nibble (D7 – D4) inside register A.
Example:
MOV A, #59H ;A=59H (0101 1001 in binary)

g
SWAP A ;A=95H (1001 0101 in binary)

in
er
2.5 BIT- ORIENTED INSTRUCTIONS
This is also called as Boolean or Bit inanipulation instructions. It is similar

e
in
to logic instructions which perform the logic operations. The difference is that

ng
these are performed upon single bits.

2.5.1 CLR Bit fE

Mnemonic Description Byte Cycle
O

CLR C Clear carry flag 1

e

1
g

CLR bit Clear direct bit 2

le

Function: Clear bit

ol

This instruction clears a single bit:

C

That bit can be the carry flag or any -

addressable location in the 8051. bit
u

(i)CLR C
ad

Operation: (CY) ¢-0

iln

(ii) CLR bit

m

Operation: (bit)
-0
Ta

2.5.2 SETB bit

Mnemonic Description Byte Cycle

SETB C Set carry flag 1
1

SETB bit Set direct bit

2 1
<br>

Page 87 of 440

8051 Instruction set

2.39
Function: Set bit
This sets high the indicated bit which can
be the carry or any directly addressable
bit of a port register, or RAM location.

) SETBC
Operation:
(CY)+1

g
in
(iü) SETB bit

er
Operation: (bit) 1

e
Example:

in
SETB P13 ; P1.3 = 1

ng
2.5.3 ANL C, Source - bit fE
Function : Logical AND for bit variables.
O
:
Flag CY
g e

Mnemonic Description Byte Cycle

le

AND direct bit to carry flag

ol

ANL C, bit 2 2
C

ANL C, bit AND complement of direct bit to carry 2 2

u

In this instruction the carry flag bit is ANDed with a source bit and the result is
ad

placed in carry. Therefore, if source bit = 0, CY is cleared; otherwise, the CY

iln

flag remains unchanged.

m

() ANL C, bit
Ta

Operation: (C) + (C) (bit)

(G) ANL C, /bit

(bit)
Operation: (C) ()a
2.5.4 oRL C, Source-bit
Function : Logical OR for bit variables.
Flags :
CY
<br>

Page 88 of 440

Embedded Systems and 10T Design

2.40
Mnemonic Description Byte Cycle

OR direct bit to carry flag 2 2

ORL C, bit

OR complement of direct bit to

carry 2 2
ORL C, bit

g
a source bit and the result is
In this instruction the carry flag bit is ORed with

in
source bit is 1, CY is set; otherwise,
placed in the carry flag. Therefore, if the

er
the CY flag remains unchanged.

e
in
() ORL C, bit

ng
Operation: (C)+(C)v (bit)
(ii) ORLC, bit fE
Operation: (C) + (C) (bit)
O
e

2.5.5 MOV dest-bit, source-bit

g
le

Function :Move bit data.

ol

Flag : CY
C

Operation:< dest-bit> << src-bit>

u
ad

Mnemonic Description Byte Cycle

iln

MOV C, bit Move direct bit to carry flag 2 1

m

MOV. bt, C Move carry flag to direct bit. 2 2

Ta

This MOV instruction will copy the source bit to the

destination bit. In this
instruction one of the operands must be
the CY flag.
(1) MOV C, bit
Operation: (C) ¢- (bit)
(ii) MOV bit, C
Operation: (bit) - (C)
<br>

Page 89 of 440

8051 Instruction set

2.41
6
BRANCH INSTRUCTIONS (OR) JUMP AND CALL INSTRUCTIONS
(OR) PROGRAM AND MACHINE CONTROL INSTRUCTIONS
PROGRAM BRANCHING INSTRUCTIONS
(OR)
The branch instructions are used to change the sequence of instruction execution
which controls the flow offprogram logic.

g
in
There are three types of branching instructions are,

er
() Jump instructions.

e
(i) Call instructions.

in
(i) Return instructions.

ng
2.6.1 CALL Instructions fE
a Definition:
O
The CALL instruction is a control transfer instruction which is used to call a
subroutine. Subroutines are often used to perform tasks that need to be
g e

performed frequently. This makes a program more structured in addition to

le

saving the memory space.

ol

Function :Transfers control to a subroutine.

C

Flags : None
u

are two types of call

In the 8051, depending upon the target address there
ad

instructions:
iln

) LCALL (long call)

m

(i) ACALL (absolute call)

Ta

Deseription Byte Cycle

Mnemonic
2 2
ACALL addr11 Absolute subroutine call
3 2
LCALL addr16 Long subroutine call

(1) ACALL 11- bit address

Mnemonic : ACALL addr11.
<br>

Page 90 of 440

2.42 Embedded Systems and 10T Design

ACALL Stands for *absolute call ". It calls subroutines with a target address tht
must be within 2K bytes of the current Program Counter (PC).
It is a 2-byte instruction, in which 5 bits are used for the opcode and the
remaining 11 bits are used for the target subroutine address. A 11-bit addres
limits the range to 2K bytes.

g
in
(2) LCALL 16-bit address

er
:
Mnemonic LCALL addr16

e
LCALL can be used to call subroutines located anywhere within the 64K byte

in
address space of the8051.

ng
When a subroutine is called, the PC register (yhich has the address of the
fE
instructjon afer the ACALI) is pushed onto the stack, and the Stack Pointer (SE)
is incremented by 2.
O
+
(SP) (SP) 2.
g e

Then the program counter is loaded with the new address and control is
le

transferred to the subroutine. After finishing the execution

of the subroutine,
ol

RET is executed and PC is popped off the stack, which returns

the control to the
C

instruction after the CALL.

LCALL is a 3-byte instruction, in which one is the opcode,
u

and the other tvo

are
ad

bytes the 16-bit address of the target subroutine.

iln

2.6.2 Return Instruction

m

Mnemonic Description Byte Cycle

Ta

RET Return from subroutine 1

2
RETI Return from interrupt

(1) RET

Mnemonic : RET
Function : Return from
subroutine
: None
Flags
<br>

Page 91 of 440

8051 Instruction set

2.43
This instruction is used to return from a
subroutine which is previously entered
by instructions LCALL or ACALL.
, The top
two bytes of the stack are popped into the program
counter (PC) and
program execution continuous at new
this address. The stack pointer (SP) is
2.
decremented by

g
in
(SP) -(SP)- 2.

er
(2) RETI

e
in
Mnemonic :
RETI

ng
Function : Return from interrupt
:
Flags None fE
This is used at the end of an interrupt service routine (interrupt handler). The top
O
two bytes of the stack are popped into the program counter and program
execution continuous at this new address. Then, the program counter (PC) and
g e

the stack pointer (SP) is decremented by 2.

le

(PC) +(PC) -2
ol

(SP) - (SP) - 2
C
u

2.6.3 JUMP Instructions

ad

The jump instruction transfers the program

sequence to the memory address
iln

given in the operand based on the specified

flag.
m

JUMP instructions are of two types,

Ta

) Unconditional Jump Instructions

Transfers the program

sequence to the described memory address.

(i) Conditional Jump Instructions

sequence to the described memory address only if
Transfers the program
the condition is satisfied.
<br>

Page 92 of 440

Embedded Systems and 1OT Design

2.44
Description Byte Cycle
Mnemonic Operand
2 2
AJMP addrl1 Absolute jump

Long jump 3 2
LJMP addr16

g
in
rel Short jump (relative addr.) 2 2
SJMP

er
Jump indirect relative to the 2
JMP @A+ DPTR

e
DPTR

in
JZ rel Jump if accumulator is zero. 2 2

ng
Jump if accumulator is not
JNZ rel 2 2
zero. fE
JC rel Jump if carry flag is set 2 2
O
JNC rel Jump if carry flag is not set 2 2
eg

JB bit, rel Jump if direct bit is set 3 2

le

JNB bit, rel Jump if direct bit is not set

ol

3 2
C

JBC bit, rel Jump if direct bit is set and

clear bit 3 2
u

CJNE Compare direct byte to A and

ad

A, direct, rel
jump if not equal 3

Compare immediate to A and

iln

CJNE A, #data, rel

jump if not equal 3 2
m

CJNE Rn, #data, rel Compare immediate to register

and jump if not equal
Ta

3 2
CJNE @Ri, #data, rel Compare immediate to ind.
and jump if not equal 3 2
DJNZ Decrement register and
Rn, rel jump
if not zero. 2 2
Decrement direct byte
DJNZ direct, rel and
jump if not zero 3 2
<br>

Page 93 of 440

(1) AJMP target 2.45!

address: Unconditional
Mnemonic AJMP addrl1
Function : Absolute jump
Flags : None
AJMP stands for
"absolute jump". It transfers program

g
address unconditionally. exccution to the target
The target address for this

in
2K bytes of program memory. instuction must be within

er
(2) UMP 16– bit addr: Unconditional

e
Mnemonic :

in
LJMP addr16

ng
Function Transfers control unconditionally to a new
• LJMP stands address
for "long jump" which is a 3-byte instruction.
fE The first byte is
the opcode and the next o
bytes are the target address.
O
LJMP is uscd to jump to any zddress
location within the 64K byte cude space
of the 80S1.
g e

(3) SJMP8- bit addr: Unconditional

le

Mnemonic :
SJMP rel
ol

Function : Transfers control unconditionally to a new

C

adiress
SJMP stands for "short junmp" which is a
2- byte instruction. The firstbyte is
u
ad

the opcode and the second byte is the signed number displacement, whict is
added to the PC (program counter) of the instruction following the SJMP to
iln

get the target address.

m

This address is often referred to as a relative (rel) address since ths target
-
Ta

address is 128 to + 127 bytes relative to the program counter (PC).

(9) JMP @A+ DPTR : Unconditional
Mnemonic :
JMP aA+ DPTR
Function : Junnp indireet

Flags :None
<br>

Page 94 of 440

2.46| Embedded Systems and TOT Deslo

The JMP instruction is an unconditional jump to a target address which

provided by the total sum of register A and the DPTR register.

(5) JZ target: Conditional jump

: JZ rel
Mnemonic

g
Function
:
Jump ifA =0

in
er
Flags : None

e
This instruction examines the contents of the accumulator and jumps if it h

in
value 0.

ng
(6) JNC target:Conditional jump
Mnemonic :
JNCrel fE
Function : Jump if no carry (CY = 0)
O
Flags : None
e

This instruction examines the CY flag and

g

if it is zero it will jump to the targ

le

address.
ol

(7) JC target: Conditional jump.

C

Mnemonic :
JC rel
u

Function : Jump carry if CY =1

ad

Flags None
iln

This instruction examines the

CY flag; if it is high, it will jump to the targ
m

address.
Ta

(8) JB bit, target & JNB bit, target

(i) JB bit, target : Conditional
Mnemonic : JB bit, rel
Function : Jump if bit set (= 1)
Flags : None
<br>

Page 95 of 440

S1nstrüction set
2.47
(ti) JNB bit, target: Conditional
-

Mnemonic : JNB
bit, rel
Function Jump if bit not set
(0)
Flags :None
These instructions are used to

g
monitor a given bit and jump to a target
address

in
ifa given or
bit is lhigh low.

er
Inthe JB, when the bit is high it will jump, while for JNB when the bit
is low
it will jump.

e
in
(9)CJNE dest-byte, source-byte,target: Conditional
and Short Jump

ng
Function Compare and jump if not equal
Flags :CY
fE
O
The magnitudes of the source byte and destination byte are compared.
If they
are not equal, it jumps to the target address.
g e

This instruction supports four addressing modes. In two of them, A is the

le

destination.
ol

(i) Immediate Mode:

C

:
Mnemonic CJNE A, #data, target
u
ad

CJNE A, #data, rél

Compares immediate data to the accumulator and jumps if not equal.
iln

Example : CJNE A,
#96, NEXT ; Jump if A isnot 96
m

(ii) Direct
Ta

Mode:
Mnemonic -: CJNE A, direct, target

CJNE A, direct, rel.

Compares direct byte to the accumulator and jumps if not equal.

Example : CJNE A, 40, NEXT

;
Jump if
A
NOT = with the
value held by RAM location 40H
<br>

Page 96 of 440

2.48 Embedded Systems and I0T Design

(ii) Register Mode:

Any register R0 -R7 can be the destination.
Mnemonic
:
CJNE Rn, #data, target

CJNE Rn, #data, rel

g
not equal.
Compares immediate data to the register and jumps if

in
er
: is not 70
Example: CJNE R5, #70, NEXT Jump ifRS

e
- Indirect Mode:

in
(iv) Register
is held by register ROor R1.
Any RAM location can be the destination which

ng
Mnemonic CJNE. @ Ri, #data, target
fE
CJNE @ Ri, #data, rel
O
Compares immediate data to indirect register and jumps if not equal.
g e

Example:
le

CJNE @RI, #80, NEXT ; Jump if RAM location whose address is held
ol

;
by R1 is not equal to 80
C

(10) DJNZ byte, target :Short Jump

u

Decrement and jump if not zero

ad

:
Function
: None
Flags
iln

In this instruction a byte is decremented, and if the result is not zero it wil
m

jump to the target address. This instruction supports following two addressiny
Ta

modes (or) formats:

(i) Register Mode:
Mnemonic :
DJNZ Rn, target (where n = 0 to 7)
DJNZ Rn, rel
Decrements register
and jumps if not 0.
Example : DJNZ R3, HERE
<br>

Page 97 of 440

8051 Instruction set

|2.49|
(i1) Direct Mode:
Mnemonic : DJNZ direct, target
DJNZ direct, rel
Decrements direct byte and jumps if not 0.

g
(11) NOP

in
Mnemonic : NOP

er
Function : No operation

e
Flags :
None

in
This performs no operation and execution continues with the next instruction. It

ng
is
sometimes used for timing delays to waste clock cycles.
fE
This instruction only updates the PC to point the next instruction following
NOP.
O

2.7 TWO MARKS QUESTIONS AND ANSWERS

g e

1. List the different types of 8051 microcontroller. [APRMAY -2010]

le

[OR]
ol

List the vaious instructions available in 8051 microcontroller.

C

APRMAY-2021]
u

of 8051 microcontroller can be classified into five diferent

ad

The instructions
groups as follows:
iln

(i) Data transfer instructions.

m

(ii) Arithmetic instructions.

Ta

(i) Logical instructions.

(iv) Program branch instructions.

() Boolean or Bit manipulation instructions.

2. Define mnemonic.
In computer assembler (or assembly) language, a mnemonic is an abbreviation
for an operation which specifies the type of operation
to be performed and they
<br>

Page 98 of 440

„50 Embedded Systems and 10T Design

are translated by the assembler. All mnemonics of the instruction are of one byte

size.
3. Write the format of instruction.
The format of instruction is as follows:

g
in
MNEMONIC DESTINATION OPERAND, SOURCE OPERAND

er
4. What is the function of
datatransfer instructions?

e
The data transfer instructions are associated with transfer of data between

in
registers or external program memory or external data memory. These

ng
instructions are used to copy the content of source operand to the destination
operand. fE
5. State any four data transfer instructions and their function.
[NOVDEC- 2018]
O
(i) MOV
e

Move a byte from the source location to

the destination.
g
le

(ii) MOVC
ol

Move code byte to accumulator.

C

(i) MOVX
Move data to/from external memory.
u
ad

(iv) PUSH
iln

Push value onto stack.

(vii) POP
m

Pop values from stack.

Ta

6. What is the operation

carried out when
MOVC A, @A+DPTR?
805l executes the instiuction

[NOVDEC-2007]
Mnemonic
Description Byte
MOVCA, @A +DPTR Cycle
Move code byte
relative
DPTR to accumulator to 1
2
<br>

Page 99 of 440

8051- Iistruction set

2.51
Function: Move code byte
Flags: None
Operation: (A)¢- ((A) + (DPTR)
This instruction moves a byte of data that
is located in program (code)

g
ROM into register A. This allows us to put strings
of data, such as look

in
up table elements, in the code space
and read them into the CPU.

er
The address of the desired byte in the code space (on-chip
ROM) is

e
formed by adding the original value of the accumulator to the 16-bit

in
DPTR register.

ng
Example:

Let (DPTR) = 1000H, (A) = 8H

fE
O
A + DPTR 8H + 1000H, the contents of memory location (1008H) = 22H.
After execution of this instruction (A) = 22H.
g e

7. Specify the difference between MOV andMOVX instructions.

le

[NOVIDEC-2018]
ol

(i) MOV Instructions

C

<src - byte>
Mnemonic: MOV <dest- byte>,
u
ad

Function: Move byte variable.

: None.
Flags
iln

source location to the destination.

This instruction copies a byte from the
m

(ii) MOVX Instructions:

Ta

Mnemonic: MOVX <dest-byte>, <source-byte>

Function: Move external
Flags: None.
external memory and register A. The
This instruction transfers data between space.
64 K bytes of data space in addition to the 64 K bytes of code
8051 has
<br>

Page 100 of 440

2.52| Embedded Systems and 10T Design

us to
This data space must be connected externally and this instruction allows
access externally connected memory.
RIinstruction is executed.
8. Write the operation carried out when MOVXA, @
[NOVIDEC -2022]

g
or
The 8-bit address of external memory is held by RO R1.

in
MOVX A,@ Ri ; where
i.=0 or 1

er
memory whose 8-bit address is
This instruction moves a byte from external

e
pointed to by the register Ri into the accumulator.

in
ng
9. What is arithnetic instruction?
as addition,
Arithmetic instructions perform several basic operations such
fE
subtraction, division, multiplication etc. After execution, the result is stored in
the first operand.
O
10. Write the function of logical instructions.
e

Logical instructions can perform logical operations upon coresponding bits of

g

two registers like AND, OR, XOR, NOT, Rotate, Clear and Swap. They are
le

performed on bytes of data on a bit-by-bit basis. After execution, the result is

ol

stored in the first operand.

C

14 What is the function of

SWAP A? [NOVDEC -2006 & 10, APRMAY -20177
u

: SWAP A
Mnemonic
ad

:
Function Swap nibbles within the accumulator
iln

:
Flags None

:(D3 - D0) > (D7- D4)

m

Operation
Ta

D7 D4 D3 DO

Higher Lower
nibble nibble
<br>

Page 10l of 440

8051 Instruction set

2.53
This SWAP instruction interchanges
the lower nibble (D3- D0) with the upper
nibble (D7- D4) inside register A.

Example:

MOV. A, #59H ;A= 59H (0101 1001 in binary)

g
SWAP A ;A=95H (10010101 in binary)

in
124What is meant by bit oriented instructions?

er
[APRMAY-2017 & NOVDEC-2019]

e
The bit oriented instruction is also

in
called as Boolean or Bit manipulation
instructions. It is similar to logic instructions

ng
which perform the logic operations.
The difference is that these are performed upon
single bits.
13. Define branch instructions.
fE
.Thebranch instructions are used to change the sequence of instruction execution
O
which controls the flow of program logic. There are three types
of branching
e

instructions are,
g

i) Jump instructions.
le

(ii) Call instructions.

ol

(ii) Return instructions.

C

l4. Write the functions of CALL instruction.

u

The CALL instruction is a control transfer instruction which is used to call a

ad

subroutine. Subroutines are often used to perform tasks that need to be performed
iln

frequently. This makes a program more structured in addition to saving the

memory space.
m

Function : Transfers control to a subroutine.

Ta

Flags :
None
15. Define subroutine. [NOVIDEC- 2018]
Subroutines are often used to perform tasks that need to be performed frequently.
This makes a program more structured in addition to saving the memory space.
16. What is the function of
RET instruction of 8051? [NOVDEC-2010]
Mnemonic : RET
Function : Return from subroutine
<br>

Page 102 of 440

Embedded Systems and I0T Design

2.54
: None
Flags
This instruction is used to return from a
subroutine which is previouslv
entered by instructions LCALL or ACALL.
The top two bytes of the stack are popped into the program counter
(PC) and

g
program execution continuous at this new
address. The stack pointer (SP) is

in
decremented by 2.

er
(SP) -(SP) -2.

e
in
What is the difference between RET and RETI
instruction in 8051?

ng
[APRIMAY -2008 & 2011]
[OR] fE
Differentiate RET and RETI instructions.
[NOVDEC-2021]
O
(1) RET
e

Mnemonic : RET
g

Function : Return from subroutine

le

Flags : None
ol

This instruction is used to return

C

from a subroutine which

entered by instructions LCALL or ACALL. is previously
u

The top two bytes of the stack are

popped into the program counter
ad

program execution (PC) and

continuous at this new address.
The stack pointer (SP) is
decremented by 2.
iln

(SP) - (SP)-2.
m

(2) RETI
Ta

Mnemonic :
RETI
Function :
Return from interrupt
Flags : None
This is used at the end an interrupt
of service routine (interrupt
two bytes of the stack are handler). The top
popped into the program counter
execution continuous at this new and progra
address. Then, the program counter
the stack pointer (SP) is decremented by 2. (PC) and
<br>

Page 103 of 440

8051Instruction set
|2.55

(PC) +(PC)-2
18. Write the functions
(SP) - (SP)-2
of jump instruction.
The jump instruction transfers
the program sequcnce to
the memory adaress

g
given in the operand based on the specified
flag. JUMP instructions are of two

in
types,

er
(i) Unconditional Jump Instructions

e
Transfers the program sequence to the described memory

in
address.
(ii) Conditional Jump Instructions

ng
Transfers the program sequence to the described memory
address only if the
condition is satisfied.
fE
19, Differentiate CALL instruction from JUMP instruction.
O
[NOVDEC-2017]
A CALL instruction is used to call a subroutinc,
e

while JUMP instruction

program
g

updates the counter value and makes it point to another location inside
le

the program.
ol

20. List the DJNZ instructions of Intel 8051 microcontroller. [NOVDEC-2022/

C

[OR]
u

Give the format and functionof the instruction DJNZ for 80s1.
ad

NOVIDEC-2019)
iln

DJNZ byte, target :Short Jump

m

Function :
Decrement and jump if not zero
Ta

Flags : None
In this instruction a byte is decrementcd, and if the result is not zero it will
jump to the target address. This instruction supports following two
addressing modes (or) formats:
0) Register Mode:
Mnemonic : DJNZ Rn,targct (where n = 0 to 7)
DJNZ Rn, rel
<br>

Page 104 of 440

Embedded Systems and 10T Design

|2.56

Decrements register and jumps if not 0.

Example .: DJNZ R3, HERE

(ii) Direct Mode:

g
Mnemonic DJNZ direct, target

in
DJNZ direct, rel

er
Decrements direct byte and jumps if not 0.

e
in
2.8 REVIEW QUESTIONS

ng
1. With necessary examples, discuss the instruction set of the 8051.
fENOVDEC- 2008, NOVDEC - 2022]
O
2. Explain the different types of instructions set used in 8051 microcontroller.
e

[NOVDEC - 2017|
g

3. Explain the various bit manipulation instructions

in 8051 with examples.
le

[NOVIDEC - 2017
ol

4. Explain the function of DJNZ

instruction.
C

[APRMAY-2009 & 2017,

u

5. Differentiate between
NOVDEC-2019)
ad

the following instructions

clearly.
() PUSH and POP.
iln

(ii) CALL and JUMP.

m

(ii) ADD and ADDC.

Ta

[APR/MAY - 2019]J

DO
<br>

Page 105 of 440

UNIT-I'
Chapter 3

g
in
er
PROGRAM AND DATA MEMORY

e
in
3.1 PROGRAM AND DATA MEMORY: 8051 MICROCONTROLLER

ng
MEMORY ORGANIZATION: INTERNAL AND EXTERNAL
MEMORIES fE
O
3.1.1 Introduction
The 8051microcontroller memory is separated as program menory (ROM) and
e

data memory (RM) on the same chip (1C), whereas a microprocessor has to be
g
le

externally interface with the memory modules.

ol

Memory
C

Unit
u

Data
ad

Memory
(RAM)
iln
m

Program
Memory
Ta

(ROM)

menmory unit
Fig 3.1 Microcontroller
8051 microcontroller has both internal ROM and internal RAM. If the internal
memory is inadequate, you can add external memory using the suitable circuits.

8051 has 4KB o-chip program memory (ROM) and 64 KB external

program
memory. It also has .I28 bytes of on-chip data memory (RAM) and 64 KB
external data memory.
<br>

Page 106 of 440

3.2 Embedded Systems and 10T Design

3.1.2 Program Memory (ROM) of 8051 Microcontroller

a Definition:
are stored in the
In 8051 microcontroller, the code or instructions be executed
to
The
program memory, which is also called as the ROM of the microcontroller.

g
in
ROM.
original 8-bit 8051 microcontroller by Intel has 4KB of internal

er
any internal
Some variants of 8051 like the 8031 and 8032 series doesn't have

e
memory with instructions
ROM and must be interfaced with an external program

in
loaded in it.

ng
Almost all modern 8051 microcontrollers, like 8052 series, have 8KB of interal
fE
program memory (ROM) in the form of flash memory and provides an option of
reprogramming the memory.
O
g e
le

CPU
ol

(ALU, CU)
C
u

Program
ad

Memory
(ROM)
iln

UUU
m
Ta

Fig 3.2 8051 progran memory in microcontroller

4 When an External Access (EA =1) pin is HIGH, then the CPU first fetches the
instructions from the 4KB of internal (on-chip)
ROM in the address rang
of 0000H to 0FFFH and if the memory addresses
exceed this linl
then the instructions are fetched from the external
ROM in the address range 0
1000H to FFFFH.
<br>

Page 107 of 440

Program and Data Memory

|3.3
+5V FFFFH
4
External
EA= 1
Program
Memory
(ROM)
64KB
1000H

g
in
OFFFH
Internal

er
Program
Memory

e
(ROM)
4KB

in
0000H

ng
Fig 3.3 Using both internal and external program memory witlh 8051
When all the instructions are fetch only from an external program memory
fE
(external ROM). Then, the EA pin must be connected to GND (EA= 0) and the
O
memory addresses of the external ROM will be from 0000H to FFFFH.
e

FFFFH
g

External
le

EA=0 Program
Memory
ol

(ROM)
64KB
C

8051 Microcontroller 0000H

u

nternal
ad

Program
Memory
iln

(ROM)
m

Fig 3.4 Using only external program memory with 8051

Ta

3.1.3 Data Memory (RAM)

A Definition:
The data memory or RAM ofthe 8051 microcontroller stores temporary data and
intermediate results that are generated and used during the normal operation of
lhe microcontroller. Original Intel's 8051 microcontroller had 128B of internal
RAM. Almost allmodern variants of 8051 microcontroller have 256B of RAM.
<br>

Page 108 of 440

Embedded Systems and 10T Design

3.4
RAM Memory
(1) Internal Data Memory: Internal RAM Organization:
Allocation in the 8051
are assigned addresses 00 to
There are 128 bytes of RAM in the 8051 which
bytes
7FH. They can be accessed directly as memory locations and these 128

g
are divided into three different groups as follows:

in
(i) Register Banks.

er
(ii) Bit – addressable RAM, and

e
in
(ii) General purpose RAM (or) Registers (or) Scratch Pad RAM.

ng
7F

fE
Scratch Pad RAM
30
O
2F
Bit-Addressable RAM
e

20
g

1F
le

Register Bank 3
co
18
ol

17
C

Register Bank 2
10
el
u

OF
ad

Register Bank 1 (Stack)

08
iln

07
Register Bank 0
m

00
Ta

Fig 3.5 RAM allocation

in the 8051
(A) 8051 Register Banks (Working
In the 128B
Registers)
of RAM (from 00H to
addresses 00H 7FH), the first 32B
to 1FH consists
of 32
ie., memory from
four banks with working registers that are
8 registers organized as
Bank3 which are in each Bank such as
selected by the Bank 0., Bank1. Bank2,
PSW (Program and
Status Word) register.
<br>

Page 109 of 440

Program and Data Memory

3.5|
Bank 0 Bank 1
Bank 2 Bank 3
7 R7 F R7 17 R7 1F R7
6 R6 E R6 16 R6 1E
R5 D
R6
5 R5 15 R5 1D
R4 R5
4 C R4 14 R4 1C R4
R3

g
3 B
R3 13 R3 1B R3

in
2 R2 A R2 12 R2 1A R2

er
R1 R1 11 R1 19 R1
RO 8 RO

e
10 RO 18 R0

in
Fig 3.6 8051 Register Banks and their RAM addresses

ng
By default, the 8051 microcontroller is
powered up with register bank 0.
Based on the possible combinations of bits RS1 and RSO
fE of PSW, the register
bank is changed accordingly, i.e., if RS1 and RS0 are 0,
then the Bank 0 is
O
selected. Similarly, Bankl, 2&3 are selected as per the values
of RS1and RSO
as shown in Table 3.1.
ge

RS1 (PSW.4) RSO (PSW.3) Register Bank Address

le

0 00H – 07H.
ol
C

1 1
08H– 0FH
u

1
10H-17H
ad

1 1 3
18H- 1FH
iln

Table 3.lPSW bits bank selection

o
The RSI.and RS2 bits are often referred to as PSW.4 and PSW.3 since thev
m

can be accessed by the bit-addressable instructions SETB and CLR., For

Ta

example, “ SETB PSW.3 " will make PSW.3 =l and select bank register 1.
These register banks are used to process the data when the microcontroller is
programmed.
(B)BitByte Addressable
-
The next 16B of the RAM from location 20H to 2FH are bit addressable
read/write memory. There are totally 128 (16 x 8) bits that can be addressed
<br>

Page 110 of 440

3.6| Embedded Systems and 1OT Design

individually using 00H to 7FH or 8 bits may form any byte address from 20H
to 2FH.
Example: 32H is the bit 2 of the internal RAM location 26H

(C) Registers of 8051 Microcontroller: General Purpose RAM

g
or subtraction, then these
If we perform any operation whether addition

in
operations are unable to be performed directly in the memory, and therefore,

er
are performed by using the registers.

e
The RAM arca above bit addressable area from 30H to 7FH is called general

in
purpose RAM which is addressable as byte.

ng
3.1.4 Interfacing External Memory with 8051 Microcontroller
fE
4 External memory interfacing in 80S1 microcontroller involves connecting
O
external memory devices such as RAM and ROM t0 the microcontroller to
provide an additional memory space.
g e

This allows the microcontroller to execute larger and more complex programs,
le

store more data, and perform more complex operations.

ol

External memory interfacing typically involves connecting the memory devices

C

to the microcontroller through a data bus and an address bus. The data bus is used
to transfer the data between the microcontroller and
u

the memory device, while

ad

the address bus is used to select a specific memory

location in the memory
device.
iln

To interface with external memory, the 8051

microcontroller uses dedicated pins
m

such as ALE (Address Latch Enable), PSEN

(Program Store Enable), and RD
Ta

(Read) and WR (Write) signals. These signals are

used to control the flow of data
between the microcontroller and an
external memory device.
Port 0 is used as a multiplexed address/bus, as
shown in Fig 3.7. In the initial
cycle, it provides a lower order 1
8-bit address, and later it is
The external latch and the ALE signal used as a data bus.
provided by the 8051 are used to
address. latch the
8-bit

&Port2 may be used as a higher byte of the address bus.

<br>

Page 11l of 440

Program and Data Memory 3.7

P1 DO
PO
D7
EA

g
in
8051 ROM/EPROM
A0

er
CLK A7
ALE

e
P3

in
A8
PA

ng
PSEN A15
OE
fE
Fig 3.7Accessing external program
O
4 In Fig 3.7, the PSEN signal is used to activate an output enable signal of the
external ROM/EPROM.
g e
le

3.2 STACKS
ol

3.2.1 Introduction
C

a Definition:
u
ad

The stack is a section of internal RAM used by the CPUto store the information
temporarily. This information could be a data or an address. The CPU needs this
iln

storage area since there is only limited umber ofregisters.

m

Stack Pointer (SP):

Ta

f the stack is a section of RAM, then there must be registers inside the CPUto
point to it. The register used to access the stack is called the Stack Pointer (SP)
register.

The stack pointer is a small register used to point the stack. When we push
Something into the stack memory, then the stack pointer gets increased.

i
<br>

Page 112 of 440

3.8 Embedded Systems and 1OT Desig,

OFH

Stack
Bank -1 Space
(stack)

g
08H

in
Stack 07H
Pointer

er
Bank- 0 Stack

e
Memory

in
0OH

ng
Fig 3.8 Stack memory allocation in 8051 microcontroller
fE
The SP in the 8051 is 8-bits wide, and it can take a value of 00H to FFH. When
thé 8051 is initialized, the SP register contains the value 07H, by default, as it is
O
shown in the Fig 3.8. This means that the RAM location 08H is the first location
e

used for the stack.

g
le

3.2.2 PUSH and POP Operation:

ol

The storing operation of a CPUregister in the stack is known as PUSH, and.

C

getting the contents from the stack back into a CPUregister is called
POP.
u

6 5
ad
iln
m

5 5 5
Empty Stack
Ta

Push 5 Push 6 Pop 6 Pop 5

Fig 3.9 PUSH and POP operations
in stack
(1) PUSH Operation: Pushing onto the Stack
In the 8051 the SP points to
the last used location of the stack.
executed, the contents of When PUSH P
the register are saved on the stack
incremented by 1. To push the and SPP
registers onto the stack, we must use
addresses. their RA

4
<br>

Page 113 of 440

Program and Data Memory

3.9
12) POP Operation: Popping from the
Stack
Popping the contents of the stack back intoa
given register is the opposite to the
process of pushing.
With every pop operation, the top byte the stack is
to the register specified by the instruction
of copied
and the stack pointer gets decremented
by once.

g
in
3.2.3 Other Instructions

er
The other instructions of the 8051 that affect
the stack and the stack pointer are

e
ACALL, LCALL, RET, and RETI.

in
The CPUalso uses the stack to save the address of an instruction just below the

ng
CALL instruction because thè CPU knows where to resume when it returns
fE from
the called subroutine.
O
* The stack pointer can be initialized to any internal RAM address by the
e

programmer, by writing the required address in the SP SFR address 81H.

g
le

3.3 8051 INTERRUPTS (OR) INTERRUPTS IN 8051

ol

MICROcONTROLLER
C

3.3.1 Introduction
u

4 An interrupt is an external or internal event that interrupts the microcontroller to

ad

inform that a
device needs its service. A single microcontroller can serve several
iln

devices by two ways:

m

(i) Interrupts:
Ta

Whenever any device needs its service, then the device notifies the
microcontroller by sending it an interrupt signal.
it
After receiving an interrupt signal, the microcontroller interrupts whatever
is doing and serves the device.

The program which is associated with the interrupt is called the Interrupt
Service Routine (JSR) or Interrupt Handler.
<br>

Page 114 of 440

|3.10| Embedded Systems and 1OT Design

a Definition:
some
Interrupt is a sub-routine calls which is given to the microcontroller. When
other program with high priority is requesting for acquire the system buses than
an interrupt occur in current running program.

g
Interrupts provide a method to postpone or. delay the current process, thereby

in
performs a sub-routine task and then restart the standard program again.

e er
(ii) Polling

in
The microcontroller continuously monitors the status of a given device.

ng
When the conditions met, it performs the service. After that, it moves on in
order to monitor the next device until everyone is serviced.
fE
Polling can monitor the status of several devices and serve each of them as
O
certain conditions are met.
e

Drawback:
g
le

The polling method is not efficient, since it wastes much

of the microcontroller 's
time by polling the devices which do 'not need service.
ol
C

Advantages
u

The advantages of interrupts in the microcontrollers are,

ad

i) It can serve many devices but not all at the same time.
Each device can get the attention
iln

of themicrocontroller based on the

assigned priority.
m

For the polling method, it is not possible to assign

priority since it checks
Ta

all devices in a round-robin fashion.

(i1) The microcontroller can
also ignore (mask) a device request for service,
which is not possible for the polling method.

3.3.2 Interrupt Service Routine (ISR)

For every interrupt, there must be an Interrupt Service
Routine (ISR), or interrupt
handler. When an interrupt is raised, then the
microcontroller runs an interrupt
service routine.
<br>

Page 115 of 440

Program and Data Memory

3.11|
For every interrupt, there
isa fixed location in memory that holds the address of
its ISR.
The group of menory locations which set separately to hold the addresses of
ISRs is called lnterrupt Vector Table.
Table 3.2 shows the Interrupt Vector table
for 8051.

g
Interrupt vector address- is the address where the controller jumps

in
&
after the
interrupt to serve the ISR.

e er
ROM location/

in
Interrupt Interrupt Pin Flag Clearing
Vector Address

ng
Reset 0000 H 9 Auto
External hardware
fE
interrupt 0 (INTO)
0003H P3.2(12) Auto
O
Timer O interrupt (TFO) 000BH Auto
e

External hardware
g

0013H P3.2(13) Auto

interrupt1 (INIT1)
le

Timer 1
interrupt (TF1) 001BH Auto
ol

Serial COM interrupt Programmer

C

0023H
(RI and TI) clears it
u

Table 3.2 Interrupt Service Routine (1SR): Interrupt Vector Tabl for the 80S1
ad

3.3.3 Steps in Executing anInterrupt

iln

for the activation of an

The following steps are used by the microcontroller
m

interrupt:
saves the address of the
Ta

) It finishes the instruction which is executing and

next (PC) on the stack.
interrupts internally, not on the
(1) It also saves the current status of all the
stack.
vector
It jumps to a fixed location in memory which is called the interrupt
(i)
ISR.
table, that holds the address of the
vector
the ISR from the interrupt
(iv) The microcontroller gets the address of
table and jumps to it.
<br>

Page 116 of 440

|3.12 Embedded Systems and IOT Design

the last
It starts to execute the interrupt service subroutine until itreaches
instruction of the subroutine which is RETI (return from interrupt).
returns to the
(vi) Afer executing the RETI instruction, then the microcontroller
place where it gets interrupted.

First, it gets the program counter (PC) address

from the stack by

g
in
popping the top two bytes of the stack into the PC.

er
Then it starts to execute from that address.

e
in
3.3.4 Six Interrupts in the 8051: Vectored Interrupts

ng
as
The six interrupts in the 8051 are follows:
(0) Reset fE
It is the power-up reset which is the highest priority interrupt. When the reset pin
O
isactivated, then the 8051 jumps to address location 0000.
e

(i) Internal interrupt: Timer Interrupt

g

8051 microcontroller has two internal interrupts namely Tiner 0 Interrupt

le

(TFO) and 7Timer 1 Interupt (TF1). Memory locations 000BH and 001BH
ol

in the interrupt vector table belong to Timer 0 and Timer 1, respectively.

C

Whenever timer overflows, timer overflow flags (TFOrTF1) are set. Then the
u

microcontroller jumps to their vector address to serve the interrupt.

ad

(ii) External Hardware Interrupt

iln

Microcontroller 8051 is consisting of two external hardware interrupts: INTO

and INTI. These interrupts are enabled at pin 12 (P3.2) and pin 13 (P 3.3) in
m

port 3 which can be level triggered (interrupt occur on highlow-level

Ta

detection) or edge triggered (interrupt occur risinglfalling edge detection).

Memory locations 0003 and 0013H in the interrupt vector table are
assigned INTO and INTI, respectively.

(iv) Serial Interrupt

Serial communication has a single interrupt (T1/R1l)
that belongs to both receive
and transmit. The interrupt vector table 0023H belongs to
this interrupt.
<br>

Page 117 of 440

Program and Data Memory 3.13

Table 3.2 gives the vector address of six interrupts available in 8051
microcontroller.
3.3.5 Enabling and Disabling an Interrupt
After reset, all the interrupts are disabled (masked) that is, none will be

g
responded to by the microcontroller if they are activated. The interrupts must be

in
enabled by software in order for the microcontroller to respond to them.

er
* Interrupt Enable (E) is a register that is responsible for enabling (unmasking)

e
and disabling (masking) the interrupts.

in
D7 6 3 DO

ng
EA ET2 ES ETI EX1 ETO EX0
fE
Fig 3.10 IE(Anterrupt Enable) register
O
EA IE.7 It disables all interrupts.= When EA =0, no interrupt will be
acknowledged and EA 1
énables the interrupt individually
g e

IE.6 Reserved for future use

le

ET2 IE.5 nables or disables timer 2 overflow interrupt (8052 only)

ol

ES IE.4 Enables (ES = 1) or disables (ES =0) the serial port

C

interrupt.
u

Enables (ETI =1) or disables (ET1 = 0) Timer overflow

1
ETI IE.3
ad

interrupt
Enables (EX1 =1)or disables (EX] =0)external interrupt 1.
iln

EXI IE.2
ETO Enables (ETO= 1) or disables (ETO = 0) Timer 0 overflow
m

IE.1
interrupt
Ta

EX0 IE.0 Enables (EX0 = 1)or disables (EX0 = 0) external interrupt 0

loenable an interrupt, we take the following steps:

() BitD7 of the IE register (EA) must be set to high to allow the rest ofregister
totake effect.
(ii) If EA = 1,. interrupts are enabled and will be responded to if their
corresponding bits in IE are high. IfEA = 0, no interrupt will be responded
to, even if the associated bit in the IE register is high.
<br>

Page 118 of 440

Embedded Systems and 10T Design

3.14

3.3.6 Interrupt Priority in the 8051/52

up, the priorities are assigned. The priority scheme is
When the 8051-is powered
sequence in which the 8051 polls the interrupts in
nothing but an internal polling
the sequence listed and responds accordingly.

g
in
a Interrupt Priority (|P):
by assigning a higher priority
to

er
We can alter the sequence of interrupt priority
any one of the interrupts by programming a register
called Interrupt Priority

e
in
(IP).
any of the interrupts, we make the corresponding bit

ng
To give a higher priority to
or more interrupt bits in the IP register are set
to
in the IP register high. When two fE
high and these interrupts have a higher priority than others,
they are serviced
according to the sequence of Table 3.3.
O

Highest To Lowest Priority

g e

External Interrupt 0 (INTO)

le

Timer Interrupt 0 (TFO)

ol
C

External Interrupt 1
(INTI)
Timer Interrupt
u

1 (TF1)
ad

Serial Communication (RI+ TI)

iln

Table 3.3 8051/52 Interrupt priority upon reset

m

(1)InterruptPriority (P) Register

Ta

8051has an interrupt priority register to assign priority to interrupts.

D7 6 5 4 3 2 DO

PT2 PS PT1 PX1 PTO PX0

Symbol Pin Purpose

IP.7 Reserved bit
IP.6 Reserved bit
<br>

Page 119 of 440

Program and Data Memory

3.15
PT2 IP.5 Timer 2 interrupt Priority bit (8052
only)
PS IP.4 Serial port interrupt priority bit
..
1=High priority
0=Low priority

g
PT1

in
IP.3 Timerl interrupt priority bit
1= High priority

er
0=Low priority

e
PX1 IP.2 External interrupt 1 priority bit

in
1=High priority

ng
0= Low priority
PTO IP.1 fE
Timer O interrupt priority bit
1=High priority
O
0=Low priority
e

PX0 IP.0 External interrupt 0priority bit

g

1= High priority
le

0-Low priority
ol

Fig 3.11 IP register

C

3.4 PROoGRAMMIG 8051 TIMERS: TIMERs

u
ad

3.4.1 Introduction
iln

The 8051 has two timers/counters. They can be used either as timers in order to
generate a tme delay or as event counters to count events happening outside the
m

microcontroller.
Ta

a Basic Registers of Timer:

Both Timer 0 and Timer 1 are 16 bits wide. Since the 8051 has an 8-bit
architecture, each 16-bit timer is accessed as two separate registers of low byte
and high byte.
* In Timer 0 and Timer 1, the low byte register is called TLO/TL1 and the high
can be accessed like any
byte register is called as THO/TH1. These two timers
other registers.
<br>

Page 120 of 440

Design
Embedded Systems and I0T
3.16
TLO
THO

D6 D5 D4 D3 D2 D1 DO
D13|D12 D11D10 D9 D7
D8
D15 D14

g
(a) Timers 0 Registers

in
er
TL1
TH1

e
in
D1 DO
D15D14D13| D12 D11D10 D9 D8 D7 D6 D5 D4 D3 D2

ng
(b)Timers 1 Registers

Fig 3.12
fE
O
3.4.2 Structure of TMOD (Timer Mode) Register
e

Both the timers 0 and I uses the same register is called as TMOD which is used
to
g

set the various timer operation modes.

le

# TMOD is a 8-bit register in which the lower four bits are for Timer0 and the
ol

upper four bits are for Timer 1. In each case, the lower two bits (MI & MO) are
C

used to set the timer mode whereas, the upper two bits are used to specify the
u

operation.
ad

(MSB)
(LSB)
iln

GATE CIT M1 MO GATE CIT M1 MO

m

Timer 1
Timer 0
Ta

Fig 3.13 TMOD register

(i) Mode Bit -1 (M1),
Mode Bit-0 (MO):
M0 and M1 bits select the
timer mode and there are three modes: 0, 1,
and 2.
Mode O is a 13-bit timer.
- Mode 1
is a 16-bit timer.
- Mode
2 is an 8-bit timer.
Modesl and 2 are
widely used.
<br>

Page 121l of 440

Program and Data Memory 3.17

MI MO Mode Operating Mode
0
0 13- bit timer mode:
8-bit timer/counter THx with TLx as 5-bit prescaler.
1 1 16- bit timer mode:

g
16-bit timer/counter THX and TLX are cascaded;

in
there is no prescaler.

er
1 2 8 bit auto reload:

e
8-bit auto reload timer/counter; THx holds a value

in
which is to be reloaded into TLx each time it

ng
overflows.
1 1 3 Split timer mode
fE
O
Table 3.4
(i) c/T (Clock/Timer)
g e

This bit is used to decide whether the timer is used as a delay generator or an event
le

counter.
ol

(a) If C/T =0, it is used as a timer.

C

(b) If C/T=1, it is used as a counter.

u

(iii) Clock Source for Timer:

ad

The frequency for the timer is always 1/12" the frequency of thecrystal attached
iln

to the 8051.
m

XTAL
Ta

+ 12
oscillator

(iv) GATE

Timers of 8051 gets started and stopped by either a software or hardware control:
(a) GATE =0: Software is used.
- The
start and stop of the timer are controlled by the way of
sofhware using the
TR(timer start) bits TRO and TRI.
- The SETB instruction starts and stopped by the CLR instruction.
<br>

Page 122 of 440

3.18 Embedded Systems and 1OT Design

(b) The hardware way of starting and stopping the timer by an external source is
achieved by making GATE=1 in the TMOD register.

3.4.3 TCON (Timer/Counter) Register

a TCON register controls the timerlcounter operations. The lower four bits of

g
TCON is for interrupt functions and the upperfour bits are for tiner operations,

in
e er
MSB LSB

in
7 6 4
3 2

ng
TFI TRI TFO TRO IE1 ITI IEO ITO
fE
BIT SYMBOL FUNCTION
O
TCON.7 TF1 Timer loverflow flag
e

TCON.6 TRI Timer lrun control bit

g

TCON.5 TFO Timer 0 overflow flag

le

TCON4 TRO Timer 0 run control flag

ol

Fig 3.14 TCON register

C

Bit 3: 1E1
u

An external interrupt 1
edge flag which is set by the hardware
ad

on INTI, pin occurred

when an interrup!
and cleared by the hardware when an
interrupt ges
iln

processed.
Bit 2: IT1
m

This bit selects the external

Ta

intefrupt event type on INT1

pin,
1= Sets interrupt on falling edge.
0 =Sets interrupt on low
level.
Bit 1: IEO

Interrupt 0 edge flag, set by

the hardware when interrupt on INTO Occured
and cleared by the hardware pin
when an interrupt is processed.
<br>

Page 123 of 440

Program and Data Memory

3.19
Bit 0: ITO.
This bit selects the external interrupt event
type on the INTO pin.
1= Sets interrupt on falling edge.
bits 0 = Sets interrupt on
low level.
tiong, 3.4.4 Mode 0:13-bit Timer Mode

g
in
A Fig 3.15 shows Mode 0 which is a 13-bit
timer mode for which 8-bit of THx and

er
5-bit of TLx are
SB used. It is mostly used for interfacing possible with old MCS-48

e
family microcontrollers.
0

in
13-bit timer
0

ng
D12
DO

fE
Load 8-bit in THx Load 5-bit in TLX as prescaler
O
D7 DO D7 DO
8-bit THx register 8-bit TLx register
g e

Fig 3.15 Mode 0 Timer

le

Higher 3-bits of TLx should be written as zero while using a timer mode 0, or it
ol

will -affect the result. The 13-bit counter can hold the values between 0000 to
1FFFH in TH-TL. Therefore, when the timer reaches its maximum of 1FFFH, it
C

rolls over to 0000, and TF is raised.

u

tern
ad

3.4.5 Mode 1 Programming

ptgt a Mode 1 (16-bit timer mode)
iln

Mode I is a l6-bit timer mode which is used to generate a delay and it uses &-bit
m

of THx and 8-bit of TLx to form a total l6-bit register.

Ta

THx TLX

D15 D0

Fig 3.16 Mode -1

(1) Operations
(or) Characteristics:
The following are the characteristics and operation of mode 1:

) It is a 16-bit timer which allows value of 0000 to FFFFH to be loaded into

the timers register TL and TH.
<br>

Page 124 of 440

3.20| Embedded Systems and 1OT Design

After TH and TL are loaded with a 16-bit initial value, the timer must
be
(ii)
started. This is done by SETB TRO" for Timer '0' and " SETB TRI"
for

Timer 1'.
After the timer is stated, it starts to count up until it reaches its limit
of
(iii)
FFFFH. When it rolls over from FFFFH to 0000, it sets TF (timer flag)
bit

g
in
HIGH.

er
Each timer has its own timer flag: TFO for Timer 0, and TF1 for Timer. This
timer flag can be monitored. When this timer flag is raised, then we can stop

e
in
the timer with the instructions “ CLR TRO " or CLR TRI" for timer 0 and

ng
timer 1, respectively.
(iv) After the timer reaches its limit and rolls over, then to repeat the process the
fE
TH and TL must be reloaded with the original value, and TF must be
O
reloaded with 0.
e

XTAL
g

+ 12 TL TEF
oscillator
le

TF goes high Overflow

=0 TR
CT when FFFF0 flag
ol

Fig 3.17 Timer with mode 1 operations

C

(2) Steps to Program in Mode 1

u

To generate a time delay using the timer's mode 1, the following steps are
ad

taken:
(i) Load the TMOD value register indicating which timer (timer 0 or s
timer 1)
iln

tobe used and or

which timer mode (0 1) is selected.
m

(ii) Load registers TL and TH with initial count values.

Ta

(iii) Start the timer.

(iv) Keep monitoring the Timer Flag (TF) with the " JNB
TFx,target" instructiot
When TF becomes HIGH, then the loop exit.

(v) Stop the timer.

(vi) Clear the TF flag for the next round

(vi) Go back to Step 2 to load TH and TL again.

<br>

Page 125 of 440

3.21
3.4.6 Mode 2
Programming
Operations (or) Characteristics:
()
The following are the
characteristics and operations
of mode 2:
) a
Itis 8-bit timer which allows only
values of 00 to FFH tobe loaded
into the timer's register TH.

g
ii) After TH is loaded with the 8-bit value,

in
the 8051 gives a copy of it to TL.
Then the timer must be started which

er
is done by the instruction “SETB
for timer 0' and SETB TRO"
TRI" for timer 1.

e
in
(ii) After the timer is started and it starts to count up
by incrementing the TL

ng
register until it reaches its limit of FFH. When it
rolls over from FFH to 00, it
sets TF (timer flag) HIGH.

(a) If we are using Timer 0, TFOgoes HIGH.

fE
O
(b) If we
are using Timer 1, TF1 is raised.
e

(iv) When the TL register rolls from FFH to 0 and TF is set to 1, then TL is
g

reloaded automatically with the original value that is hold by the TH register.
le

To repeat the process, we must simply clear TF and without any need by the
ol

programmner to reload the original value. This makes mode 2 an auto-reload.

C

in contrast with mode 1 in which the programmer has to reload TH and TL.
u
ad

XTAL TF Overflow
+12
iln

oscillator flag
TR TF goes high
cT=0
m

Reload when FF0

TH
Ta

Fig 3.18 Timer with mode 2 operations

a Mode 2: 8-bit auto-reload timer mode
In 8051lmicrocontroller, mode 2 is a 8-bit auto-reload timer mode. In this mode,
We have to load the THx-8 bit value only. When the Timer gets started, the THx

Value gets automatically loaded into the TLx and TLx starts counting from that
value.
<br>

Page 126 of 440

3.22 Embedded Systems and 10T Design

When the value then the TFx flag gets set

of TLx overflows from the FFH to 0,
TLx register.
and again value from th TH gets automatically loaded into the
That's why this is called the auto-reload mode.
(2) Steps to Program in Mode 2:
The steps used by the timer's mode 2 to generate a time delay are as follows:

g
() Load the TMOD value register indicating which timer (timer 0 or timer 1)

in
is to be used, and the timer mode (mode 2) is selected.

er
(ii) Load the TH registers with the initial count value.

e
(ii) Start the timer.

in
(iv) Keep monitoring the timer flag (TF) with the JNB TE, target " instruction to

ng
see whether it is raised. Get out of the loop when TF goes
high.
(v) Clear the TF flag. fE
(vi) Go back to Step 4, since mode 2 is auto-reload.
O
3.5 COUNTER PROGRAMMING
e

# Timers can also be used as counters counting events happening outside the
g

8051.When it is used as a counter, it is a pulse outside

le

the 8051 that increments

the TH, TL registers.
ol

TMOD and TH, TL registers are the same as for the timer.
C
u

3.5.1 C/T bit in TMOD Register

ad

The CT bit in the TMOD registers decides

the source of theclock for the timer.
iln

(i) IfCT = 0, the timer gets pulses from the crystal.

(ii) IfCT= 1, the timer is
m

used as a counter gets and its pulses from outside

Ta

the 8051.
4 The counter. counts up as pulses are
fed from pins 14 and 15 and these are
called TO pins
(timer 0 input) and T1 (timer 1 input).
Pin Port Pin Function Description
14 P3.4 TO Timer/counter 0 external
input.
15 P3.5 T1 Timer/counter 1 external input.
<br>

Page 127 of 440

Program and Data Memory 3.23

(MSB) (LSB)
GATE C/T M1 MO GATE C/T M1 MO
Timerl Timer 0
Fig 3.19 Port 3 pins used for Timers 0 and I

g
Port pins are used for Timers 0 and 1. In case of Timer 0, when C/T = 1, pin
3

in
P3.4 provides the clock pulse and. the counter counts up for -each clock pulse

er
coming from that pin.

e
Similarly, for Timer 1, when C/T = 1
each clock pulse coming in from pin P3.5

in
that makes the counter count up.

ng
(1) Counter 0 in Mode 1:
fE Overflow
flag
O
Timer 0 THO TLO TFO
external
input
e

pin 3.4 TFO goes high

g

TRO when FFFF 0

CT = 1
le

Fig 3.19 Timer O with External Input (mode 1)

ol

To operate counter 0 in mode 1 we have to perform the following steps in TMOD

C

register:
u

CT= 1; to allow counter mode operation.

ad

i)
1.
(11) M1:MO bits are set to 01 to select mode
iln

start the counter.

When GATE=0 and TRO is set to to
1
(iii)
m

(iv) When GATE = 1; counter will run only if TRO is set tol and the logic signal
on external interrupt pin INTO is high.
Ta

(2) Counter 1
in Mode 1:
Overflow
flag
Timer 1 T1
external
input
TH1
TL1H
pin 3.5 TF1'goes high
TR1 when FFFF0
= 1
ciT
(mode 1)
Fig 3.20 Timer I with External Input
<br>

Page 128 of 440

3.24| Embedded Systems and IOT Design

To operate counter 1 in mode 1 we have to perform the following steps in TMOD
:
register
(i) C/T=1, to allow the counter mode operation.

(i) M1:MO bits are set to 10 to select mode 1.

(iii) When GATE =0 and TRI is set to 1 in order to start the counter.

g
(iv) When GATE = 1, counter will run only if TRI is set tol and the logic signal

in
on external interrupt pin INTI is set to high.

er
(3) Counter O in Mode 2:

e
Overflow

in
flag

ng
Timer 0
external TFO
input TRO
pin 3.4 fE Reload
THO
O
cT=1 TFO goes high
e

when FF0
g

Fig 3.21 Timer 0 witlh ExternalInput

le

(mode 2)
To operate counter0 in mode
2 we have to perform the following
ol

register: steps in TMOD

C

(i) C/T = 1, to allow

the counter mode operation.
u

.
(ii)) M1:M0bits are set to
10 to select mode 2.
ad

(ii) When GATE=0 and TRO

is set to 1 in order to start
iln

(iv) When GATE =1, counter the counter.

will run only if TRO is set
on external interrupt tol and the logic signal
m

pin INTO is set to high.

Ta

(4) Counter 1 in Mode 2:

To operate counterl
inmode 2 we have to perform the following
register: steps in TMOD
() CT=1, to allow counter
mode'operation.
(i) M1:MO bits are set to 10 to
select mode 2.
=
(ii) When GATE =0 and TRI is set to 1
in order to start
the counter.
<br>

Page 129 of 440

Program and Data Memory

3.25
(iv) When GATE =1, counter run
will only if TRI is set tol and the logic
on external signal
interrupt pin INTI is set to high.

Overflow
Timer 1 flag
external TF1
input

g
pin 3.5 TR1

in
Reload

er
TH1
cIT

e
=1 TF1 goes high

in
when
FF0
Fig 3.22 Timer Iwith External Input (mode 2)

ng
3.5.2 TCON Register: Timer/ Counter Control Register fE
4 TCON (timer control) register is a 8-bit register. The upper
four bits are used to
O
store the TF and TR bits of both Timer 0 and Timer 1
and the lower four bits are
used for controlling the interrupt bits.
g e

The TROand TRIflags in TCON register are used to turn on or off the timers.
le
ol

(MSB) (LSB)
TF1 TR1 TFO TRO IE1 IT1
C

IEO ITO
u
ad

Upper 4 bits Lower 4 bits

iln

Name and Significance

m

Symbol Position
Timer Overflow Flag. Set by hardware on
1
Ta

TF1 TCON.7
tmer/counter overflow. Cleared when interrupt
processed.
TRI TCON.6 Timer-1 Run control bit. Set/cleared by software to
turn timer/counter on/off.
TFO TCON.5 Timer 0 Overflow Flag. Set by hardware on
timer/counter overflow. Cleared when interrupt
processed.
<br>

Page 130 of 440

3.26| Embedded Systems and 1OT Design

Symboi Position Name and Significance

to
TRO TCON4 Timer 0 Run control bit. Set/cleared by software
turn timer/counter on/off.
external
IE1 TCON.3 Interrupt 1Edge Flag. Set by hardware when
interrupt edge detected. Cleared when interrupt

g
processed.

in
IT1 TCON.2 Interrupt 1 Type control bit. Set/cleared by software

er
to specify falling edge/low level triggered external

e
interrupts.

in
IEO TCON.1 Interrupt 0 Edge Flag. Set by hardware when external

ng
interrupt edge detected. Cleared when interrupt
processed.
ITO TCON.0
fE
Interrupt 0 Type control bit, Set/cleared by software
to specify falling edgelow level triggered external
O
interrupts.
e

Fig3.23 TCON register

g

TCON egister is a bit-addressable register. Instead of using instructions such as

le

"SETB TRI" and "CLR TRI", we could use "SETB TCON.6" and « CLR
ol

TCON.6 ", respectively.

C

Timer 0
u

SETB TRO SETB TCON. 4

ad

CLR TRO CLR TCON. 4

iln

SETB TFO = SETB TCON. 5

m

CLR TFO = CLR TCON. 5

Ta

Timer 1
SETB TRI SETB TCON, 6
CLR TR1 CLR TCON, 6
SETB TF1 SETB. TCON. 7
CLR TF1 CLR TCON. 7
Table 3.5 Equivalent instructions
for the TCON.
<br>

Page 131l of 440

Program and Data Memory 3.27

3.5.3 GATE = in TMOD

1

4 If GATE = 1, the start and stop of the timer are done externally through pins P3.2
and P3.3 for timers 0 and 1, respectively. This hardware way allows to start or
stop the timer extermally at any time via a
simple switch.

g
XTAL
Oscillator + 12

in
e er
c/T-1

in
TO IN
Pin 3.2

ng
TRO

Gate
fE
O
INTO Pin
Pin 3.2
e

Fig 3.24 Timer/Counter 0

g
le

a Timer0 and Timer 1 are turned ON by the software method using the
SETB
ol

TRO" and “ SETB TRI" instructions and which is beyond the control of the user
C

of that product.
u

XTAL +12
ad

Oscillator Tc/T-0
iln
m

c/T=1
T1 IN
Ta

Pin 3.5

TR1

Gate

INT1 Pin
Pin 3.3

Fig 3.25 Timer /Counter 1

<br>

Page 132 of 440

3.28 Embedded Systems and IOT Design

3.6 8051 SERIAL PORT PROGRAMMING

3.6.1 8051 Connection to RS232

port for connecting the computers and their
RS-232 is a standard communication
peripheral devices to enable the serial data exchange.

g
5

in
1 2 3 4

e er
in
ng
fE
6 7 8 9
O
Pin Deseription
e

1
Data Carrier Detect (DCD)
g
le

2 Received Data (RxD)

ol

3 Transmitted Data (TxD)

C

4 Data Terminal Ready (DTR)

u

5 Signal ground (GND)

ad

6 Data Set Ready (DSR)

iln

Request ToSend (RTS)

m

Clear To Send (CTS)

Ta

Ring Indicator (RI)

Fig 3.26 RS-232 connector DB-9

(1) RxD and TxD Pins
8051 has hwo pins that are used specifically
for transferring and receivilig
data serially. These two pins are called TxD
and RxD and are part of the port
3group (P3.0 and P3.1).
<br>

Page 133 of 440

Program and Data Memory

3.29
Pin 11 of
the 8051(P3.1) is assigned to TxD and pin 10 (P3.0) is designated as
RxD. These pins are TTL compatible; therefore,
they require a line driver to
make them RS232 compatible.

(2) MAX 232

g
The RS232 standard is not TTL Compatible, therefore,
it requires a line driver

in
(voltage converter) such as the MAX232 chip to convert RS232
voltage levels

er
to TTL levels, and vice versa:

e
o The RS232's signals to TTL voltage
levels will be acceptable at the 8051's

in
TxD and RxD pins.

ng
8051 MAX232

TxDO (P3.1)
11 11
fE
14
O
13

RxDO (P3.0) 10 12
DB-9
g e
le

Fig 3.27 8051 connection with 8051

ol

3.6.2 Baud Rate in 8051

C

* To allow the data transfer between the PC and 8051 system without any error, we
u

must make sure that the baúd rate of the 8051 system matches the baud rate of the
ad

PC's COM port.

iln

* The 8051 transfers and receives data serially at many different baud rates. The
m

baud rate in the 8051 is programmable which is donc with the help of Timer 1.
Ta

4 The 8051 divides the crystal frequency by 12 in order to get the machine cycle
frequency. In the case of XTAL =l1.0592 MEHz, the machine cycle fequency is
921.6 kHz (11.0592 MHz /12=921.6 kHz).

* The 8051's serial communication UART circuitry divides the machine cycle
frequency of 921.6 kHz by 32 once more before it is used by Timer I to set the
baud rate. Therefore, 921.6 kHz is divided by 32 gives 28,800 Hz.
<br>

Page 134 of 440

3.30| Embedded Systems and I0T Design

Machine cycle freq. 28,800 Hz

XTAL + 12
+32
by UART to
1
To Timer
Oscillator 921.6 kHz
set the baud
rate

g
in
Fig 3.28 Baud rate in the 8051

er
must be programmed in mode 2, that
When Timer is used to set the baud rate it
1

is 8-bit, auto-reload. To get baud rates compatible with the

PC, we must load THI

e
in
with the values shown in Tabl 3.6.

ng
Baud Rate THI(Decimal) THI(Hex)
9600 -3 fE FD

4800 -6 FA
O
2400 -12 F4
e

-24 E8
g

1200
le

Table 3.6: Timer 1 THIregister values for various baud rates

ol

3.6.3 SBUF Register

C

a SBUF is a 8-bit register used solely for the purpose of serial communication. For
u

a byte data to be transferred via the TxD line, it must be placed in the SBUF
ad

register. Similarly, SBUF holds the byte of data when it is received by 8051 RxD
iln

line.
m

3.6.4 SCON (Serial Control) Register

Ta

The SCON register is a 8-bit register which is

used to program the start bit, stop
bit,and data bits of the data framing. Fig 3.29
describes various bits of the SCON
register.
(MSB)
(LSB)
D7 6 4 3
2 1 DO
SMO SMI SM2 REN TB8 RB8 TI RI
<br>

Page 135 of 440

Program and Data Memory

3.31|
Symbol Position Name and significance
SMO SCON.7 Serial port Mode control bit 0
which is set/cleared
by the software.
SM1 SCON.6 Serial port Mode control bit 1
which is set/cleared

g
by the software.

in
SM2 SCON.5 Serial port Mode control bit 2 which is used
for

er
multiprocessor communication.

e
REN SCON.4 Receiver Enable control bit. Set/cleared by the

in
software to enableldisable the serial data reception.

ng
TB8 SCON.3 Transmit Bit 8. Not widely used.
RB8 SCON.2
fE
Receive Bit 8: Not widely used.
O
TI SCON.I Transmit Interrupt flag. Set by HW and cleared by
SW.
g e

RI SCON.0 Receive Interrupt flag. Set by HW and cleared by

le

SW.
ol

Fig 3.29 SCON serial port control register (bit- addressable)

C

) SMO, SM1:
u

SM0and SMIare D7 and D6 of the SCON register, respectively. These two

ad

bits determine the framing of data by specifying the number of bits per
character, and the start and stop bits.
iln

In the SCON register, when serial mode 1 is chosen, the data framing is 8
m

bits, I stop bit, and l start bit which makes it compatible with the COM port
Ta

of IBM/compatible PCs.
In serial mode 1, it allows the baud rate to be variable and is set by Timer
1

of the 8051.

SMO SM1 Mode

0 Serial Mode 0.
1 Serial Mode 1,
8-bit data, 1 stop bit, Istart bit.
<br>

Page 136 of 440

Embedded Systems and 10T Design

3.32
2.
1 0 Serial Mode

1 1 Serial Mode 3.

(i) SM2
enables the multiprocessing

g
SCON register and this bit
SM2 is the DS bit of the

in
capability of 8051.

er
(iii) REN (Receive Enable)

e
as since
is also referred to SCON.4

in
the SCON register which
It is D4 bit of

ng
SCON isa bit-addressable register.
bit is high (REN = 1), it allows the 8051 to receive data on the
() When REN fE
RxD pin of the 8051.
O
=
(ii) When REN bit is low (REN 0), the receiver is disabled.
SETB SCON.4" and
e

REN =1 or REN=0 can be achieved by the instructions

g

"CLR SCON. 4", respectively.

le

These instructions use the bit-addressable features of register SCON. This bit
ol

can be used to block any serial data reception.

C

(iv) TB8 (Transfer Bit 8)

u

TB8 is bit D3of SCON which is used for both the serial modes 2 and 3.
ad

(v) RB8 (Receive Bit 8)

iln

RB8 is bit D2 of the SCON register. In serial mode 1, this bits gest a copy the
of
m

stop bit when a 8-bit data is received.

Ta

(vi) TI (Transmit
Interrupt)
TI is bit Di of the SCON register. When 8051 finishes the transfer
of 8-b
character:
-
I raises TIflag to indicate that it is ready to transfer an
another byte.
TI bit is raised at the beginning
of the stop bit.
(vi) RI(Receive Interrupt)
.
RIis the DO bit of the SCON register.
After 8051 receives
RxD:
data serially
<br>

Page 137 of 440

Program and Data Memory

3.33
It raises the RI flag bit to indicate
that a byte has been received and
be picked up should
before it is lost.
RI is raised hatfiway through the stop bit.

Mode Transmission format

Baud rate
8-data bits.

g
oscillator frequency

in
12
10-bit (start bit + 8-data bits + stop bit).

er
Variable

e
2 11-bit (start bit + 8-data bits + 1

in
programmable 9" data bit + stop bit). Programmable to either 32

ng
1

fE or
a oscillator frequency
3 11-bit (start bit + 8 data bit +| Variable
programmable 9" data bit + stop bit).
O

Table 3.7 Summary of'serial port modes

g e

3.6.5 Programming the 8085 to Transfer Data Serially:

le

steps are used to program the 8051 in order to transfer the character
ol

The following
bytes serially:
C

) TMOD register is loaded with the value 20H which indicates the use of
u

timer 1 in móde 2 (8-bit auto-reload) to set the baud rate.

ad

(i) The THIis loaded with one of the values to set the baud rate for serial data
iln

transfer.
m

(ii) The SCON register is loaded with the value 50H which indicates serial mode
Ta

1, where a 8- bit data is framed with start and

stop bits.

(v) TR1 is set to l to start Timer 1.

() TI is cleared by "CLR TI instruction.

register.
(V1) The character byte to be transferred serially is written into SBUF
use of instruction “JNB TI. Xx" which
(VIi) The TI flag bit is monitored with the
indicates whether the character has been transferred completely.

(iii) To transfer the next byte, go to Step 5.

<br>

Page 138 of 440

3.34| Embedded Systems and 10T Design

3.6.6 Programming the 8051 to Receive Data Serially:

The following steps are uscd to progranm the 80S1 to receive character bytes serially:
use of
() TMOD register is loaded with the value 20H, which indicates the
timer l inmode 2 (8-bit auto-reload) to set baud rate.
(ii) THl is loaded to set baud rate.

g
in
indicates serial
(iiü) Thc SCON register is loaded with the value 50H, which

er
receive
mode 1, where a 8- bit data is framed with start and stop bits and

e
cnablc is turned on.

in
(iv) TRI is set to 1 to start Timer 1.

ng
(v) RI is cleared by " CLR RI" instruction.
(vi) The RI flag bit is monitored with the use
fE of instruction " JNB RI, xx" if an
entire character has been received yet.
O
(vii) When RI is raised, SBUF has the byte and its contents are moved into a safe
e

place.
g
le

(vii) To rcccive the next character, go to step 5.

ol
C

3.6.7 Doubling the Baud Rate in the 8051

t4 There are two ways to increase the baud rate of data transfer in the 8051 are,
u
ad

() To use a higher frequency crystal.

(ii) To change a bit in the PCON (power control) register.
iln
m

(1) PCON (Power Control) Register

Ta

The PCON or Power Control register is used to control the 8051

microcontroller's power modes. Using two bits in the PCON register, the
microcontroller can be set to idle mode as well as power down mode. 87HS
assigned to the PCON register. Fig 3.30 shows the bit pattern of PCON.

D7 DO

SMOD GF1 GFO PD IDL

<br>

Page 139 of 440

Program and Data Memory

3.35
Symbol Position Name and Significance
SMOD PCON.7 Serial baud rate modify bit. It is 0 at reset. It is set to 1
by program to double the baud rate.
PCON 6-4 Not defined
GF1 PCON.3 General purpose user flag bit 1. Set/cleared by program.

g
PCON.2 General purpose user flag bit 0. Set/cleared by program.

in
GFO

er
PD PCON.1 Power down bit. It is set to 1 by program to enter power
down configuration for CHMOS microcontrollers.

e
PCON.0 Idle mode bit. It is set to 1 by program to enter idle

in
IDL
mode configuration for CHMOS microcontrollers.

ng
Fig 3.30 PCON register fE
There is a software way to double the baud rate of the 8051 while the crystal
O
frequency is fixed. This is done with the register called PCON.
The PCON register is a 8-bit register. The bit that is used for the serial
g e

communication is D7, the SMOD(serial mode) bit.

le

When the 8051 is powered up, D7(SMOD bit) of the PCON register is zero.
ol

We can set it to high by the software and thereby double the baud rate.
C

(2) SMOD
u

57600 Hz
ad

SMOD =1
11,0592 MHz +16 To timer
1 To set
XTAL
Machine cycle freq.
iln

+ 12 the Baud
oscillator 921.6 kHz 28800 Hz
+32 rate
m

SMOD =0

Fig 3.31 Baud rates for SMOD.

Ta

(i) Baud Rates for SMOD = 0

32 and uses
When SMOD = 0., the 8051 divides 1/12 of the crystal frequency by
that frequency for Timer to set the baud rate.
1

= 12 = 921.6 kHz
Machine cycle frequency 11.0592 MHz/
=
and 921.6 kHz /32 28,800 Hz for
SMOD =0.
<br>

Page 140 of 440

Embedded Systems and 10T Design

|3.36|
= 1
(iü) Baud Rates for SMOD

frequency, we can double the baud rate by making

With the fixed crystal
SMOD =1.

= 11.0592 MHz/ 12 = 921.6 kHz

g
Machine cycle frequency

in
Hz for SMOD = 1.
and 921.6 kHz/ 16=57,600

er
uses that
XTAL is divided by 16 and
XTAL = 11.0592 MHz, then 1/12 of

e
rate.
frequency for Timer l to set the baud

in
ng
(Decimal) (Hex) SMOD=0 SMOD=1
THÍ
9,600 19,200
-3 FD fE
-6 FA 4,800 9,600
O
- 12 F4 2,400 4,800
e

-24 E8 1,200 2,400

g

Table 3.8 Baud Rate comparison for SMOD =

le

and SMOD =1
0
ol

3.7 SOLVED EXAMPLES

C

Example-1
u

State the contents of RAM locations after the following program:

ad

MOVR0, #99H ; load R0 with value 99H

iln

MOV R1, #85H :;

load R1 with value 85H
m

MOV R2, #3FH ;load R2 with value

3FH
Ta

MOV R7, #63H ; load R7 with value

63H
MOV R5, #12H ; load RS with value 12H
Solution
After the execution
of the above program, we have
the following:
RAM location 0 has value
99H RAM location 1 has value
RAM location 2 has value 3FH 85H
RAM location 7 has
RAM location 5 has value 12H value 63H
<br>

Page 14lof 440

Program and Data Memory

3.37|
Example-2
Show the stack and stack pointer from the
following. Assume the default stack
area.
MOV R6, #25H
MOV Rl, #12H

g
MOV R4, #0F3H

in
PUSH 6

er
1
PUSH

e
PUSH 4

in
ng
Solution
After PUSH 6 fE
After PUSH 1
After PUSH 4
OB OB OB 0B
O
OA OA OA OA F3
e

09 09 12 09 12
g

08 08 25 08 25 08 25
le

Start SP= 07 SP = 08 SP= 09 SP= 0A

ol

Example-3
C

.
Examining the stack, show the contents of the register and SP after execution
u

of the following instructions. All value are in hex.

ad

POP 3 ;
POP Stack into R3
iln

POP 5 ;
POP Stack into R5
POP Stack into R2
m

;
POP 2
Ta

Solution
After POP 3 After POP 5 After POP 2

OB 54 OB 0B OB

OA F9 OA
F9

09 76 09 76 09 76 09

08 6C 08 6C 08 6C 08 60

Start SP 0B SP= 0A SP = 09 SP = 08
<br>

Page 142 of 440

Embedded Systems and 10T Design

3.38|

Example-4
Indicate which mode and which timer is selected for each of the following.
(a) MOV TMOD, #01H (b) MOV TMOD, #20H (C) MOV TMOD, #12H

Solution

g
(LSB)

in
(MSB)
CIT M1 MO

er
GATE CIT M1 MO GATE

Timer 1 Timer 0

e
in
TMOD register

ng
Based on M1 and MO bits:
We convert the value from hex to binary. fE
(a) TMOD = 00000001, model of timer 0 is selected
O
(b) TMOD=00100000, mode 2 of timer 1 is selected
timerlare selected.
e

(c) TMOD= 00010010, mode 2 of timer 0, and mode l of

g
le

Example-5
ol

Find the timer's clock frequency and its period for various 8051-based
C

systems, with the following crystal frequencies.

u

(a) 12 MHz
ad

(b) 16 MHz
iln

(c) 11.0592 MHz

m

Solution
Ta

XTAL
+ 12
oscillator

(a) 1/12 x 12 MHz = 1

MHz and T=1/1 MHz = 1 us
(b) 1/12 x 16 MHz =
1.333 MHz and T = 1/1.333 MHz us
=75
(c) 1/12 x 11:0592 MHZ =921.6kHz:

T= 1/921.6 kHz=1.085 us
<br>

Page 143 of 440

Program and Data Memory 3.39

Example-6
With XTAL = 11.0592 MHz, find the TH1 value needed to have the following
baud rates. (a) 9600 (b) 2400 (c) 1200

Solution

g
The machine cycle frequency of 8051 = 11.0592/12 = 921.6 kHz, and 921.6

in
LHZ/32 = 28,800 Hz is frequency by UART to timer 1 to set baud rate.

er
(a) 28,800/3 = 9600 where-3 = FD (hex) is loaded into TH1

e
(b) 28,800/12 =2400 where-12 = F4 (hex) is loaded into THI

in
(c) 28,800/24 = 1200 where -24 = E8 (hex) is loaded into TH1

ng
Example-7 fE
Ifthe crystal frequency is 22 MHz, what will be the baud rate if: (a) THÍ =-3;
O
(b) THI=-12 with SMOD =0 and SMOD= 1?
e

Solution
g
le

With SMOD = 0, we have

ol

22
Machine Cycle freq. = 12 = 1833 kHz
C

1833 = 57.281 kHz = 57,281

and 32
u
ad

57281 =
(a) With THI =-3, the baud rate is 3
19,093
iln

57281 =
(b) With TH =-12, the baud rate is 12
4773
m

With SMOD = 1, thebaud rates are doubled.

Ta

(a) With THI=-3, the baud rate is 38,186

(b) With TH=-12, the baud rate is 9546
3.8 TWO MARKS OUESTIONS AND ANSWERS
Write the memory capacity
of microcontroller 8051. NOVVDEC -2008]
[OR]
[APRMAY-2010]
Give the memory size of 8051 microcontroller.
<br>

Page 144 of 440

3.40| Embedded Systems and 10T Desion

8051 has 4KB on-chip program memory (ROM) and 64 KB external program
memory. It also has 128 bytes of on-chip data memory (RAM) and 64 KB

external data memory.

2. What is program memory?

g
are stored in the
In 8051 microcontroller, the code or instructions to be executed

in
Tha
program memory, which is also called as the ROM of the microcontroller.

er
original 8051 microcontroller by Intel has 4KB of internal ROM.

e
Write thefunction of data memory in 8051l microcontroller.

in
3.
The data memory or RAM of the 8051 microcontroller stores temporary data
and

ng
intermediate results that are generated and used during the normal operation of the
fE
microcontroller. Original Intel's 8051 microcontroller had 128B of internal RAM.
Almost all modern variants of 8051 microcontroller have 256B of RAM.
O
4. Define stack. [APRMAY-2018
e

The stack is a section of internal RAM used by the CPU to store the information
g

temporarily. This information could be a data or an address. The CPU needs this
le

storage area since there is only limited number of registers.

ol
C

5. What is meant by Stack Pointer?

If the stack is a section of RAM, then there must be registers inside the CPU to
u

point to it. The register used to access the stack is called the Stack Pointer (SP)
ad

register.
iln

6. What is ISR?
The program which is associated with the interrupt is called the Interrupt
m

Servico
Routine (ISR) or Interrupt Handler.
Ta

7. Define interrupt.
Interrupt is a sub-routine calls which is given to the
microcontroller. When so
other program with high priority is
requesting for acquire the system buses
an interrupt occur current
in running program.
Interrupts provide a method to postpone
or delay the current process, thereby
performs a sub-routine task and
then restart the standard program
again.
<br>

Page 145 of 440

Program and Data Memory

3.41
8 What ispolling?
The microcontroller continuously
monitors the status of a given device. When
the conditions met, it performs
the service. After that, it moves on in order to
monitor the next device until everyone is serviced.

polling can monitor the status

of several devices and serve each of them as

g
certain conditions are met.

in
Write the advantages of interrupts in

er
9. the microcontrollers.
The advantages of interrupts in the microcontrollers are,

e
in
() It can serve many devices but not all at the same time.

ng
Each device can get the attention of the microcontroller based on the
assigned priority. fE
For the polling method, it is not possible to assign priority since it checks
O
alldevices in a round-robin fashion.
e

(i) The microcontroller can also ignore (mask) a device request for service,
g
le

which is not possible for the polling method.

ol

10. What is Interrupt vector table?

C

The group of memory locations which set separately to hold the addresses of
Interrupt Service Routines (ISRs) is called Interrupt Vector Table.
u
ad

11. What do you mean by Interrupt vector address?

iln

Interrupt vector addrèss is the address where the controller jumps after the
interrupt to serve the Interrupt Service Routine (ISR).
m

I2. Define Interrupt Priority (1P) register.

Ta

We can alter the sequence of interrupt priority by assigning a higher priority to

any one of the interrupts by programming a register called Interrupt Priority (IP).
What are the sources of interruptsin 8051? NOVIDEC -2010]
5
[OR]
Name the interrupts available in microcontroller 8051.
[NOVDEC-2008 & APR/NOV-2008]
<br>

Page 146 of 440

3.42 Embedded Systems and I0T Design

External interrupt 0 IEO 0003H

Timer interrupt 0 TFO 000BH
External interrupt 1 IEI 0013H
Timer interrupt 1 ' TF1 001BH

g
0023H

in
Receive interrupt R1

er
Transmit interrupt T1 0023H

e
14. Define IE.

in
Interrupt Enable (IE) is a register that is responsible for enabling (unmasking)

ng
and disabling (masking) the interrupts.
fE
154 What is the difference between timer and counter operation in 8051?
NOVDEC-2004 & APRMAY-2005]
O
The 8051 has two timers/counters. They can be used either as timers in order to
e

generate a time delay or as event counters to count events happening outside the
g

microcontroller.
le

16. What is TMOD register?

ol

Both the timers 0 and 1 uses the same register is called as TMOD (Timer Mode)
C

which is used to set the various timer operation modes.

u

TMOD is a 8-bit register in which the lower four bits are for Timer 0 and the
ad

upper four bits are for Timer 1. In each case, the lower two bits (M1 & M) are
iln

used to set the timer mode whereas the upper two bits are used to specify the
operation.
m

17. What do you mean by mode l timer?

Ta

Mode 1 is a 16-bit timer mode which is used to generate a delay and it uses 8-bit
of THx and 8-bit of TLx toform a total 16-bit register.
18. Why mode-2 in 8051 microcontroller is also called an auto-related mode?
In 8051 microcontroller, mode 2 is a 8-bit auto-reload timer mode. In this mode,
we have to load the THx-8 bit value only. When the Timer gets
started, the THX
value gets automatically loaded into the TLx and TLx starts counting from thal
value.
<br>

Page 147 of 440

Program and Data Memory |3.43

/hen the value of TLX overflows from the FFH to 0, then the TFx flag gets set
ad again value from the THx gets automatically loaded into the TLx register.
That's why this is called the auto-reload mode.
10 List the ways used to increase the baud rate of data transfer in the 8051.

There are two ways to increase the baud rate of data transfer in the 8051 are,

g
in
() To use a higher frequency crystal.

er
(ii) To change a bit in the PCON.(power control) register.

e
20. Which register has the SMOD bit, and what is its status when the 805! is

in
NOVVDEC -2021]

ng
powered up?
The PCON (power control) register is a 8-bit register. The bit that is used for the
fE
serial communication is D7, the SMOD (Serial mode) bit.

of the PCON register is zero. We can

O
When the 8051 is powered up, SMOD bit
set it to high by the software and thereby double the baud rate.
g e

3.9 REVIEW QUESTIONS

le
ol

[APRMAY-2006]
I. Explain the RAM memory space allocation in
8051.
C

an 8051 microcontroller. APRMAY-2010]

2. Explain the memory structure of
u

805l microcontroller. [APRMAY-2019)

3. Explain the memory organization of
ad

4. Draw the data memory structure of 8O51

microcontroller and explain.
iln

[NOVDEC-2017|
m

8OSl microcontroller?
How do youselect a register bank in
Ta

D
NOVDEC-2011 & APRMAY -2010, 1I]
access external memory devices in an 8051
O Explain with block diagram, how to
[NOVIDEC-2017]
based system.

DiscuSs in detail about the stack in the

805lmicrocontroller.
any two interrupts.
O What are the interrupts of 805I? Highlight the function of
NOVDEC-2019)
<br>

Page 148 of 440

3.44| Embedded Systems and I0T Design

(APRMAY-2016]
9. Explain the vectored interrupts in 8051 microcontroller.
80S1. [NOVIDEC-2007 & 08]
Writeashort notes on interrupt
of
10.
register in 8051 microcontroller.
l1. Briefly write about the IE and IP (NOVIDEC-2011)

g
(TMOD) register of 8051.

in
options available with Timer Mode
12. Illustrate the
[NOVIDEC-2021 & APR/MAY-2023/

e er
witlh neat diagram.
13. Disciuss in detail about TCON register

in
and mode -2 timer operations the control
witlh
I

ng
14. Write about the mode
registers used in 805I.
(NOVDEC -2022)

15.
fE
Explain the different modes of operation of timers in 8051 in detail
with its
[NOVDEC -2004 & APRMAY-2011, 17]
O
associated registers.
16. Draw the block diagram of Intel 8031/805I timer/counter and erplain its
e

[APRMMAY -2004]
g

different modes of operation.

le

17. Discuss the counters and timers of

8051 microcontroller. [NOVDEC-2010]
ol

18. Draw and explain SCON special function register. [NOVDEC -2010]
C

19, Discuss in detail about the serial data transfer in 8051. (NOVDEC-2022|
u
ad
iln
m
Ta
<br>

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UNIT - II
Chapter 4

g
in
EMBEDDED COMPUTING

e er
4.1 EMBEDDED SYSTEM DESIGN PROCESS

in
ng
4.1.1 Introduction

A Objectives: fE
The two major objectives of an embedded system design process are
O
() I will give us an introduction to the various steps involved in embedded
system design before we know into them in more detail.
g e

(i) It willallow us toget an idea about the design methodology itself.

le
ol

A Methodology:
C

Understanding your design mcthodology helps you to ensure that you didn't skip
reasons:
anything. A design methodology is important for the following three
u
ad

(i) Optimizing Performance:

iln

allows us to keep a scorecard on a design to ensure that cverything have done

It
or performing
whatever we need to do, such as optimizing the performance
m

functional tests.
Ta

(i) Automated Steps:

a completed design with the
Developing a single program which emits
can be resolved by
concept of an embedded system would be a risk task that
can work on automating
breaking the process into manageable steps and it
the steps one at a time.
It allows us to develop Computer-Aided Design (CAD) tools that
helps us

for automate methodology steps and to keep track of the

methodology itselt.
<br>

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Embedded Systems and 10T Design

4.2
(ii) Easy Understanding:
methodology makes it much easier for members of a design team to
Design
are designed by teams, so, the
communicate. Most of the embedded systems
a design methodology.
coordination is the most important role of well-defined

g
in
4.1.2 Steps
Fig 4.1 summarizes the major. steps involved in
the embedded system design

er
process. ln top-down design, we will begin with the most abstract
description of

e
the system and it concludes with the concrete details.
But in the bottom-up

in
a system. The real design
design, we start from small components to build large

ng
often uses the both techniques.

What does the customer want?

fERequirements
Top-down
O
Bottom-up
design design
e

System functionslcharacteristics Specification

g
le
ol

Block diagram (HW vs. SW) Architecture

C
u

HW& SW module detailed design Components

ad
iln

Working System System integration

m

Fig 4.1 Major levels of abstraction in the design process

Ta

In this top-down view, we start with the system requirements and specification
that is we create a more detailed description of what we want?
The bottom-up design information to help us refine
the system and its steps are
shown in the Figure 4.1 as dashed-line arrows.
The specification states only how the system
behaves, not how it is built? Tne
details of the system's internals begin to
architecture, which gives the system structure
take shape. when we develop
in terms of large components.
e
<br>

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Embedded Computing
4.3
Once we know the
needed components, we can
components, including design our need using
both the software modules those
-Based on those components, and any specialized hardware.
we can finally build a
complete system.
Major Goals:
The major goals
of the embedded system design are,

g
in
(i) Manufacturing cost,

er
(ii) Performance (both
overall speed and deadlines),
and

e
(iii) Power consumption.

in
ng
a Tasks:
The tasks which should be performed at every fE
step in the design process:
(i) We must analyze the design at each step to
determine how we can meet
O
the specifications.
e

(i) We must then refine the design to add detail.

g
le

(iii) We must verify the design to ensure that it still meets

all system goals,
ol

as
such cost, speed, and so on.
C

4.1.3 Requirements
u

At the initial stages of the design process, we must know what we are
designing?
ad

This information is useful in creating the architecture and components.

We
iln

generally proceed this information in tvo phases:

m

() We gather an informal description from the customers known as

Ta

requirements, and
(a) We refine the requirements into a specification that contains enough
information to begin the designing of the system architecture.

(1) Requirements vs. Specifications

Separating out requirements analysis and specification is often necessary
because of the large gap between what the customers can describe about the
system they want and what the architects need to design the system.
<br>

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Embedded Systems and 10T Design

4.4
Definition:
what the user wants and expects
Requirement is a plain language description of
ways:
to get. It may be developed in several
Talking directly to customers,

g
Talking to marketing representatives, and

in
er
users for comment.
Providing prototypes to the

e
as a function of output) or
Requirements may be functional (output

in
not sufficient.
non-functional. Functional description is often

ng
s Nonfunctional Requirements: fE
The typical nonfunctional requirements are,
O
() Performance:
e

usability of the
The speed of the system is major consideration for the
a
g

system and its ultimate cost.

le

such
The performance may be a combination of soft performance metrics
ol

as approximate tine to perform a user-level function and hard deadlines

C

by which aparticular.operation must be completed (atency).

u
ad

(ii) Cost:

The target cost or the purchase price of the system is almost a consideration.
iln

Cost typically has two major components:

m

(a) Manufacturing cost which includes the cost of components and

Ta

assembly, and
(b) NonRecurring Engineering (NRE) costs include the personnel and
other costs of designing the system.
(ii) Physical size and weight:
The physical aspects ofthe final system depend upon the application.
A handlheld device typically has
tight requirements on both the size
weight that can be considered through the
entire system design.
<br>

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Embedded Computing
4.5
(iv) Power Consumption:
Power is an important consideration
in other applications.
in the battery-powered systems as well as
It can be clearly specified in the requirements
terms of a battery life. stage in

(2) Validating Requirements

g
Validating a set
of requirements is a psychological task because it requires

in
understanding both i.e., what the people want
and how the communicate

er
those needs.

e
One good way is an user interface portion
of a system's requirements is to

in
build a mock-up which may uses canned data to simulate the
functionality in a

ng
restricted demonstration, and it may be executed on a PC or a workstation.
fE
It should give the customera good idea that how the system will be used and
how the user can react to it. Generally, the nonfunctional models of devices
O
can also give customers a better idea of characteristics such as size and
weight.
e
g

(3) Simple Requirements Form

le

o Requirements analysis for a big system can be complex and a time consuming
ol

one. Capturing a relatively small amount of information in a clear and simple

C

format is a good start toward understanding the system requirements.

u

can be filled out at the start of

Fig 4.2 shows a sample requirements form. that
ad

o
as a checklist and it is considered as the
the project. We can use this form
iln

basic characteristics of the system.

m

GPS moving map

Name
Ta

Purpose
Inputs
Outputs
Functions
Peformance
Manufacturing cost
Power
Physical size and weight
requirements form
Fig 4.2 Sample
<br>

Page 154 of 440

4.6 Embedded Systems and 10T Design

The entries in the requirements form are,

0) Name:
name of the project can also be useful fo
This is simple and helpful. The
develop the purpose of the design.

g
(i) Purpose:

in
It is a one or two-line description that what the
system is supposed to d.

er
(ii) Inputs and outputs:

e
an idea about the following detail:

in
The inputs and outputs to the system gives

ng
Types of data,
Data characteristics, and
Types of I/O devices.
fE
O
(iv) Functions:
system does. A good
The function is a more detailed description of what the
e

way to approach this is to work from the inputs to the outputs.

g
le

(v) Performance:
ol

at least some time to control the

Many embedded computing systems spend
C

from the physical world.

physical devices or processing data that is coming
a certain time fram.
These computations must be performed within
u
ad

It is essential that the performance requirements

be identified early because
implementation to ensure that the
they must be carefully measured during
iln

system works properly.

m

(vi) Manufacturing Cost:

Ta

This includes primarily the cost of the hardware components.

(vi) Power:
consu
We may have only a rough idea of how much power the system can
Typically, the most important decision is whether the machine will be battery
powered or plugged into the wall.
spend
Battery-powered machines must be much more careful about how they
energy.
<br>

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Embedded Computing
4.7|
(vii) Physical Size and Weight:
Some indication of the physical size and weight of the system is to
help guide
certain architectural decisions.

4.1.4 Specification

g
4 The specification serves as the contract between the customer and
the architects.

in
It must be carefully written so that it can accurately
reflects the customer's

er
requirements that can be clearly followed during the design.

e
4 Specification is essential in creating the working systems with a minimum of

in
designer effort.

ng
# The specification should be understandable because someone can verify that
fE
whether it meets system requirements and overall expectations of the customer.
O
# Designers can run into several different types of problems caused by unclear
specifications. So, the designers must know what they need to build.
g e

Example:
le

A specification of the GPS system would include several components:

ol
C

Data received from the GPS satellite constellation.

Map data.
u
ad

User interface.
Operations that must be performed to satisfy the customer requests.
iln

Báckground actions required to keep the system runing, such as operating

m

the GPS receiver.

Ta

4.1.5 Architecture Design

a Definition:
The architecture is a plan for the overall structure of the system that will be used
up the architecture. The creation of the
later to design the components that make
as design.
architecture is the first phase of what many designers think
of
<br>

Page 156 of 440

Embedded Systems and 10T Design

|4.8|
which
sample-system architecture for the moving map is shown in Fig. 4.3,
A among
block diagram that shows a major operations and data flows
form the
them.

Search Display

g
GPS Renderer
receiver engine

in
er
User

e
Interface

in
Database

ng
Fig 4.3 Block diagram for the moving map
fE
The above diagram is giving an idea that helps in
implementing the functions
4.3
described in the specification. We can refine the system block diagram in Fig
O
into two block diagrams as shown in Fig 4.4:
e

(i) One for hardware, and

g
le

(i) One for software.

ol

The hardware block diagram clearly shows that one central CPUsurrounded by
C

memory and I/O devices. We have chosen to use two memories: a frame buffer
u

for the pixels to be displayed and a separate program'data memory for general
ad

use by the CPU.

iln

The software block diagram closely follows the system block diagram and added
a timer to control when we read the buttons on the user interface and render data
m

onto the screen.

Ta

Architectural descriptions must be designed to satisfy both functional and

nonfunctional requirements. Starting out with a system architecture and refining
that to hardware and software architectures is one good way to ensure that we
meet all specifications.

First, we can concentrate on the functional elements in the system block diagram
and then consider the nonfunctional constraints when creating the hardware and
software architectures.
<br>

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Embedded Computing
4.9

Frame
buffer CPU

Display
GPS receiver

g
Memory.

in
er
Panel /O
Bus

e
in
(a) Hardware

ng
Database fERenderer Pixels
search
O
e

CPosition User Timer

interface
g
le
ol

(b) Software
C

Fig 4.4 Hardware and software architectures forthe moving map

u

4.1.6 Designing Hardware and Software Components

ad

or .
The designer must spend time for architecting the system before start coding
iln

-are ready-made and some can be

designing the circuits. Some components
m

modified from existing designs, others must be designed

fromn the scratch.
Ta

In the moving map, the GPS receiver is a good example of a specialized

component which will be a predesigned, standard component. We can also make
use of standard software modules.

4.1,7 System Integration

we can putting them together and check the
* Afier all the components are buil,
system
whether the system is working or not. Bugs are typically found diring this
integration, and good planning can help us to find the bugs quickly.
<br>

Page 158 of 440

|4.10 Embedded Systems and 10T Design

we can
By building the system in phases and running properly by chosen tests,
more easily find the bugs.

4.1.8 Formalisms for System Design

Unifted Modeling Language (UML) is an object-oriented modeling language

g
process.
which is designed to be useful at many levels of abstraction in the design

in
er
Object-oriented design emphasizes two important concepts:

e
() It encourages the design to be described as a number of interacting objects,

in
rather than a
few large monolithic blocks
of
code.

ng
(ii) We can also use UML to model the outside world that interacts with our
system such objects may be a people or other machines. Thinking of the
fE
design in terms of actual objects helps us understand the natural structure of
O
the system.
Object-Oriented (00) specification can be viewed in two complementary ways:
g e

i) It allows a system to be described in a way that closely models the real

le

world objects and their interactions.

ol

(i) Itprovides a basic set of primitives that can be used to describe systems
C

with a particular attributes, irrespective of the relationships of those

u

systems' components to the real-world objects.

ad

4 Both object-oriented specification and object-oriented programming languages

iln

provide a basic methods that are similar for structuring large systems.
m

4.1.9 Structural Description

Ta

Structural description means the basic components of the system. The principal
component of an object-oriented design is the ohject. An object includes a set
of
attributes that define its internal state.
When implemented in a programming language, these attributes usually become
variables or constants held in a data structure.
An object describing a display such as a CRT screen in UML notation is shown
in Fig 4.5. The text in the folded-corner-page icon is a note which does nol
correspond to an object in the system and only serves as a comment.
<br>

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Embedded Computing
4.11
Pixels is d1: Display
a 2-D array Object name: class name
pixels: arrayl] of pixels
elements Atributes
menu_items

Fig 4.5 An object in UML notation

g
& The attribute is an array
of pixels that holds the contents of the display.

in
object is identified in two ways: It The
has a unique name, and it is a member a

er
class. of

e
# The name is underlined to. show that this is a
description of an object and not

in
class.

ng
(1)Classes as Types
A Definition: fE
A class defines the attributes that an object may have. It also defines the
O
operations that determine how the object interacts with the rest of the world.
e

A class is a form All objects derived from the same class

of type definition.
g

the same characteristics even their attributes may have different values.
le

have
ol

The UML description of the display class is shown in Fig 4.6.

C

Display Class name

u

pixels
ad

elements Attributés
menu_items
Pixels is
iln

a 2-D array
m

mouse_click( )
draw_box() Operations
Ta

Fig 4.6 A class in UML notation

defines the pixels attribute
The class has the name: Display. The Display class
Seen in the object which has its
own memory. So that the different objects of
same own values for the attributes. Other classes can
the class have their
examine and modify class attributes.
<br>

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Embedded Systems and 10T Design

4.12

A class defines both the interface for

a particular ype of object and also for
that object's implementation.
(2) Choose Your Interface Properly
a very important decision in object-oriented
The choice of an interface is as
ways to access the object's state

g
design. The proper interface must provide

in
well as the ways to update the state.

er
Relationships between Objects and Classes:

e
can exist between objects and

in
There are several types of relationships that

ng
classes:
(i) Association: fE no
It occurs between objects that communicate with
each other but have
O
ownership relationship between them.
e

(i) Aggregation:
g

It describes a complex object made up of smaller objects.

le
ol

(iii) Composition:
owner does not allow the access to
C

It is a type of aggregation in which the

the component objects.
u
ad

(iv) Generalization:
It allows us to define one class in terms of another.
iln

(3) Derived Classes

m

UML allows us to define one class in terms of another. Fig 4.7 shows a
Ta

example where we can derive two particular types of displays:

) BW display describes a black and white display. This does not require
to add new attributes or operations, but we can specialize both to work o

one-bit pixels.
(ii) color map to allo
Color_ map_display uses a graphic device known as a
the user to select from a large number of available colours even wiu
small number of bits per pixel.
<br>

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Embedded Computing 4.13

Display
pixels
objects Base class
menu_item s

pixel( )

g
set_pixel()
mouse_click ()

in
draw_box()
8,k

er
Generalization

e
in
BW_display Color_mnap_display

ng
color_map

fE
O
Derived classes
e

Fig 4.7 Derived classes as aform of

generalization in UML
g
le

The color_ map_display class defines a color map attribute that determines
ol

how pixel values are mapped onto the display colors.

C

In this case, Display is the base class for the two derived classes. A derived
class is defined to inclde all the attributes and operations of its base class.
u
ad

s Inheritance: "
iln

The inheritance has two purposes:

(i) It allows us to describe one class that shares some characteristics with
m

another class.
Ta

(ii) It captures those relationships between classes and documents them. If we

need to change any of those classes, knowledge of the class structure
helps us to make changes.

(4) Generalization and Inheritance:

UML considers inheritance to be one form of generalization. UML allows us
to define multiple inheritance, in which each class is derived from more than
<br>

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Embedded Systems and 10TDesign

14
multiple
object-oriented programming languages support
one base class. Most
inheritance as well. Here, we have created
inheritance is shown in Fig 4.8.
An example of multiple display class with a speaker
by combining the
a Multinedia display class

g
in
class for sound. base
attributes and operations of both its
inherits all the

er
The derived class
speaker.
classes such as display and

e
in
Display
Speaker Base class

ng
fE
O
g e

Multimedia_display
le

Derived class
ol
C

Fig 4.8 Multiple inheritance in UML

u

and Associations
ad

(5) Links
capure
A
link describes a relationship between objects and association is the
iln

type information about these links.

m

Fig 4,9. shows examples of links and an association. When we consider

o the

actual objects in the system, there is a set of messages that keeps track of
Ta

current number of active messages (two messages) and also points to u

active messages.
we
In this case, the link contains the relation. generalized into classes,
When
define an association between the message set class and the message cla
The association is drawn as a line between the two labeled class with the nate
of the association, namely, contains.
The ball and the number at the message class end indicate that the messag
may include zero or more message objects.
<br>

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Embedded Computing
4.15
message msg1: mnessage
msg = msg1
set1: message set
length 1102
message set
msg2: message
Count =2
message

g
msg =msg2

in
length =2114|

er
(a) Links between objects

e
in
message

ng
Contains message set
msg: ADPCM_stream
0.* cOunt: integer
length: integer fE
O
(b)Association between classes

Fig 4.9 Links and associations

g e

4.1.10 Behavioral Description

le

One' way to
specify the behavior of an operation is a state machine. Fig 4.10
ol

shows UML states and the transition between two states are shown by a skeleton
C

arrow.
u
ad

State
iln

a b
Name
m
Ta

Fig 4.10Event-driven events in UML state machines

Changes from one. state to another are triggered by the occurrence of the events.
An event is some type of action. UML defines three types of events as illustrated
in Fig 4.11.

() Signal:
It is an asynchronous occurrence which is defined in UML by an object and
it is labeled as a << signal>>.
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4.16 Embedded Systems and IOT Design

The object in the diagram serves as a declaration of the event's existence.

Because it is an object, a signal may have parameters that are passed to the
signal's receiver.

(ii)Call Event:

g
This call event follows the model of a procedure call in a programming language.

in
er
(iii)Time-Out Event:

e
A time-out event causes the machine to leave a state after a certain amount

in
of time. The label tm(time-value) on the edge gives the amount of time after

ng
which the transition occurs.

A time-out is generally implemented with an extemal timer.

fE
O
Signal event
declaration
g e

<<signal>>
le

Name mouse_click a mouse_click (x,y,button)

(x, y, button)
ol

left to right: button

C

X, y: position
Parameters
u

Signal event
ad

Event
iln

draw_box(10,5,3,2,blue)
d
m

Call event
Ta

tm(time-value)
e. f

Time-out event

Fig 4.11Signal, call, and time-out events in UML

(1) State Machine
A simple state machine specification is used to understand the semantics of
UML state machines.
<br>

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Embedded Computing
4.17|
A state machine for an operation
of the display is shown in Fig 4.12. The start
and stop states are special states that
help us to organize the flow of the state
machine.
The states in the state machine represent
different conceptual operations. In
Some cases, we take conditional transitions out
of states based on inputs or

g
the results of some computation done the state.

in
in In other cases, we make an
unconditional transition to the next state.

er
o Splitting a complex operation into several states helps us to document

e
the
required steps, much as subroutines and it can be used to structure

in
the code.
When several objects are involved, it is useful to

ng
show the sequence of
operations over time.
fE
Start state
O

mouse_click(x,y ,button)/ region = menu/

e

find_r egion(r egion) which_menu(i) call_menu(i)

g

Stop state
le

Region Got menu Called menu

found item item
ol
C

highlight(objid)
region = drawing/
find_objec(objid)
Object
u

Found object
highlighted
ad

Fig 4.12 A State maclhine specifcation in UML

iln

(2) Sequence Diagram

m

A sequence diagram is similar to a hardware timing diagram. The time flows

Ta

vertically in a sequence diagram, whereas time typically flows horizontally in

a timing diagram.
The sequence diagram is designed to show a particular scenario or choice of
events. An example of a mouse click and its associated actions is shown in
Fig 4.13.
O In this case, the sequence shows what happens when a mouse click occurs on
the menu region. Processing includes three objects shown at the top of the
diagram.
<br>

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|4.18| Embedded Systems and IOT Design

d1: Display
m: Menu
Object m: Mouse

mouse_click (x,y,button) which_menu(i)

Time

g
in
cal _menu(i)

er
Focus of
control

e
in
Lifeline

ng
Fig 4.13 A sequence diagram in UML
fE a
Each object is extending by its lifeline which is dashed line that shows how
O
long the object is alive. In this case, all the objects remain alive for the entire
sequence, but in other cases objects may be created or destroyed during the
g e

processing.
le

The boxes along the lifelines show the focus of control in the sequence, that
ol

is, when the object i actively processing. In this case, the mouse object is
C

active only long enough to create the mouse click event.

u

The display object uses call events to invoke the menu object twice: once to
ad

determine which nenu item was selected and again to actually execute the
menu call.
iln
m

4.2 DESIGN EXAMPLE: MODEL TRAIN CONTROLLER

Ta

4.2.1 Introduction
Let us consider a simple system
that is, a model train controller which 1S
illustrated in Fig 4.14 in order to
learn how to use UML to model
The user sends messages
the systems.
to the train with a control box attached
The control box may to the tracks.
have familiar controls
button, and so on. such as a throttle, emergency S
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Embedded Computing
4.19

Receiver,
motor controller

Power

g
|supply

in
er
Console

e
in
ng
System setup

Message
fE
Header AddressComman d ECC Motor| Receiver
O
Track
g e
le

Console
ol

Signaling the train

C

Fig 4.14 A model train control system

u

power from the two rails of the track the control

ad

The train receives its electrical

box can send signals to the train
over the tracks by modulating the power supply
iln

voltage.
m

over the tracks to the receiver on the train. The

* The control panel sends packets
sense the bits being transmitted and a control
Ta

train includes analog electronics to

system to set the train motor's speed and
direction based on those commands..
on
an address so that the console can control several trains
* Each packet includes
also includes an Error Correction Code (ECC) to
the same track and the packet
errors.
guard against transmission
cannot send
one-way communication system. So, the model train
Ihis is a
Commands back to the user.
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Embedded Systems and 10T Design

|4.20

4.2.2 Requirements
Name Model train controller
model trains
Control speed of up eight
to
Purpose emergency stop, train number
Throttle, inertia setting,

g
Inputs.

in
Train control signals
Outputs upon inertia settings;
Set engine speed based

er
Functions
respond to emergency stop
at least 10 times per second

e
Can update train speed

in
Performance
Manufacturing cost $50

ng
Power 10 W (plugs into wall)
two hands,
Physical size and weight Console should be comfortable for
fE weight
approximate size of standard keyboard;
less than 2 pounds
O
Fig 4.15 Requirements in chart format
e

The basic set of requirements for the

system are,
g
le

up to eiglht trains on a single track.

(i) The console shall be able to control
ol

(ii) The speed of each train shall be

controllable by a throttle to at least
C

reverse.
63 different levels in each direction i.e., forward and
u

user to adjust the

(iii) There shall be an inertia control that should allow the
ad

inertia
responsiveness of the train to commanded changes in speed. The
control will provide atleast eight different levels.
iln

(iv) There shall be an emergency stop button.

m

An error detection schem will be used to transmit messages.

Ta

(v)

4.2.3 DigitalCommand Control (DCC)

The DCC standard was created by the National Model Railroad Association to
support an interoperable digitally controlled model trains.

The DCC was created to provide a standard that could be built by any
manufacturer. Therefore, we can use mix and match components from multip
vendors.
<br>

Page 169 of 440

Embedded Computing
4.21|
(1) DCC Standards
() Standard S-9.1
This is the DCC electrical standard
that defines how bits are encoded on the rails

g
for transmission.

in
(i) Standard S-9.2

er
This is the DCC communication standard that defines the
packets that carry

e
in
information.

ng
(2) DCC Electrical Standard
The DCC electrical standard deals with voltages and currents on the track.
fE
This standard must be carefully designed because the main function of the
O
track is to carry power to the locomotives.
e

The signa! encoding system should not interfere with power transmission
g

either to DCC' or non-DCC locomotives. A key requiremnent is that the data

le

signal should not change the DC value of the rails.

ol

The data signal swings between two voltages around the power supply
C

voltage. In the Fig 4.15, bits are encoded in the time between transitions, not
u

whilea l is
ad

is atleast 100us
only by voltage levels. The bit time of 0'
nominally 58us.
iln

a
o The specification also gives the 'allowable variations in bit times that
m

conforming DCC receiver must be able to tolerate. This standard also

Ta

as allowable
describes other electrical properties of the system, such
transition times for signals.

Time

=100 us
58 us
Fig 4.15 Bit encoding in DCC
<br>

Page 170 of 440

|4.22| Embedded Systems and 10T Design

(3) DCC Communication Standard

are combined into packets.
The DCC communication standard describes how bits
a as,.
The basicpacket fornat is expressed in regular expression
PSA(sD) +E

g
in
where,
a sequence of atleast 101 bits.

er
P - Preamble, which is

Packet start bit which is a 0 bit.

e
S-

in
is 8 bits
A
- Address data byte that gives the address of the unit which

ng
long.
s- Data byte start bit, which is a 0 bit.
fE
D - Data byte, which is bits long and it may contain an address,
O
instruction, data, or error correction information.
E- Packet end bit, which is a 1
bit.
g e

(4) Baseline Packet

le

A baseline packet is the minimüm packet that must be accepted by all DCC
ol

implementations. It has three data bytes:

C

() An address data byte that gives the intended receiver of

thepacket.
u

(i1) The instruction data that byte provides a basic instruction.

ad

(ii) Error. correction data byte that is used to detect and correct
iln

transmission errors.
m

4.2.4 Conceptual Specification'

Ta

a Definition:
The conceptual specification helps us to write a detailed specification that needs
tobe given to a system architect.
A train control system turns comnands into packets. A command comes from
the command unit while a packet is transmitted over the rails.
Fig 4.16 shows a generic command class and several specific commands derived
from that base class such as Set-speed, Set-inertia and Estop (emergency
stop).
<br>

Page 171l of 440

Embedded Computing
|4.23

Command

g
Set-speed Set-inertia

in
Estop
value: integer

er
value: unsigned-integer

e
Fig 4.16 Class diagramfor the train controller commcnds

in
(1) Subsystems:

ng
There are tvo najor subsystens and each of these has its own internal
structure:
fE
O
) Command unit, and
(ii) Train-board component (receiver)
g e

The basic relationship between these subsystems is illustrated in Fig 4.17

le

which shows in a UML collaboration diagram. The command unit and

ol

receiver -are each represented by the objects; the command unit sends a
C

sequence of packets to the train's receiver which is illustrated by the arrow.

u

1..n: command
ad

:Console :receiver
iln

Fig 4.17 UML collaboration diagram for major

m

subsystems of
the train controller system
Ta

The console sends all the messages, which are numbered the arrow's
messages as 1..n: Those messages are carried over the track.
O. The console needs to perform the following three functions:
on the command unit,
Read the state of the front panel
Format messages, and
Transmit messages.
O, The train receiver must also perform three major functions:

Receive the message,

<br>

Page 172 of 440

4.24 Embedded Systems and IOT Design

Interpret the message (taking into account the current speed, inertia
setting, etc.), and
Control the motor.
(2) UML Class Diagram

g
Fig 4.18 illustrates the UML class diagram which shows the console class using

in
three classes and its basic characteristics are,

er
)) The Panel class describes the command unit's front panel, which contains

e
the anialog knobs and hardware to interface to the digital parts of the

in
system.

ng
(ii) The Formatter class includes behaviors that know how to read thepanel
fE
knobs and creates a bit stream for the required message.
(ii) The Transnmitter class interfaces to analog electronics to send the message
O
along the track.
Some special classes that represent the analog componets as,
g e

(i) Knobs * deseribes the actual analog knobs, buttons, and levers on the control
le

panel.
ol

(iü) Sender* describes the analog electronics that send bits along the track.
C

Train set
Documentation
u

only

-
ad

1..t
Console Train
iln

1 1
m

1
1 1 1 1

Transmitter
Ta

Panel Formatter Receiver Controller Motor

interface

1 1 1

1 1 1

Detector Pulser
Knobs* Sender

-Physical object

Fig 4.18 A UML class diagram forthe train

controller showing the composition of tle subsystens
<br>

Page 173 of 440

Embedded Computing |4.25

Train makes use oftthree other classes that define its components:

) The Receiver class knows how to turn the analog signals on

the track into
digital form.
G) The Controller class includes behaviors that interpret the commands and
figures out how to control the motor.

g
in
(ii) The Motor interface class defines how to generate the analog signals

er
required to control the motor.

e
Two classes to represent analog components:

in
(1) Detector* detects analog signals on the track and converts them into digital

ng
form.
(ii) fE
Pulser* turns digital commands into an analog signals required to control
the motor speed.
O

4.2.5 Detailed Specification

e

a Fig 4.19 showS a class diagram for these classes which shows a little more detail
g
le

than Fig 4.18. ThePanel has three knobs:

ol

(i) Train number (which train is currèntly being controlled),

C

(i) Speed (which can be positive or negative), and

u

(iii) Inertia.
ad

Knobs* Pulser*
iln

train-knob: integer pulse-width: unsigned-integer

speed-knob: integer
m

direction: boolean
inertia-knob: unsigned-integer
emergency-stop: boolean
Ta

set-knobs()

Sender
Detector

send-bit() <integer> read-bit (): integer

control system
ig 4.19 Classes describing analog physical objects in the train
<br>

Page 174 of 440

|4.26| Embedded Systems and 10T Design

energency-stop. When we change the train

The panel also has one button for
to the proper values for
number setting, we also want to reset the other controls
are not used to change the
that train so that the previous train's control settings
current train's settings.
a that allows the rest of the
To do this, Knobs* must provide set-knobs behavior

g
in
system to modify the knob settings.
put out and
The Sender and Detector classes are relatively simple. They simply

er
to control the train
pick up a bit, respectively. The Pulser class actually used

e
in
motor's speed.

ng
Panel Motor-interface
speed: integer
panel-active( ): boolean
fE
train-number( ): integer
O
speed(): integer
inertia( ): integer
estop( ): boolean
e

new-settings( )
g
le

Fig 4.20 Class diagram for the panel and motor interface
Fig 4.20 shows the classes for the panel and motor interfaces. These classes
ol

forms the software interface to their respective physical devices. The Panel
C

class defines a behavior for each controls on the panel.

u

The Motor-interface defines an attribute for speed that can be set by other
ad

classes.
The Transmitter and Receiver classes are shown in Fig 4.21.
iln

They provide the

software interface to the physical devices that send
and receive bits along the
m

track.
Ta

Transmitter Receiver
current: command
new: boolean
send-speed(adrs: integer, read-cmd( )

speed: integer)
send-inertia(adrs: integer new-cmd (): boolean
val: integer) rcv-type(msg-type:
send-estop(adrs: integer) command)
rcv-speed(val: integer)
rcv-inertia(val: integer)

Fig 4.21 Class diagramfor the

transnitter and receiver
<br>

Page 175 of 440

Embedded Computing
4.27|
The Transmitter provides a distinct behavior for
each type of message that can
he sent and it internally takes care of formatting the message.
The Receiver clasSS
a
nrovides read-cmnd behavior to read a message
off the tracks.
The Formatter class is shown in Fig 4.22, which holds the current control
settings for all the trains. The send-command method is a utility function that

g
serves as the interface to the transmitter. The operate function performs the basic

in
actions for the object.

eer
Formatter

in
curr ent-train: integer

ng
Curr ent-speed[ntrains]: integer
curr ent-inertia[ntrains]: unsigned-integer
fE
curr ent-estop[ntrains]: boolean
O
send-command( )
panel-active( ): boolean
g e

operate( )
le

Fig 4.22 Class diagram for the Formatter class

ol

panel's values do not

C

The panel-active behavior returns true whenever the

correspond to the current values.
u

is illustrated by the
The role of the formatter during the panel's operation
ad

to the knob settings:

sequence diagram of Fig 4.23, which shows two changes
iln

emergency stop and then to the train number.

1.., speed, inertia and any
m

The panel is called periodically by the

formatter to determine whether
Ta

control settings have changed.

the current train, then the formatter decides to send a
setting has changed for
*lfa to transmitter and it takes a noticeable
Command, by issuing a send-command the
command. In the meantime, the
amount of time for the transmitter to finish that
control settings.
Tormatter continues to check the panel's
to
number bas changed, the formatter must cause the knob settings
lf train
the
get reset to the proper values for
the new train.
<br>

Page 176 of 440

4.28 Embedded Systems and 1OT Design

:Formatter :Transmitter
:Knobs :Pane!
speedlinertia/estop

Change in
control settings Read panel
panel-active
Panel settings

|send-speed,
send-command send-inertia,

g
Read pand
Panel settings send-estop

in
in

er
Change

e
Read pand
number|
Panel settings

in
ng
Change in train number Read pand
train
Panel settings
in
Change

set-knobs
fE
new-settings
Operate
O

Fig 4.23 Sequence diagram for transmitting a control input.

g e
le
ol

new-settings( )
C

)
panel-active( New train number
Idle
u

send-command()
ad

Other
iln

Fig 4.24 State diagram for theformatter operate behavior

The state diagram for a very simple version of the operate behavior of the
m

Formatter class is shown in Fig 4.24. This behavior watches the panel for
Ta

activity. If the train number changes, it updates the panel display otherwise, it
causes the required message to be sent.
Fig 4.25 shows a state diagram for the
panel-active behavior.

4 The class diagram of train's. controller class is shown in Fig 4.26. The operate
behavior is called by the receiver when it gets a new
command; operate looks al
the contents of the message and uses the issue-command
behavior to change th
setting of speed, direction, and inertia as necessary.
<br>

Page 177 of 440

Embedded Computing
4.29
Start

T current-trai n = train-knob
panel": read-knob ()
update-scr een
changed = true
F current-train I= train-knob

g
in
T
curr

er
panel": read-speed() ent-speed=throttle
changed=true

e
current-speed throttle

in
ng
panel": read-inertia( curr ent-inerti a=
inertia
fE
knob change d =true
F current-inertia = inertia-knob
O
e

T
panel": read-estop ) current-estop = estop-button -
g

value changed =true

le

F current-estop estop-button
ol

value
C

Return change d
u
ad

Stop
iln

Fig 4.25 State diagram for the panel-activate behavior

m

Controller
Ta

current-train: integer
current-speed[ntrains]: unsigned-integer
current-dir ection[ntrains]: boolean
curr ent-inertia[ntrains]: unsigned-integer

operate( )
issue-command( )

Controller class
Fig 4.26 Class diagram for the
<br>

Page 178 of 440

|4.30 Embedded Systems and 10T Design

A specification for operate is shown in Fig 4.27.

Wait for
command from
receiver

g
in
read-cmd
issue-command()

e er
in
operate behavior
Fig 4.27 State diagram for the Controller

ng
the reception of a set-speed
The operation of the Controller class during
fE
command is illustrated in Fig 4.28. The Controller's
operate behavior must
message.
execute several behaviors in order to determine the nature of the
O

has been parsed, it must send a

sequence of commands
Once the speed command
g e

to the motor to smoothly change the train's speed.

le
ol

:Receiver :Controller :Motor-interface :Pulser

C
u

new-cmd
ad

rcv-typ e
rcv-speed
iln

Set-pulsé
Set-speed
m

Set-pulse
Ta

Set-pulse

Set-pulse

Set-pulse

read-cmd operate

Fig 4.28 Sequence diagram for a set-speed command received by the train
<br>

Page 179 of 440

Embedded Computing
4.31|
4,3 TWO MARKS QUESTIONS AND
ANSWERS
Write the objectives of an
embedded system
design process.
The two major objectives an
of embedded system design process are
) It us an introduction to the
will give
various steps involved in embedded
system design before we know

g
into them in more detail.

in
(i) It will allow us to get an idea about the design methodology
itself.

er
2 Why design methodology is inportant in embedded system design

e
process?

in
design methodology is important for the following
A

three reasons:

ng
() Optimizing performance,
(ii) Automated steps. fE
(iii) Easy understanding.
O
3. Name the five basic steps involved in embedded system design process.
e

The basic steps involved in embedded system design process are,

g
le

() Requirements,
ol

(G) Specification,
C

(ii) Architecture,
u

(iv) Components, and

ad

(v) System integration.

iln

4. Write the goal of the embedded system design.

m

The major goals of the embedded system design are,

Ta

i) Manufacturing cost,
deadlines), and
(i) Performance (both overall speed and
(ii) Power consumption.
Define requirement in embedded design.
Requirement is a plain language description of what the user wants and
expects
1O get.
It may be developed in several ways:

Talking directly to customers,

<br>

Page 180 of 440

4.32 Embedded Systems and 10T Design

Talking to marketing representatives, and

Providing prototypes to the users for comment.

6. List the nonfunctional reguirements of embedded system design.

The nonfunctional requirements are,

g
(i) Performance,.

in
(ii) Cost,

er
(ii) Physical size and weight,

e
(iv) Power consumption.

in
7. Define architecture design.

ng
The architecture is a plan for the overall structure of the system that will be used
fE
later to design the components that make up the architecture. The creation of the
architecture is the first phase of what many designers think of as design.
O
8. What is UML?
e

Unified Modeling Language (UML) is an object-oriented modeling language

g

which is designed to be useful at many levels of abstraction in the design process.

le
ol

9. Define class.
A class defines the attributes that an object may have. It also defines the
C

operations that determine how the object interacts with the rest of the world.
u

A class defines both the interface for a particular type of object and also for that
ad

object's implementation.
iln

10. Differentiate object, link and association.

m

The principal component of an object-oriented design is the object. An object

includes a set of attributes that define its internal state.
Ta

A link describes a relationship between objects and association is the capture

type information about these links.

1I. List the DCC standards.

(i) Standard S-9.1
This is the DCC electrical standard that defines how bits are encoded on the rails
for transmission.
(ii) Standard S-9.2
<br>

Page 181 of 440

Embedded Computing

This is the DCC communication 4.33

standard that
information. defines
the packets that cary
12. Express the basic packet
format
in DCC standard.
The DCC communication
standard describes
The basic packet how bits are combined
format is expressed a into packets.

g
in regular expression as,

in
PSA(sD)
+E

er
where,

P. - Preamble, which is a sequence

e
in
of atleast 101 bits.
S - Packet start bit which

ng
is a 0 bit.
A - Address data byte that gives
the address of the unit which
fE
long. is 8 bits
O
S Data byte start bit, which is a 0 bit.
D - Data byte, which is 8 bits long
e

and it may contain an address,

g

instruction, data,or error correction information.

le

-
E Packet end bit, which is a 1 bit.
ol

13. What is meant by baseline packet?

C

A baseline packet is the minimum packet

that must be accepted by all Digital
u

Command Control (DCC) implementations. It has three data bytes:

ad

() An address data byte that gives the intended receiver of the packet.
iln

(ii) The instruction data that byte provides a basic instruction.

m

(ii) Error correction data byte that is used to detect and correct transmission
Ta

errors.
% What is the function of conceptual specification?

Ihe conceptual specification helps us to write a detailed specification that needs

to be given to a system architect.

4.4 REVIEW QUESTIONS

Witlh a detailed reasons and explain why design methodology is important in

embedded system design process.

<br>

Page 182 of 440

4.34| Embedded Systems and IOT Design

2. Discuss in detail about the basic steps involved in embedded system design
process.
3. List and discuss about nonfunctional requirements af embedded system design.

4. What are requirements? Discuss its contribution in embedded system design.

g
Write note on specification in embedded design process with an example.

in
S.

er
6. With an example, discuss about architecture designin embedded system.

e
-7.
Explain about sample requirements form with an example.

in
8. With neat sketches, explain about embedded system design process.

ng
9. Explain about designof model train controller with neat sketches.
fE
O
g e
le
ol
C
u
ad
iln
m
Ta
<br>

Page 183 of 440

UNIT - II
Chapter 5

g
in
ARM INSTRUCTION SETS

e er
5.1 ARM PROCESSOR

in
Introduction

ng
5.1.1
a Definition:
An Advanced
fE
RISC Machine (ARM) processor is one of a family of Central
O
Processing Units (CPUs) based on the Reduced Instruction Set Computer
(RISC) architecture for computer processors.
e

ARM processors are used in music players, smartphones, wearailes, tablets,

g

and other consumer electronic devices. This needs a very few instruction sets
le
ol

and transistors.
C

I Advantages:
The advantages of ARM processor are,
u

() Due to its very small size, it is perfectlyfitfor small-sized devices.

ad

(i) has less power consunption along with reduced complexity in its circuits.
t
iln

(ii) is easy to program at the assembly level.

I
m

ARM processor can be applied to various designs such as 32-bit devices and
embedded systems and we can even be upgraded according to the user needs.
Ta

ARM instructions are written one per lne, starting after the first column.
Comments begin with a semicolon and continue to the end of the line. A label
gives a name to a memory location, comes at the beginning of the line, starting
in the first column:

LDR r0, [r8] ;a comment

label ADD r4, r0, rl.
<br>

Page 184 of 440

Embedded Systems and 10T Design

5.2
5.1.2 Processor and Memory Organization
are identified by the number. ARM7
Different versions of the ARM architecture
uses a Harvard
is a Von Neunann architecture machine and ARM9,

architecture.

g
in
The ARM architecture supports two basic types of data:

er
Standard ARM Word is 32 bits long, and
Word may be divided into four &-bit bytes.

e
in
addresses to be 32 bits long and an address refers to a byte, not a
ARM7 allows

ng
space is at location 0, the word 1 is at 4,
word. Th word 0 in the ARM address.
the word 2 is at 8, and so on. As a result, the PC is incremented by 4.
fE in a
The ARM processor can be configured at power-up to address the bytes
O
word in either little-endian or big-endian mode, as shown in ig 5.1. Big endian
stores the Most Significant Bytes (MSBs) first, whereas litle endian stores the
g e

Least Significant Bytes([SBs) first.

le

Bit 31 Bit 0
ol

Word 4
C

Byte 3 Byte 2 Byte 1 Byte 0 Word 0

u

MSB LSB
ad

(a) Little - endian

iln

Bit 31 Bit 0
m

Word 4
Ta

Byte 0 Byte 1
Byte 2 Byte 3 Word 0

LSB MSB
(B) Big -endian
Fig 5.1Byte organizations within anARM word

5.1.2 Data Operations

In the ARM processor, arithmetic and logical operations cannot be performed
,
directly on memory locations. While some processors allow such operations to
directly link to the reference of main memory.
<br>

Page 185 of 440

ARM IAStructian Sets 5.3!

ARA is a load-siIe Gnhulecture in waish th tis opPds Pst first be ivtaked

(1) ARM Programming Model

g
in
e er
in
ng
fE
O
Rrgintet iCTSS:
g e
le
ol
C
u
ad
iln
m
Ta
<br>

Page 186 of 440

5.4
Embedded Systems and
10T Design
This register is setup automatically
during every arithmetic, logical., or
shifting operation. The top
four bits of the CPSR hold the following useful
information about the results
of that arithmetic/logical operation.
() The negative N).bit is set when the

g
result is negative in two's.

in
complement arithmetic.

er
(ii) The zero (Z) bit is set when every bit of
the result is ero.

e
(ii) The carry (C) bit is set when there is a.carry out of
the operation.

in
(iv) Thë overflow () bit is set when an arithmetic operation results in an

ng
overflow.
These bits can be used to easily check the results
fE of an arithmetic operation.
O
(2) Data Processing Instructions
e

The following instructions are used for data processing in ARM processor:
g

(i) Arithmetic Instructions,

le

(ii) Multiply instructions,

ol

(iii) Logical instructions,

C

(iv) Shift and rotate instructions,

u
ad

(v) Comparison instructions, and

(vi) Load and store instructions.
iln

Most of the data processing instructions an process one of their operands

m

using the barrel shifter.

Ta

pre-processing

Rn Pre-processing
Rm

Barrel shifter
SI
SE
No Result N

RS
Arithmetic logic unit
RS

Rd
<br>

Page 187 of 440

Sete
Instruction
RM
are 32-bit which are 5.5
All operands coming from registers
or literals and the
are placed in any register.
results
One operand to ALUis routed through
the Barrel shifter. Thus,
modified before it the operand
can be is used which is usefiul for fast multiplication
and
dealing with lists, table and other complex data structure.

g
The basic formof a data instruction is simple as,

in
er
ADD r0, rl, r2

e
This instruction sets register r0 to the sum of the values stored in rl and r2.

in
Instrüctions
) Arithmetic

ng
The arithmetic operations perfom addition and subtraction and with carry
fE
versions inchude the current value of the carry bit in the computation.
ADD Add
O

ADC Add with carry

g e

SUB Subtract
le

SBC Subtract with carry

ol

RSB Reverse Subtract

C

RSC Reverse Subtract with carry

u
ad

Rd= Rn+N
ADD Add two 32-bit values
iln

|ADC Add two 32-bit values and carry Rd= Rn +N+ carry
m

Rd= Rn-N
Ta

SUB Subtract two 32-bit values

flag)
Subtract with carry of two 32-bit values | Rd= Rn-N-!(carry
Rd=N- Rn
RSB Reverse subtract of two 32-bit values
RSC Rd= N- Rn - ! (carry flag)
Reverse subtract with carry of two
32-bit values

Rd - Destination
register
Instructions
Table 5.l Arithmetic
<br>

Page 188 of 440

Embedded Systems and 10T Design

5.6
Examples:
ADD R0, R1, R2 @ RO =R1 + R2

ADC R0, R1, R2 @RO= RI+ R2+C

@RO = RI - R2

g
SUB R0, R1, R2

in
SBC R0, R1, R2 @RO =
RI– R2-!C

er
RSB R0, R1, R2 @ RO = R2- RI

e
RSC R0, R1, R2 @ RO =R2- R1 -!C

in
ng
(i) Multiplication Instructions
instructions. Here, Rs is the
The basic,ARM provides two multiplication fE
source register and Rd and Rm cannot be the same register.
O
Multiply and accumulate Rd = (Rm * Rs) + Rn
MLA
Rs
Rd= Rm *
e

MUL Multiply
g

Table 5.2 Multiplication instructions

le

Example:
ol

MLA R4, R3, R2, RI @ R4 =R3 x R2+ RI

C

(ii) Logical Instructions

u
ad

The bit-wise logical operations perform logical AND, OR, and XOR that is,
exclusive -or (EOR) operations.
iln

Logical bitwise AND of two

32- bit values
AND Rd= Rn AND N
m

ORR Logical bitwise OR of two 32- bit values Rd = Rn ORN

Ta

EOR Logical exclusive OR of two 32- bit values Rd = Rn EORN

BIC Logical bit clear (AND NOT) Rd = Rn AND NOT N

Table 5.3 Logical instructions
Examples:
AND R0, R1, R2 @RO = R1 AND R2
ORR RO, R1, R2 @RO =RI OR R2

EOR RO, R1, R2 @RO =R1 XOR R2

<br>

Page 189 of 440

IHstruclion Sets.
ARM
5.7
RO, R1, R2 @
BIC RO
=RI AND (~R2)

)Shift and Rotate Instructions

Shifting means to move bits,
riglt and left inside an
operand.
and rotate instructionssaffect Overflow Al of the shift
Flag(0F) and Carry Flag(CF).

g
LSL Logical shift left (zero
fill)

in
er
LSR Logical shift right (zero fill)

e
ASL Arithmetic shift left

in
ng
ASR Arithmetic shift right

ROR Rotate right fE

O
RRX Rotate right extended with C
e

Table 5.4 Slhift and rotate instructions

g
le

The slhift modifier is always applied to the second source operand. The LSL
ol

and LSR modifiers perform left and right logical shifts, filling the least
C

significant bits of the operand with zeroes.

u
ad

Destination
iln

(a) LSL.
m
Ta

...0 Destination CF

(b) LSR

Fig 5.4
ARM has two arithmetic shift operations: ASL and ASR. ASL is an
arithmetic shift left by 0 to 31 places. The vacated bits at the least

SIgnificant end of the word are filled with zeros.

<br>

Page 190 of 440

Embedded Systems and 1OT Design

5.8

MSB
LSB
4
31 27

g
in
e er
ASL #4

in
.Fig 5.5

ng
ASR is an arithmetic shift right by 31 to 0
places. The vacated bits at the
most significant end of the word are fE
filled with zeros if the original value
(the source operand) was positive.
O
The vacated bits are filled with ones
if the original value was negative.
g e

MSB
le

31 27 LSB
4
ol
C
u
ad
iln

(a) ASR #4 positive value

MSB
m

31 27 LSB
dloo|d1lanodo:lo|1]olo|11]|poou1o|o|o1]
Ta

(b) ASR #4 negative value

Fig 5.6
<br>

Page 191l of 440

ARM Instruction Sets

5.9|
In ROR instruction , the bits that are
rotated off to the right end are inserted
into the vacated bit positions on the left and the
last bit rotated is also used as
the carry out.

g
Destination

in
er
Fig 5.7 ROR

e
in
MSB LSB

ng
Destination CF

Fig 5.8 RRX

fE
In RRX instruction, it rotates right by 1 bit and it is extended to carry, then
O
the carry output goes to the MSB of the register.
g e

(v) Compare (or) Comparison Instructions:

le

The conpare instructions are used to compare or test a register with a 32

ol

bitvalue. They update the CPSR flag bits according to the result, but do not
C

affect other registers.

u

After the bits have been set, the information can then be used to change
ad

program flowby using conditional execution.

iln

CMP Compare Flags set as a result of Rn -N

m

CMN Negated compare Flags set as a result of Rn +N

Ta

TST Bit– wise test Flags set as a result of Rn AND N

TE Bit- wise negated test Flags set as a result of Rn EOR N

Table 5.5 ARM compare instructions

Examples:

CMP R1, R2 @R1 -R2

CMN RI, R2 @ R1 + R2
<br>

Page 192 of 440

Embedded Systems and IOT Design

5.10|

TST R1, R2 @ RIAND R2

TEQ R1, R2 @ RI EOR R2

(vi) Move Instructions
Move is the simplest ARM instruction which copies the value (N) of
second

g
operand into Rd(destination register), where N is the register or immediate

in
value. This instruction is useful for seting an initial values and transferring

er
the data between registers.

e
MOV Move Move a 32 - bit value into a register.

in
MVNMove negated Move the NOT of the 32 - bit value into register.

ng
Table 5.6 Move instructions
fE
The MVN instruction takes the value.of second operand and performs a
O
bitwise logical NOT operation on that value, and places the result into Rd.
e

Example:
g

MOV r0, rl
le

This instruction sets the value r0to thecurrent value of rl.

ol

of
C

(vii) Load-Store lnstructions: Memory Instructions

u

LDR Load
ad

STR Store
iln

LDRH Load half- word

m
Ta

STRH Store half- word

LDRSH Load half- word signed

LDRB Load byte

STRB Store byte

ADR Set register to address

Table 5.7ARM load-store instructions

<br>

Page 193 of 440

ARM Instruction Sets

5.11|

ARM uses load-store instruction only for memory access.

LDR is used to
load something from memory into a register, and STR is used to store
something from a register toa memory address.
Examples:

g
LDR Ra, [Rb]

in
Value at [address] found in Rb is loaded into
register Ra.

er
STR Ra, [Rb]

e
in
Value found in register Ra is stored to [address] found in Rb.

ng
(a) Base-Plus -Offset Addressing
fE
This is related to indirect addressing. Here, the register value is added to
another value to form the address.
O
LDR. r0, [r1, # 16]
e

Loads ro with the value stored at the location rl+16. Here, rl is referred to as
g
le

the base and the immediate value is the offset.

ol

When the offset is an inmediate, it may have any value upto 4,096 and an
C

another register may also be used as affset. This addressing mode has two
u

other variations:
ad

(i) Auto-indexing, and

iln

(ii) Post-addressing.
m

Auto-indexing updates the base register. For example

Ta

LDR r0, [rl, #16]!

First adds 16tothe value of r1, and then uses that new value as the address.
The ! operator causes the base register to be updated with the computed
address so that it can be used again later.

Post-indexing does not perform the offset calculation until after the fetch
has been performed.
<br>

Page 194 of 440

12| Embedded Systems and 10T Design

LDR ro, r1, #16]!

#16

r1

g
rt=t+ 16

in
r0

e er
in
Fig 5.9 Auto-indexing

ng
LDR r0, [r1, #16] !

#16 fE
O
ro
g e
le

r1=r1+ 16
ol
C

Fig 5.10Post-indexing
First load r0 with the value stored at the memory location whose address is
u
ad

given by rl, and then add 16 to rl and set rl to the new value.
iln

5.1.3 Flow of Control

m

The B (branch) instruction is the basic mechanism

in ARM for changing the flow
Ta

of control. The' address that is the destination of the branch is often

called the
branch target.
The branch specifies the offset from the current
PC value to the branch target.
The offset is in words, but the ARM is byte
addressable. So the offset 1s
multiplicd by four to form a byte address:

B# 100
It will add 400 to the current PC value.
<br>

Page 195 of 440

ARM Instruction Sets

5.13|
Almost all ARM instructions including
branches have a condition field which
allows it to be executed conditionally and
data operations. Fig 5.11 summarizes
the condition codes.
31 28 24 20 12 8
Cond

g
in
er
0000 = EQ 0111 = VC

e
0001 = NE 1000 = HI

in
0010 = CS 1001 = LS

ng
0011 = CC 1010 = GE
0100= MI 1011 = LT
0101 = PL 1100 = GT
fE
0110 = VS 1101 = LE
O
EQ Equals zero Z=1
e

NE
288|85|5|9
Not equal to zero
g

Z=0
le

CS Carry set C=1

ol

CC Carry clear C=0

C

MI Minus N=1
u

PL Nonnegative (plus) N=0

ad

VS Overflow V=1
iln

VC Nooverflow V=0
m

HI Unsigned higher C=l and =0 Z

Ta

LS Unsigned lower or same C=0 or Z=1

GE Signed greater than or equal N=y
LT Signed less than NV
GT Signed greater than Z=0 and N=V
LE Signed less than or equal Z=1 or NV
Fig 5.11Condition codes in ARM
<br>

Page 196 of 440

5.14| Embedded Systems and IOT Design

statement, particularly in signal processing code.

The loop is a veryy common C
can naturally implemented using conditional branches because loops
Loops be
arrays and loops are also a good illustration of
often operate on values stored in
mode.
another use of the base-plus-offset addressing

g
(1) C Functions:

in
B(<cond>} label

er
Branch:
Branch with Link: BL{<Cond?} sub_routine_label

e
in
31 28 27 25 24 23

ng
Offset
Cond 101
Link bit 0 fE
Branch
1=Branch with link
O
Condition field

Fig 5.12 Branch instruction in CPSR

g e

ARM for procedure calls.

The branch and link instruction is used in the
le

BL foo
ol

that
This instruction and link to the code starting at location 'foo'
willperform
C

The Branclh Link (BL) instruction implements a

is, PC-relative addressing.
u

(LR) of the current

subroutine call by writing (PC+4) into the Link Register
ad

bank.
iln

;call subroutine.
BL sub
m

To return from subroutine, simply need to restore the PC from the LR.
Ta

;
MOV PC, LR return
a
The standard procedure for allowing nested procedure calls, to build stack,
as illustrated in Fig 5.13.This C code shows a series of functions that cau
other functions: f1() calls f2(), which in turn calls f3( ).

At the right side, we can see the state of the procedure call stack uring i
active
execution of f3( ).The stack contains one activation record for each
procedure.
<br>

Page 197 of 440

ARM Instruction Sets

5.15
When f3() finishes,it gets pop from the top of
the stack to get its return
address, leaving the return address for
f20 waiting at the top of the stack for
its return.

void f1(int a) {

f2(a);

g
in
f3
void f2(int r)

er
{

f3(r,5);

e
f2 Growth

in
void f3(int x, int y) {

ng
9= x+ y; f1

main () {
fE
Function call stack
f1 (xyz);
O
e

C
code
g

Fig 5.13 Nested function calls and stacks

le
ol

s Procedure Linkage:
C

Most procedures need to pass parameters into the procedure and return values
u

out of the procedure as well as remember their return address. We can also
ad

make use of the procedure call stack to pass the parameters. The conventions
used to pass values into and out ofprocedures are known as procedure linkage.
iln

The compiler passes parameters and return variables in a block of memory

m

known as a frame which is also used to allocate local variables.

Ta

The stack elements are frames. A Stack Pointer (SP) defines the end of the
current frame, while a Frame Pointer (FP) defines the end of the last frame.
When a new procedure is called, the SP and FP are modified to push another
frame onto the stack.
(2) ARM Procedure Call Standard (APCS)
The APCS is a good illustration of a ypical procedure linkage mechanism:
<br>

Page 198 of 440

|5.16| Embedded Systems and IOT Design

parameters into the procedure. ro is also

r0 -r3: Used to pass the first four
more than four parameters are
used to hold.the return value. If
required, then they are put on the stack frame.
r4 - r7: Hold register variables.

g
rll :Frame pointer.

in
:
r13 Stack pointer.

er
to check for
r10 : Holds the limiting address on stack size, which is used

e
stack overflows.

in
uses in the protocol.
Other registers have additional

ng
5.1.4 Advanced ARM Features
features for a variety of
Several models of ARM processors provides advancedfE
applications:
O
(i) Digital Signal Processing (DSP)
of ARM that provides improved DSP. Multiply Accumulate
e

Several extensions
g

x or 32 x16 MAC in one clock cycle.

(MAC) instructions can perform a 16 16
le

Single-Instruction Multiple Data (SIMD)

ol

(ii)
is
Multimedia operations are supported by SIMD operations. A single register
C

treated as several smaller data elements, such as bytes. The same operation
is
u

simultaneously applied to all the elements in the register.

ad

(iii) NEON Instructions

iln

NEON is the ARMv8 version of SIMD. The NEON unit has 32 registers and
each 64 bits wide. Some operations also allow a pair of registers that is to be
m

treated as a 128-bit vector.

Ta

Data in a single register are treated as a vector of elements and each smaler
than the original registe, with the same operation being performed in parallel
on each vector element.

(iv) Trust Zone

Trust Zone extensions provide security features. A separate monitor mode alloW
the processor to enter a secure world to perform operations which is not permitted
in the normal mode.

A
<br>

Page 199 of 440

ARM Instruction Sets

5.17
(v) Jazelle
The Jazelle instruction set allows direct execution of 8-bit Java'M bytecodes that
is, no need to execute the Java programs.

(vi) Cortex

g
Cortex-A5 provides Jazelle execution of Java, floating-point processing,

in
and NEON multimedia instructions.

er
Cortex-A8 is a dual-issue in-order superscalar processor.

e
Cortex-A9 can be used in a multiprocessor with four processing elements.

in
Cortex-A15 is a Multicore Processor Core(MP) with up to four CPUs.

ng
Cortex-R family is designed for real-time embedded computing.
fE
Cortex-M family is designed for microcontroller-based systems that
requires low cost and low-energy operation.
O
5.2 PRELIMINARIES
g e

5.2,1 Computer Architecture Taxonomy

le

(1) Von Neumann Architectures

ol
C
u

Address
ad

CPU
Data
iln

Memory
m

ADD r5, r1, r3 PC

Ta

Fig 5.14 A Von Neumann Architecture Conputer

A block diagram of Von Neumann architecture computer is shown in Fig
5.14. The computing system consists of a Central Processing Unit (CPU)
and a memory.
A
computer whose memory holds both data and instructions is known as a
Von Nemann maclhine.
<br>

Page 200 of 440

5.18 Embedded Systems and 10T Design

store
values used internally.
The CPUhas several internal registers that
in memory of an
Program Counter (PC) is a register which holds the address
memory, decodes the
instruction. The CPU fetches the instruction from
instruction, and executes it.

g
only we can change what the CPU does.
If you change the instructions, then

in
er
(2) Harvard Architectures:
Address

e
in
Data memory
CPU
Data

ng
Address
fE PC
Program memory
Instructions
O
Fig 5.15A Hardvard architecture
Harvard architecture is shown in Fig 5.15 which has separate memories for
g e

memory.
data and program. The PC points the program memory, not data
le

Therefore, it is harder to write self-modifying programs on Harvard machines.

ol

Due to the separation of program and data memories, it provides kigher

C

performance for digital signal processing. Data sets that arrive contimuously
and periodically are called streaning ata. Two memories with separate
u

ports provide Iigher memory bandwidth.

ad

(3) RISC vs CISC

iln

Many early computer architectures are Complex Instruction Set Computers

(CISC) which provides a variety of instructions that may perform very'
m

complex tasks and they also generally used a number of different instruction
Ta

formats of varying lengths.

Here, a single instruction, will do all loading, evaluating, and storing
operations and hence it's complex.
The advances in the development of high-performance microprocessors using
the concept of Reduced Instruction Set Computers (RISC) which uses the
fewer and simpler instructions.
In RISC, a simplify hardware is obtained by using an instruction set
composed of a few basic steps for loading, evaluating, and storing operations
just like a load comnand willload data, a store comnand will store the daa.
<br>

Page 20lof 440

ARM Instruction Sets

5.19|
(4) Instructions Set Characteristics
o The instruction set
of the computer defines. the interface between software
modules and the underlying hardware. The instructions
define what the
hardware will do under certain circumstances.

g
o The characteristics of instructions are as follows:

in
Fixed versus variable length,

er
Addressing modes,

e
- Numbers

in
of operands, and

ng
-Types
of operations supported.
(5) Worá Length fE
We can characterize architectures by their word length: 4-bit, 8-bit, 16-bit,
O
32-bit, and so on. In some cases, the length ofa data word, an instruction, and
e

an address are the same.

g

Generally, the computers are designed to operate on smaller words,

le

instructions and addresses may be longer than the basic data word.
ol
C

(6) Little-endian vs. big-endian

u

MSB LSB
ad

Byte 3Byte 2Byte 1 Byte 0

iln

High Address High Address

m

Byte 3 Byte 0
Ta

Byte 2 Byte 1

Byte 1 Byte 2

Byte 0 LSB MSB Byte 3

Low Address
Low Address

Little Endian .Big Endian

LSB is at least address MSB is at least address

Fig 5.16 Litle-endian and big-endian

<br>

Page 202 of 440

5.20
Embedded Systems and IOT Design

A big-endian system stores the Most Significant Byte

(MSB) of a word at the
Smallest memory address and the Least Significant Byte (LSB) at the largest.
A little-endian system, in contrast, stores the LSB at the smallest address.

(7) Instruction Execution

g
in
o A
single-issue processor executes one instruction at a time. Although it may

er
have several instructions at different stages of execution, only one instruction

e
can be at any particular stage of execution. In multiple-issue processor,

in
multiple instructions are executed at a time.

ng
A superscalar processor can execute more than one instruction during a
fE
clock cycle by simultaneously dispatching multiple instructions to different
execution units on the processor. Therefore, it allows more throughputs.
O
Limitations:
e

The limitations of the superscalar process are

g

(i) It uses too.much energy,

le

(ii) Difficulty of scheduling instruction becomes complex,

ol
C

(ii) It is too expensive for widespread use in embedded systems.

u

a VLIW:
ad

Very Long Instruction Word (VLI) processor uses

instruction level
iln

parallelism, ie, it has programs to control the parallel execution of the

instructions. It relies on the compiler to determine what conbinations
m

of

instructions can be legally executed together. VLIW processors are often used
Ta

in high-performance embedded computing.

The set of registers available for use by the programs is .called the
programming model and also known as the programmer mnodel.
(8) Architectures and Implementations
There may be several different implementations of architecture. Different CPS
may offer different clock speeds, diferent cache configurations, changes to the
bus or interrupt lines, and many other changes that can make one model of CPU
more attractive than another for any given application.
<br>

Page 203 of 440

ARM Instruction Sets 5.21

(9) CPU s and Systems
The CPUis only part of a complete computer system. In addition to the
memory, we also need I/O devices to build a useful system.
We can build a
computer from several different chips, but many useful computer systems
come on a single chip

g
in
A microcontroller is one form of a single-chip computer that includes a
processor, memory,and I/0 devices. The term microcontroller is usually used

er
to refer to a computer system chip with a relatively small CPU that includes

e
some read-only memory for program storage.

in
A System-on-Chip (So) generally refers to a larger processor that includes

ng
on-chip RAM that is usually supplemented by an off-chip memory.

5.2.2 Assembly Languages

fE
O
Definition:
e

Anassembly language is a type of programming language that translates high

g

level language into machine language. It is a necessary bridge between sofiware

le

programs and their underlying hardware platforms.

ol

labell ADR r4, c

C

LDR r0, [r4] ;a comment

u
ad

ADR r4, d
iln

LDR rl, [r4]

m

;
SUB r0, r0, rl another comment
Ta

Fig 5.16An example of ARMassembly language

4 Fig 5.16 shows a part of ARM assembly code which reflects the basic features
of assembly languages:
One instruction appears per line.
- Labels: Give names to memory locations and start in the first column.
- Instructions must start in the second column.

Comments run from some designated comment character to the end the line.
of
<br>

Page 204 of 440

5.22 Embedded Systems and 10T Design

(1) ARM Data Processing Instruction Format: .

(imm8), and
Data-processing instructions have a 8-bit unsigned immediate
4-bit rotation' (rot); An imm8 is rotated right
to create a 32-bit constant.
. 11
16 15 12

g
31 28 27 26 25 24 21 20 19

in
Format determined
Cond 00 OPCode Rn Rd by Ibit (Operand 2)

e er
in
Immediate
Condition operand -Destination register

ng
field

Operation
code
fE First Operand register.
(Source Register Operand)
O
Set condition codes
0= Do not alter condition codes
e

1= Set condition codes

g
le

|=1 (represents operand 2):

ol

11-8 7-0
C

# rot 8- bit immediate

u
ad

(a) Immediate
I=0 format:
iln

11-8 6-5 4 3-0

m

# shift Sh
Ta

Rm

(b) Register

11 -8 7 4
6-5 3 -0
Rs 0 Sh Rm

(c) Register - shifted register

Fig 5.17 Format of

anARM data processing instruction
<br>

Page 205 of 440

ARM Instruction Sets 5.23|

Data processing instructions perform move, arithmetic, logical, compare

and
multiply operations. All instruction operations are carried out in ALUexcept
multiply instructions which are carried out in multiplier
block.
Data processing instructions are not access memory. Instructions operate on
two 32-bit operands and produces 32-bit result.
Instructions can pre-process

g
one operand using barrel shifter.

in
er
Examples:

e
Operand Addressing

in
Mode Example Description

ng
-
Register only ADD R3, R2, R1 R3 4- R2 + R1

Immediate SUB R3, R2, #25

fE R3 4- R2 - 25
O

5.2.3 VLIW Processors

g e

The performance of the processor is improved by using either of the following

le

methods:
ol

() Pipelining: Break the instruction into subparts,

C

(ii) Superscalar processor: Independently execute the instructions in different

u

parts of the processor.

ad

(ii) Out-of-order-execution: Execute orders diferently to the program.

iln

But cach of these methods add to the complexity of the hardware very much.
m

This is overcome by VLIW processors.

Ta

Very Long Instructions Word (LIW) processors has programs to control the
parallel execution of the instructions. These processors rely on the compiler to
identify the sets of instructions that can be executed in parallel.

The programs decide the parallel flow of the instructions and to resolve conflicts.
This increases the compiler complexity but decreases the hardware complexity
by a lot.
<br>

Page 206 of 440

|5.24 Embedded Systems and IOT Desigy

The main goal of VLIWis to remove the complicated instruction scheduling and
parallel dispatch that appears in most modern microprocessors. A VLIW
processor needs to be quicker and less costly than a comparable RISC chip.

* Fig 5.18 shows the VLIW architecture, the multiple functional units share a
common multi-ported register file for fetching the operands and storing the

g
results.

in
Parallel random access by the functional units to the register file is facilitated by

er
the read/vwrite crossbar. Execution of the operations in the functional units is

e
carried out concurrently with the load/ store operation of data between a RAM

in
and the register file

ng
Multiported Register Fil
fE
O
e

Program
Read /Write Corss Bar
g
le

Control
ol
C

Unit Functional Functional

Unit 1 1
Unit
u
ad
iln

Instruction Cache
m

Fig 5.18 VLIW architecture

Ta

(1) Packets
set of instructions is bundled together into a VLIW packet, which a set oj
A

is
instructions that may be executed together.
The execution of the next packet will not start until all the instructions the
in
current packet have finished exxecuting. The compiler
identifies packets by
analyzing the program to determine the sets of instructions that can alwayS
execute together.
<br>

Page 207 of 440

ARM Instruction Sets 5.25|

i2)
Inter-instruction Dependencies
oA data dependency is a relationship between the data operated on by
instructions. For example in Fig 5.19, the first instruction writes into ro while
the second instruction (r2) reads from it.

ro

g
r1

in
er
add ro, r1, r2 r3

e
add r3, r0, r4

in
r2
Instructions

ng
fE r4
O
Data dependencies

Fig 5.19 Data dependencies and order of instruction execution

e

As a result, the first instruction must finish before the second instruction can
g
le

performs its addition. This data dependency graph shows the order in which
ol

these operations must be performed.

C

r1 r1 r4 2 r5
u

add ro, r1, r2

ad

add r1, r4, r3

add r2, r5, r4
iln

r3 r4
Instructions 2
m

Fig 5.20 Instructions without data dependencies

Ta

Fig 5.20 shows that these instructions

use common input registers but the
instruction.
result of one instruction does not affect the result of the other

(3) VLIW vs.Superscalar

Architecture Advantages Disadvantages
hardware Complex compilers are
Reduces
complexity. required.
Reduces power Increased program code
consumption. size.
<br>

Page 208of 440

5.26 Embedded Systems and 10T Design

Simplifies decoding and Larger memory bandwidth

instruction issues. and register -file
VLIW
Increases potential clock 'bandwidth.
rate. Unscheduled events.

g
Improves performance by Dependency checking

in
executing multiple between instructions is
instructions per

er
clock cycle. required.
Superscalar
Reduces hardware -
Out of- order execution

e
complexity. leads to more complexity.

in
Enhances instruction

ng
throughput.

(4) VLIW and Embedded

Computing
fE
O
A number of different processors have implemented
VLIW execution modes,
and these processors have been
e

used in many embedded computing systems.

g

VLIW is very well suited to many

signal processing and multimedia
le

applications. Channel processing is

easily mapped onto VLIW processors
ol

because there are no data dependencies

between the different signal channels.
C

5.3 TWO MARKS QUESTIONS AND

ANSWERS
u

1. Define ARMprocessor.
ad

An Advanced RISC Machine

(ARM) processor is one
of a family of Central
iln

Processing Units (CPUS) based on

the Reduced Instruction Set Computer
architecture for computer processors. (RISC)
m

ARM processors are used in

Ta

music players, smartphones, wearables,

other consumer electronic devices. tablets, and
This needs a very few instruction
transistors. sets and

2. Mention the advantages of ARMprocessor.

The advantages of ARM processor
are,
(i) Due to its very small size, it is perfectly
fit for small-sized devices.
(ii) It has less power consumption
along with reduced complexity
(iii) It is easy to program at in its circuits.
the assembly level.
<br>

Page 209 of 440

(nstruction, Sets
5.27|
Name the basic types
of
data supported
by ARM architecture.
ARM. architecture supportstwo
The basic types of
data:
Standard ARM word is
32 bitslong, and
- Word may be divided into four 8-bit bytes.

WhyaARMprocessor called as load-store

4 architecture?

g
ARM load-store architecture
is a
in which the data operands must

in
first be loaded
intothe CPU and then stored back to main memory save
to the results.

er
Define CPSR.

e
The basic

in
register in the programming model is the Current
Program Status

ng
Register (CPSR) Which is used by the ARM core to
monitor and control the
internal functions, This register is setup automatically
during every arithmetic,
fE
logical, or shifting operation.
O
6 List the aritlhmetic instructions in ARMprocessor.
e

ADD Add
g

ADC Add with carry

le

SUB Subtract
ol

Subtract with carry

C

SBC

RSB Reverse Subtract

u
ad

RSC Reverse Subtract with carry

iln

1. Define ROR.
are rotated off to the right end are
m

Kotate Right (ROR) instruction, the bits that

An

is also
vacated bit positions on the left and the last bit rotated
Ta

Mserted into the

used as the carry
out.

Destination

8, What
is RRX?
it rotates right by 1 bit and is
it
In Rotate
right extended with C(RRX) instruction,
extended goes to the MSB of the register.
to
carry, the carry output
then
<br>

Page 210 of 440

5.28 Embedded Systems and IOT Design

MSB LSB

Destination CF

9. What is the needfor compare instructions?

g
The compare instructions are used to compare or test a register with a 32-bit

in
value. They update the CPSR flag bits according to the result, but do not affect

er
other registers.

e
in
After the bits have becn set, the information can then be used to change program

ng
flow by using conditional execution.
10. List the compare instructions. fE
CMP Compare Flags set as a result of Rn -N
O
CMN Negated compare Flags set as a result of Rn + N
e

Bit- wise test Flags set as a result of Rn AND N

g

TST
le

TEQ Bit- wise negated test Flags set as a result of Rn EOR N

ol

10. Mention the need of branch instruction in ARM processor.

C

The B (bränch) instruction is the basic mechanism in ARM for changing the flow
u

of control. The address that is the destination of the branch is often called the
ad

branch target.
iln

The branch specifies the offset from the current PC value to the branch target.
m

The offset is in words, but the ARM is byte addressable. So the offset 1s
Ta

multiplied by four to form a byte address:

B# 100
It willadd 400to the current PC value.
12. Write the function of branch link instruction.
The Branch Link (BL) instruction implements a subroutine
call by writns
(PC+4) into the Link Register (LR) of the current bank.
BL sub ;call subroutine.
To return from subroutine, simply need to restore the PC from the LR.
<br>

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ARM Instruction Sets

5.29
MOV PC, LR ; return

13. Define procedure linkage.

Most procedures need to pass parameters
into the procedure and return values
out of the procedure as well as
remember their return address. We can also
use of the procedure make
call stack to pass the parameters. The conventions
pass values into used to

g
and out of procedures are known as procedure linkage.

in
14. What is frame?

er
The compiler passes parameters and return variables
in a block of memory

e
known as a frame which is also used to allocate local variables.

in
15. Diferentiate SP and FP.

ng
The stack elements are frames. A Stack Pointer (SP) defines
the end of the
current frame, while a Frame Pointer (FP) defines the end
fE of the last frame.
When new procedure is called, the SP and FP are modified to push another
O
frame onto the stáck.
16. List the features of ARM processors.
g e

Several models of ARM processos provide advanced features for a variety of

le

applications:
ol

) Digital Signal Processing (DSP)

C

(ii) Single-Instruction Multiple Data (SIMD)

u

(iii) NEON Instructions

ad

(iv) Trust Zone

iln

(v) Jazelle
m

(vi) Cortex
Ta

17. What is Von Neumannmachine?

The computing system consists of a Central Processing Unit (CPU) and a
memory. A computer whose memory holds both data and instructions is known
as a Von Neumann machine.

18. What is meant by Harvard architecture?

Harvard architecture has separate memories for data and program. Due to
separation of program and data memories, it provides higher performance for
digital signal processing.
<br>

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Embedded Systems and 1OT Desion

5.30

19. Compare the features

of
RISCand CISC architectures. [APRMAY-2023/
(Complex Instruction Set
RISC (Reduced Instruction Set Computing) and CISC
a
are two different approaches to designing the instruction set of
Computing)
CPU(Central Processing Unit).
RISC processors are characterized by.having. a small, highly optimized

g
that they
This means they have a smaller number of instructions

in
instruction set.
very fast and
these instructions is designed to be

er
can execute, but each of

e
efficient.
more complex instruction set.

in
CISCprocessors are characterized by a larger and
faster
uses many memory references process complex instructions. RISC has

ng
It
processing, while CISC has slower processing.
20. Differentiate between big endian and little endian.
fE
A big-endian system stores the Most Significant Byte (MSB) of a word at the
O
smallest memory address and the Least Significant Byte(LSB) at the largest. A
e

little-endian system, in contrast, stores the LSB at the smallest address.

g

Bit 0
le

Bit 31

Word 4
ol

Byte 1. Byte 0 Word 0

C

Byte 3 Byte 2

LSB
u

MSB
(a) Little- endian
ad

Bit 31 Bit 0
iln

Word 4
m

Byte 0 Byte 1
i Byte 2 Byte 3 Word 0
Ta

LSB MSB
(b) Big - endian

21. Define instruction set.

The instruction set of the computer defines the interface between software
modules and the underlying hardware. The instructions define what. the hardware
will do under certain circumstances.
22. List the characteristics of instructions.
The characteristics of instructions are as follows:
<br>

Page 213 of 440

ARM Instruction Sets

5.31
Fixed versus variable length,
Addressing modes,
-
Numbers of operands, and
Types of operations supported.
23. What is superscalar processor?

g
in
superscalar processor can execute more than one
A

instruction during a clock

er
cycle by simultaneously dispatching multiple
instructions to different execution
units on the processor. Therefore,

e
it allows more throughputs.

in
24. Write the limitations of
'superscalarprocessor.

ng
The limitations of the superscalar process are
(i) It uses too much energy, fE
(ii) Difficulty of scheduling instruction becomes complex,
O
(i) It is too expensive for widespread use in embedded systems.
e

25. What do you mean by VLIWprocessor?

g
le

Very Long Instruction Word (VLIW) processor uses instruction level

parallelism, i.e. it has programs to control the parallel execution of the
ol

instructions. It relies on the compiler to determine what combinations of

C

instructions can be legally executed together.

u

VLIW processors are often used in high-performance embedded computing.

ad

26. What is meant by programming mdel?

iln

The set of registers available for use by the programs is called the programming
m

model and also known as the programmer model.

Ta

27. Define SoC.

A System-on- Chip(SoC) generally refers to a larger processor that includes on

chip RAM that is usually supplemented by

an off-chip memory.

28. Write language.

thefunction of assembly
An assembly language is a type of programming language that translates high
level language into machine language. It is a necessary bridge between software
programs and their underlying hardware platforms.
<br>

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12 Embedded Systems and IOT Design

List the basic features of assembly languages.

The basic features of assembly languages:
One instruction appears per line.
start in the first column.
- Labels: Give names to memory locations and

g
in
- Instructions must start in the second column.
comment character to the end of the line.

er
Comments run from some designated
format of ARM dataprocessing instruction.

e
0. Draw the

in
21 20 19 16.15. 12 11
31 28 27 26 25 24

ng
Format determined
Cond 00 OPCode S Rn Rd by Ibit (Operand 2)
fE
Immediate
O
Condition operand Destination register
field
g e

Operation First Operand register

le

code (Source Register Operand)

ol

Set condition codes

0= Do not alter condition codes
C

1=Set condition codes

u

31. What do you mean by VLIW packet?

ad

a
A set of instructions is bundled together into a VLIW packet, which is set of
iln

instructions that may be executed together.

m

32. Define data dependency.

A data dependency is a relationship between the data operáted on by instructions.
Ta

33. Give the comparisons of VLIW and superscalar processors.

Architecture| Advantages Disadvantages
VLIW Reduces hardware Complex compilers are
complexity. required.
Reduces power Increased program code
consumption. size.
Simplifies decoding and
Larger memory bandwidth
instruction issues.
and register -file
bandwidth.
<br>

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ARM Instruction Sets

5.33
Increases potential clock
Unscheduled events.
rate.
Superscalar Improves performance by
executing multiple Dependency checking
between instructions is
instructions per clock cycle.
required.

g
Reduces hardware -
Out of- order execution

in
complexity.
leads to more complexity.

er
Enhances instruction
throughput.

e
in
34. Write tlhe advantages of VLIWprocessor.
The advantages

ng
of VLIW processor are,
) Reduces hardware complexity.
fE
(ii) Reduces power consumption.
O
(iii) Simplifies decoding and instruction issues.
(iv) Increases potential clock rate.
g e
le

5.4 REVIEW QUESTIONS

ol

1. With neat sketches, explain in detail about ARM processor.

C

2. Explain about data operations in ARM processor.

u

3. Discuss in detail about the data processing instructions with examples.

ad

4. Write note on
iln

() Auto-indexing addressing.
m

(i) Post-indexing addressing.

Ta

S, Explain about flow of

control in ARMprocessor.
6. List and discuss about advanced ARMfeatures.
7. Discuss about computer architecture taxonomy with neat diagrams.
8. Write note on VLIW processors.
<br>

Page 216 of 440

UNIT-II
Chapter 6

g
in
CPUs

eer
6.1 PROGRAMMING INPUT AND OUTPUT

in
ng
6.1.1 Input and Output Devices
fE
O
Status
register
e

CPU Device
g

mechanism
le

Data
ol

register
C
u

Fig 6.1 Structure ofa Typical VO Device

ad

some analog or non-electronic

the input and output devices have
Usually,
iln

a typical IO device and its

components. Fig 6.1 shows the structure of
m

relationship to the CPU.

is a set of registers.
The interface between the CPUand the device's internals
Ta

and readhwrite electronics

Examples of. device's internals are the rotating disk
writing the
in a disk drive. The CPU interact to the device by reading
and

registers. Devices have typically several registers:

as
are treated as data by the device, such the
() Data registers hold values that
data read or written by a disk.
(ii) Status registers provide information about the device's operation,
such as

whether the current transaction has completed.

<br>

Page 217 of 440

6.2 Embedded Systems and IOT Design

Some registers may be read-only, such as a status register that indicates when
the device is done, while others may be readable or writable.

6.1.2 Input and Output Primitives

In microprocessor system, there are two methods of interfacing input/output
a

g
in
(I/O)devices:

er
)Memory-mapped I/0, and

e
(ii) I/Omapped I/O.

in
a Memory-Mapped i/0:

ng
In memory-mapped I/O, inputloutput devices are mapped to the memory
fE
address space of the microprocessor. This means that the I/O devices are
treated like memory locations and can be accessed using the same read and
O
write instructions as memory.
e

In other words, the same bus and control signals used for memory access are
g

used for I/Oaccess as well.

le
ol

a /O Mapped i/0:
C

In I/O mapped VO, input/output devices are mapped to a separate I/O

u

address space which is different from the memory address space. The
ad

microprocessor uses special instructions to access the VO devices using

specific I/O address signals, which are separate from the memory address
iln

signals.
m
Ta

6.1.3 Busy-Wait I/0

The simplest way to communicate wilth devices in aprogram is busy-valt
IVO. Devices are typically slower than the CPU and may
require many cycles t0
complete an operation.

If the CPUis performing multiple operations on a single device, such as

writin
several characters to an output device, then it must wait for
first operation
complete before starting the next one.
<br>

Page 218 of 440

PUs 6.3

.1.4 Interrupts
The interrupt mechanism allows devices to signal the CPU and to force execution
of a particular piece of code.
When an interrupt occurs, the Program Counter's value is changed to point to an

g
interrupt handler routine which is also commonly known as a device driver that

in
takes care of the device: writing the next data, reading the data that have just

er
become ready, and so on.

e
in
ng
Interrupt request Status
register
fE
CPU Interrupt acknowledge Device
PC
O
mechanism

Data /address Data

e

register
g
le

Device :,
ol
C

Fig 6.2 The interrupt mechanism

u

Fig 6.2 shows the interface between the CPU and VO device includes several
ad

signals that control the interrupt process:

iln

VO device asserts the interrapt reguest signal when it wants service from
the CPU, and
m

CPU asserts the interrupt acknowledge signal when it is ready tohandle the
Ta

VO evice's request.
* The I/O device's logic decides when to interrupt. The program that runs when
no interrupt is being handled is often called the foreground program.

* The CPU implements interrupt by checking the interrupt request line at the
beginning of execution of every instruction. If an interrupt request has been
asserted, the CPU does not fetch the instruction pointed to by the PC.
<br>

Page 219 of 440

6.4| Embedded Systems and 10T Desien

A Interrupts and Subroutines

every instruction, it can respond quickly to
The CPU checks for interrupts at
service requests from devices. The interrupt
handler must return to the
foreground program without disturbing the foreground
program's operation.

g
is typically a

in
The subroutine call mechanism in modern microprocessors
return address on a stack.

er
stack, so the interrupt mechanism puts the

e
(1)Priorities and Vectors

in
some
o Most of the systems have more than one I/Odevice, so that there must be

ng
mechanism for allowing multiple devices to interrupt.
o There are two ways to handle multiple devices which provides more flexible for
fE
the associated hardware and software:
O
(i) Interrupt priorities allows the CPU to recognize some interrupts as more
important than others, and
g e

(ii) Interrupt vectors allow the interrupting device to specify its handler.
le

Interrupt acknowledge log2 n

ol
C
u

Device 1 Device 2 Device n

ad
iln
m

...
Ta

L1 L2 Ln

CPU

Fig 6.3 Prioritized device interrupts

o Fig 6.3 shows that the
CPUprovides several different interrupt request sig
such as LI, L2, upto Ln. Typically, the lower-numbered
interrupt lines u

given higher priority.

<br>

Page 220 of 440

CPUs
6.5
o If devices. 1,2, and n all requested the interrupts simultaneously. The first
request would be acknowledged because it is
connected to the highest-priority
interrupt line.

A Masking:

g
The priority mechanism must ensure that a lower-priority
interrupt does not

in
occur when a higher-priority interrupt is
being handled, then the decision process

er
is known as masking.

e
When an interrupt is acknowledged, then the CPU stores the priority level of

in
that interrupt in an internal register. Ifa subsequent interrupt is received, then

ng
its priority is checked against the priority register.
fE
If the new request has higher priority than the currently pending interrupt then
only it is acknowledged. When the interrupt handler exits, then the priority
O
register must be reset.
g e

A Power -down Interrupts: NMI

le

The highest-priority interrupt is normally called as Non-Maskable Interrupt

ol

(NMI). It is usually reserved for interrupts caused by the power failures which
C

cannot be turned off.

u

NMI interrupt handler can be used to save critical state in nonvolatile

ad

memory. It turn off VO devices to eliminate spurious device operation during

iln

power down, and so on.

m

(2) Interrupt Vectors

Ta

Interrupt vectors provides the ability to define the interrupt handler that
more flexibility.
should service a reguest from a device, which is
Fig 6.4 shows the hardware structure required to suport interrupt vectors. In
addition to the interrupt request and acknowledge lines, an interrupt vector
lines run from the devices to the CPU. After a device's request is
acknowledged, it sends its interrupt vector over those lines to the CPU.
<br>

Page 221l of 440

6.6 Embedded Systems and 10T Design

a memory
The CPUthen uses the vector number as an index in table stored in
as shown in Fig 6.4. The location referenced in the interrupt vector table by

the vector number gives the address of the handler.

Vector

g
Device Interrupt vector
Vector 0

in
1
table head Handler
Handler 3 Vector 1

er
Interrupt
request Interrupt
ackno wledge Handler 4 Vector 2

e
Vector 3

in
Handler 2
CPU.

ng
Interrupt vector table

Hardware structure fE
Fig 6.4 Interrupt vectors
O
(3) Interrupt Overhead
g e

Once a device requests an interrupt, the following steps are performed by the
le

CPU and some other device by the software:

ol

(i) CPU:
C

The CPU checks the pending interrupts at the beginning of an instruction to find
u

the highest-priority interrupt and gives it to the interrupt priority register.

ad

(i) Device:
iln

The device which receives the acknowledgment sends its

m

interrupt vector to the

CPU.
Ta

(iüi) CPU

The CPU looks up the device handler address in the interrupt vector
table
using this vector as an index.
A subroutine-like mechanism is used to save the current value
of the PC and
possibly other internal CPUstate, such as general purpose registers.
<br>

Page 222 of 440

CPUs
6.7
(iv) Software:
The device driver may save additional CPUstate, then it performs the required
onerations on the device which restores any saved state and executes the interrupt
return instruction.
(v) CPU:

g
The interrupt return instruction restores the PC and other automatically saved

in
states in order to return the execution to the code that was interrupted.

er
(4) Interrupts in ARM:

e
in
The ARM processor has two levels of external interrupt:

ng
() Fast Interrupt Requests (F1Qs), and
(i) Interrupt Requests (IRQs). fE
Fast Interrupt Requests (FIas):
O
FIQ is aspecialized type of interupt request, which is a standard technique
e

as
-usedin computer CPUs to deal with events that need to be processed they
g

occur, such as receiving data from a network card, or keyboard or mouse

le

actions.
ol

FIQs is a fast and low-latency interrupt handler.

C
u

A Interrupt Requests (IRQS)

ad

An IRO is a signal sent to a computer's processor to momentarily stop

a device to
(interrupt) its operations. The signal is usually sent by hardvare
iln

some time to run its own

interrupt the processor so that the device gets
m

operation.
Ta

to an interrupt:
The ARM7 performs the following steps when responding
return.
() Saves appropriate value of the PC to be 'used to
the
(SPSR),
- (ii) Copies the CPSR into an Saved Program Status Register
(iii) Forces bits in the CPSR to note the interrupt, and
vector.
(iv) Forces the PCto the appropriate interrupt
<br>

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6.8 Embedded Systems and 10T Design

6.2 SUPERVISOR MODE

6.2.1 ARM Operating Modes
The ARM processor has seven different modes of operation. Each ARM
operating mode has a specific purpose, and only one mode is active at any one

g
moment.

in
er
Mode Privileged Purpose

e
User No
|Normal operating mode for most programs

in
(tasks).

ng
|Fast Interrupt
Yes Used to handle a high-priority (fast) interrupt.
Request (FIQ) fE
|Interrupt Request Used to handle a low-priority (normal)
O
Yes
(IRQ) interrupt.
e

Used when the processor is reset, and to

Supervisor Yes
g

handle the software interrupt instruction: SWI

le

Abort Yes Used to handle memory access violations.

ol
C

Used to handle undefined or unimplemented

Undefined Yes
instructions.
u
ad

|Systen Yes Uses the same registers as user mode.

iln

Table 6.1 ARM operating modes

a
m

Definition:
Ta

Supervisor mode is an automatic selected mode when a computer is powered

on that is, a processor enters supervisor mode on reset.
When a program is in user mode, wants to execute a privileged task, jor
example allocating more memory, it needs to make a system call. So thal,
the operating system performs instructions to do the privileged task, which is
achieved, by the program executing the supervisor call (SVC) instruction.
<br>

Page 224 of 440

CPUs
6.9
The operating system
of a computer usually operates in this mode.
mode helps in preventíng Supervisor
applications from corupting
the data of the operating
system.

Features:
Some of the important features

g
of supervisor mode are as follows:

in
() It handles different types of commands but mostly deals with privileged

er
instructions.

e
(i) The operating system selects supervisor mode

in
for the low level tasks that
require complete access to the system hardware.

ng
(ii) It cancreate the memory address spaces as well as updating them.
fE
(iv) Various interrupts can be enabled or disabled using the supervisor mode.
O
It also contributes to the loading of the processor status.
supervisor mode can access the various data structures available inside
e

(v) The
g

the operating system.

le

# In ARM, Software Interrupt(SWI) instruction puts the CPU in supervisor mode:

ol

SWI CODE_1
C

* In supervisor mode, the bottom five bits of the CPSR are all set to 1 to indicate
u

that the CPU is in supervisor mode. The old vaue of the CPSR just before the
ad

SWI is stored in a register is called the Saved Program Status Register (SPSR).
iln

The supervisor mode SPSR is referred to as SPSR_svc. To return from the

m

supervisor mode, it restores the PC from register rl4 and the CPSR from
Ta

SPSR SVC.

6.3 EXCEPTIONS

6.3.1 Introduction
A Definition:
exception is an internally detectèd error. This mechanism provides a
way for
An

tne program to react for an unexpected event.

<br>

Page 225 of 440

|6.10 Embedded Systems and I0T Design

Processor exceptions occur when this normal flow of execution gets diverted, to
allow the processor to handle the events generated by an internal or external
SOurces.

Examples of Events:
Resetting ARM core.

g
in
Failure of fetching instructions.

er
- legal memory accesses.
Externally generated interrupts.

e
an undefined instruction.
An attempt by the processor to execute

in
ng
6.3.2 Exceptions and Modes
Each exception causes the ARM core fE
toenter a specific mode:
O
Exception Mode Purpose
e

Fast Interrupt Request FIQ Fast interrupt handling.

g
le

Interrupt Request IRQ Normal interrupt handling.

ol

SWIand RESET SVC Protected mode for OS.

C

Pre-fetch or data abort

u

ABT Memory protection handling.

ad

SW emulation of HW
iln

Undefined Instruction UND coprocessors.

m

Table 6.2
Ta

In general, exceptions require both prioritization and vectoring. It must be

prioritized because asingle operation may generate more than one exception. The
priority of exceptions is usually fixed by the CPU architecture.
to Vectoring provides a way for the user to specify the handler for the exception
condition. The vector number for an exception is usually predefined by tne
architecture which is used as index into a table of exception handlers.
<br>

Page 226 of 440

CPUS
6.11

6.4 TRAPS
Definition:

A trap is an instruction that explicitly generates an exception condition

which is
also known as a software interrupt. The most common use a trap is to enter
of

g
the mode.

in
The entry into supervisor mode must be controlled to maintain security.
If an

er
interface between user and supervisor mode is improperly designed, a user

e
program may be able to sneak code into the supervisor mode

in
that could be
executed to perform the harmful operations.

ng
The ARM provides the SWI interrupt for software interrupts. This instruction
fE
causes the.CPU to enter supervisor mode. An opcode is embedded in the
instruction that can be read by the handler.
O
e

6.5 MODELS OF PROGRAMS

g
le

6.5.1 Introduction
ol
C

Control fiow analysis Inter-procedural Program

u

Flow analysis Intra-procedural Function

ad

Local
iln

Data flow analysis Basic block

m

Fig 6.5 Program flow analysis

Ta

* In the program analysis,

() Control Flow Analysis:
It deternines the control structure ofa program and builds Control Flow
Graphs (CFGs).
(i) Data Flow Analysis:
It determines the flow of data values and builds Data Flow Graphs (DFGs).
<br>

Page 227 of 440

6.12| Embedded Systems and 10T Design

6.5.2.Data Flow Graphs (DFGS)

Definition:
the data processing requirements
The Data Flow Graph (DFG) model translates
emphasizes on the data and operations on the data
into a graph. This model

g
which transforms the input data to
output data.

in
operation on the data (process) is
DFG is a visual model in which the

er
arrows. An
using a block (circle) and data flow is represented using
represented

e
process (circle) represents input data and an outward arroy
arrow

in
inward to the
output data in DFG notation.
from the process (circle) represents

ng
input, to an output.
In a DFG model, a data path is the data flow path from
Embedded applications which are compütationally
fE intensive and data driven are

modeled using the DFG model.

O
a simple basic block. As the C code
Consider a below example which is
e

execute all the

executed, we would use this basic block at the beginning and
g
le

statements which is illustrated as in Fig 6.6.

ol

X=a+b;
C

y= X -C;
u

a b
ad
iln

Data flow node

m

X
Ta

Data flow node

Fig 6.6 DFGforour sample basic block

<br>

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CPUS
6.13|
6.5.3 Control /Data Flow Graphs (CDFG)

Definition:
The fundamental model
for programs is the ControVData Flow Graplh
(CDFG). II constructs the model
for both data operations (arithmetic and

g
other computations) and control

in
operations (conditionals).
A CDFG uses a datá flow graph as an

er
element and adding constructs to
describe the control. The basic

e
CDFG, have two types nodes:
of

in
(i) Decision nodes, and

ng
(ii) Data flow nodes.
# A
data flow node encapsulates a complete data fE
flow graph to represent a basic
block anda decision node is used to
describe all types of control in a sequential
O
program.
e

Fig 6.7 illustrates a bit of code with control constructs and the CDFG
g
le

constructed from it, as shown in fig 6.8. The

rectangular nodes in the graph
represent the basic blocks. The basic blocks in
ol

the Ccode have been represented

C

by the function calls for simplicity.

if (condl)
u

basic block 1();

ad

else
basic block 2 ()
iln

basic block 3();

m

{
switch (testl)
case cl: basic block 4 (); break;
Ta

case c2: basic block 5(); break;

case c3: basic block_6(): break;
}

Fig 6.7 C code

*The diamond-shaped nodes represent the conditionals. The node's condition is
given by the Label, and the edges are labeled with the possible outcomes of
evaluating the condition.
<br>

Page 229 of 440

Design
Embedded Systems and 10T
6.14|
C code

T
basic_block_1()
cond1
F

basic block _2)

g
in
er
basic_block_3()

e
in
test1

ng
C1 c3
c2

basic block 4() basic_ block_5()

fE basic_block_6()
O
e

CDFG
g
le

Fig 6.8 CDFG offig 6.7

(1) Lòops:
ol

o
Looping statements in execute the sequence of statements
C many times until
C

the stated condition becomes false.

u

o A loop in C consists of two parts: a body of a loop and a control statement.

ad

The control statement is a combination of some conditions that direct the

body of the loop to execute until the specified condition becomes false.
iln

o The purpose of the C loop is to repeat the same code for a number of times.
m

The control conditions must be well defined and specified otherwise the loop
Ta

will execute for an infinite number of times.

o A while loop is the most straightforward looping structure. The syntax for
While loop in C programming language is as follows:
{
while (condition)
statements;

Fig 6.9 Syntax of while loop in C

<br>

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CPUs
|6.15
Building a CDFG for a while loop is straightforward
with an example is given
in Fig 6.10.
while(a < b) {
a = proc1(a,b);
b= proc2(a,b);

g
in
C code

er
a <b

e
in
T

ng
a=
proc1(a,b);
b= proc2(a,b); fE
O
CDFG

Fig 6.10 A while loop and its CDFG

g e

6.6 ASSEMBLY, LINKING AND LOADING

le
ol

6.6.1 Introduction
C

& The compilation process in C is converting an understandable human code into

u

a machine understandable code.

ad
iln

Source Code Compilation Machine Code

m

Written in C ..011010110...
Language
Ta

Fig 6.11Compilation process

* Compilation process in C involves four steps:

) Preprocessing,
(ii) Compiling,

(ii) Assembling, and

(iv) Linking.
<br>

Page 23 of 440
1l

6.16| Embedded Systems and IOT Design

Compiling Assembling
Preprocessing

in C Expanded source code Assembly Code

Source Code

g
in
Executable file Object Code

er
Linking

e
in
Fig 6.12 Steps involved in compilation process

ng
(1) Program Generation Work Flow:
High-level
Compiler
fE
Assembly Object
language Assembler code
code
O
code
g e
le

Linker
ol

Execution
C

Loader Executable
binary
u
ad

Fig 6.13 Program generation fromconmpilation through loading

iln

Most of the compilers do not directly generate machine code. A compiler is a

software that -converts the source code (or) high-level language into the
m

instruction-level program in the form of human-readable assembly

Ta

language.
The assembler's job is to translate symbolic assembly language statements
into a bit-level representations of instructions known as object code.
The final steps in determining the addresses of instructions and data are
performed by the linker, which produces an executable binary file. The
program that brings the program into memory for execution is called a
loader.
<br>

Page 232 of 440

CPUs 6.17
(1) Absolute And Relative Addresses
o
There are two types of addressing:
(i) Absolute addresses, and
(ii) Relative addresses.

g
& Absolute Addresses:

in
er
The simplest form of the assembler assumes that the starting address of the
assembly language program has been specified by the programmer. The

e
in
addresses in such a program are known as absolute addresses.

ng
In absolute addressing. you can specify the actual address of a memory
location which is called as absolute address. It is constant and is not
fE
modified in any way by the microprocessor.
O
a Relative Addresses:
e

Relative addresses means an address specified by indicating its distance

g

from another address which is called as the base address that is start of the
le

file.
ol

The absolute address specifies the plysical storage location of the record.
C

The relative address specifies the number of bytes from the start of the file.
u

For example, in Fig 6.14, a relative address might be B+4, B being the base
ad

as the offset. The linker is

address and 4 the distance which is also called
iln

addresses.
then responsible for translating the relative addresses into the
m
Ta

1 3 5

Absolute
Base
Address
Address
(B) (3)

Relative Address
B+4
addressing
Fig 6.14 Absolute and relative
<br>

Page 233 of 440

|6.18 Embedded Systems and 10T Design

6.6.2 Assemblers
When translating an assembly code into object code, the assembler must
translate opcodes and format the bits in each instruction, and then translate the
labels into addresses.

g
in
* Labels make the assembly process more complex, but they are the most

er
inportant abstraction provided by the assembler. Label processing requires two

e
passes through the assembly source code:

in
() The first pass scans the code to determine the address of
each label.

ng
(i) The second pass assembles the instructions using
the label values computed
in the first pass. fE
(1) Symbol Table
O

add ro,r1,r2
e

PLC XX add r3,r4,r5

g

cmp r0,r3 XX Ox8

le

yy sub r5,r6,7
Ox10
ol

Assembly code
Symbol table
C

Fig 6.15 Symbol table processing

during assembly
u

Fig 6.15 shows the name of each symbol

and its address is stored a symbol
ad

table that is built during the first pass. in

The symbol table is built
by scanning
iln

from the first instruction to the last.

During scanning, the current
m

location in memory is
Location Counter (PLC). At kept in a Program
Ta

the start of the first pass,

program'sstarting address and the PLC is set to the
the assembler points to the first
line.
After examining the line, the
assembler updates the PLC to
the next location
and looks at the next instruction.
If the instruction begins with a label, a new entry
is made in the symbol table,
which includes the label name and iis value.
The value of the label is equal to
the current value of the PLC. At the end
of the first pass, the assembler
rewinds to the beginning of the assembly language file to
make the second
pass.
<br>

Page 234 of 440

CPUS
6.19|
ORG 100 label1 100
PLC = 100 label1 ADR r4,c 100
LDR rO.(r4]

Code Symbol tablo

g
in
Fig 6.16
During the second pass, when a label name is found, the label is looked up in

er
the symbol table arnd its value substitutcd into the appropriate place in the

e
in
instruction.

ng
(2) Object Code Formats
The assembler produces an object file that deseribes the instructions, data and
fE
any addressing information in the binary format. A commonly used object file
O
format, originally developed for Unix is Common Object File Format (COFF).
e

6.6.3 Linking
g
le

2 Linker:
linker is a sofhware tool that plays a crucial role in the compilation process of
ol

a program. It takes the object code generated by an assembler and combines it

C

an executable file.
with other necessary libraries and molules to create
u

your
The linker takes care of resolving references between different parts of
ad

or
program. When you write code, you often divide it into multiple source files
iln

necessary functions and variables

the modules. The linker ensures that all the
m

your program to run

from different modules are correctly connected and allowing
Ta

smoothly.
assembler and modifies the
The linker operates on the object files created by the
necessary links between the files.
assembled code to make the
same file. Other labels will be
Some labels will be both defined and used in the
as illustrated in Fig 6.I7.
defined in a single file but used clsewhere
<br>

Page 235 of 440

Embedded Systems and 10T Design

|6.20|

LDR rO,[r1) label2 ADR var1

label1

ADRa
B labct3

B label2 X

y s 1

g
var1 % 1 3 10

in
er
Extornal Entry

e
Extemal Entry roferuncos points

in
references points
var1 label2

ng
label1
label2 labol3
var1
fE
O
Filo 1
Filo 2
e

Fig 6.17 Externalreferences and entry points

g
le

The place in the file where a label is

efined is known us un entry pvint. The
ol

place in the file where the label is used is culled an

external reference.
C

+ The main job of the loader is to resolve

extemal references buscd on availbl:
entry points. Extermal references are identified
u

in thc object code by their relative

ad

symbol identifiers.
iln

(1) Linking Process:

m

The linker proceeds into two phases:

Ta

(i) First, it detemines the address of the start

of each object file. Vhen the
nun or by creating a mop loJris
load file that gives the order in whicth tles ane to tv
placed in mennory and the length
of caclh object file, it is casy to compute tx
starting address of an cach file.
(ii) At the start of sccond phase, the loader mcrgcs all the
symbol tables tott the
a
object files into single and large table. It then cdits the objcet files to chunge
the
relative addresses into addresses. This is typically pertormed by
having the
<br>

Page 236 of 440

CPUS 6.21
assembler extra bits into the object file to
write
identify the instructions and
felds that refer to labels.
Dynamically Linked Libraries
(2)

Static linkers merge all the necessary object code and libraries into a single
executable file, resulting in a self-contained program.

g
in
o
Dynamic linkers allow the program to be loaded into memory at runtime and

er
link to shared libraries which enabling more flexibility and an efficient

e
memory usage.

in
ng
A Dynamic Link Library (DLL):

A
Dynamic Link Library (DLI) is defined as a file type containing code,
fE
data, and resources that can be shared among multiple programs to
O
accomplish the specific tasks.
e

DLLs offers common functionality to programs that can be loaded into

g

memory and executes on demand.

le
ol

6.6.4 Object Code Design

C

(1) Memory Map Design

u

are placed in
o The linker allows us to control where object code modules
ad

memory. We may need to control the placement of several types of data:

iln

(i) Interrupt vectors and other information for I/O devices must be placed in
m

a specific locations.
Ta

must be set up.

() Memory management tables
processes must be put
(ii) Global variables used for communication between
users of that data.
in locations that are accessible to all the
(2) Reentrancy:
program is reentrant
Many programs, should be designed to be reentrant. A
the
ifit can be interrupted by another call to the function without changing
results of
either call.
<br>

Page 237 of 440

6.22| Embedded Systems and 1OT Design

A program is recursive lf the program changes the value of

global variables,
it may give a different answe.

(3) Relocatability:
A program is relocatable if it can be executed when loaded into diferent parts of

g
memory. It requires some sort of support from hardware that provides address

in
calculation.

er
6.7 COMPILATION TECHNIQUES

e
in
6.7.1 The Compilation Process

ng
a Definition:
The compilation is a process
fE
of converting the source code into object code. It is
done with the help of the compiler and an assembler. The compiler checks the
O
source code for the syntactical or structural errors, and if the source code is
error-free, then it generates. an assembly code. This assembly code is then
g e

converted into object code by using an assembler.

le

Compilation =-Translation + Optimization

ol

The compilation process is outlind in Fig 6.18. Compilation begins with high
C

level language code such as Cor C++ and generally produces assembly code.
u

High-level
ad

language code
iln

Parsing, symbol table generation, semantic analysis

m
Ta

Machine-independent optimizations

Instruction-level optimizations
and code generation

Assembly code

Fig 6.18 Compilation process

<br>

Page 238 of 440

CPU: 6.23|

language program is parsed to break it into statements and

The high-level
expressions. In addition, a symbol table is generated, which includes all the
named objects in the program.

Some compilers may then perform higher-level optimizations that can be viewed
as modifying the high-level language program input without reference to an

g
instructions.

in
er
6.7.2 Basic Compilation Methods

e
in
(1)Procedures

ng
Procedures are known as
functions in C that requires a specialized code. We
generate the code to handle the procedure call and returm. At each call of the
fE
procedure, we set up the procedure parameters and then makes the call.
O
as a frame. The frames
The information for a call to a procedure is known
are stored on a stack to keep track of the order in which the procedures have
g e

been called.
le

grow down from high addresses. A

Procedure stacks are typically built to
ol

current frame, while a Frame

Stack Pointer (SP) defines the end of the
C

Pointer (FP) defines the end ofthe last frame.

frame by addressing relative to
u

can refer to an eleinent in the

The procedure
ad

SP and FP are modified to push

SP. When a new procedure is called, the
iln

another frame onto the stack.

(APCS) is the recommended procedure
The ARM Procedure Call Standard
m

o
processors. are used to pass the first four parameters
linkage for ARM r0- r3
Ta

used to hold the return value.

into the procedure and r0 is also

(2) Data Structures

translate references to data structures into
The compiler must also
references to raw memories. array
must be computed at run time, because the
Address of an array element
index may change.
<br>

Page 239 of 440

Embedded Systems and 10TDesign

6.24|

us consider a one dinensional array:

Let
a[il element
array in memory is shown in Fig6.19. The zeroth
The layout the
of
the array, the first element directly below.
is stored as the first element of
and so on.

g
in
a[0]

er
a[1]

e
in
of a one-dimensional array in memory

ng
Fig 6.19 Layout
For our convenience, we can use the pointer aptr for the reading of a[i] as,
fE
*(aptr + i)
O
If the a[ } array
with the size of Mx
N,
then the two-dimensional array
e

access can be expressed as,

g

a
le

i, j]

as
ol

o Fig 6.20 shows two-dimensional array structure which is implemented

C

a contiguous block of
structure can be accessed using
memory. Fields in this
u

constant offsets to the base address of the structure.

ad

For example, if fieldl is 4 bytes long, then field2 can be accessed as

iln

*(aptr + 4)
m
Ta

a[0,0]

a0,1]

a[1,0]
a[1,1]

arrays
tn Mausnm Inut for two-dinnensional
<br>

Page 240 of 440

CPUs
|6.25|
6.7.3 Compiler Optimizations
The basic compilation techniques can generate
inefficient code. Then compilers
a
1se wide range of algorithms to
optimize the code vwhich it generates.

(1) Loop Transformations: Loop Optimization Techniques

g
Loop optimization is the process of increasing an
execution speed and

in
reducing the overlheads associated with loops. It plays an
important role in

er
improving cache performance and making effective use
of parallel

e
processing capabilities.

in
Most execution time of a scientific program
is spent on loops.

ng
(0 Loop Unrolling:
fE
Loop unrolling is a loop transformation technique that helps to optimize the
execution time of a program. It increases the program 's speed by eliminating
O
loop control instruction and loop test instructions.
g e

() Loop Fusion (or) Loop Jamming

le

Loop fusion is combining tvo or more loops in a single loop which reduces the
ol

loop overhead and also reduces the time taken to compile the many loops i.e.,
C

improve the run-time performance.

u

Before optimization:
ad

for (int i=0; i<5; i++)

iln

a = i + 5;

for (int i=0; i<5; it+)

m

b= i + 10;
Ta

After optimization:
for (int i=0; i<5; i++)

a = + 5:
i
b= i + 10;

Fig 6.21 Loop fusion

<br>

Page 24lof 440

Enbedded Systems and 10T Design

6.26|

(ii) Loop Distribution

(or) Loop fission is a compiler optimization technique in
Loop distribution
multiple loops over the same index range with
which a loop is broken into
loop's body.
cach taking only a part oftheoriginal
processors that can split a

g
efficient in multi-core
This optimization is most

in
processor.
task into multiple tasks for cach

er
(d) Loop Tiling

e
inner loop
up a loop intoa set of nested loops and each

in
Loop tiling breaks
the data.
performing the operations a subset of
on

ng
up into tiles of
Here, each loop is broken
An cxample is shown in Fig 6.22.
two loops. For example, the inner 'i"
fE
size two that is, each loop is split into
loop iterates within the tile and the
outer i' loop iterates across the tiles.
O

c0.1]|(0.2} (0,N-1]
e

[0,2] [0,N- 1] [o,0]

[0,0]
g

[1,N- 1] [1,0] [1,1]| [1.2]1,N- 1]

le

[1,0) (1,2]
Access
pattern
(2,N - 1]
ol

in [2,0) [2.2] 2,N-1] [2,0] 2.1]|(2,2)

a array
C

[3,2) [3,N - 1] [3,0] (3,2] (3,N - 1]

[3,0]
u
ad
iln

Before After

Fig 6.22 Loop tiling

m

(2) Dead Code Elimination

Ta

A Dead Code:
Dead code is the code that can be never executed. It can be generated by he
programmers, either inadvertently or purposefully and also by the compilers.

Dead code can be identified by reachability analysis that is, finding the
other statements or instructions from which it can be reached. Dead code
elimination analyzes the code for reachability and removes it.
<br>

Page 242 of 440

PUs 6.27|

|Register Allocation
Register allocation is an important method in the final phase of the compiler.
Registers are faster to access than cache memory and registers are available in
small size up tofew hundred kB .Thus, it is necessary to use a minimum number
ofregisters for variable allocation.

g
in
Scheduling:

er
Instruction Scheduling:

e
Insiruction scheduling is a process of mapping a series of instructions into

in
execution ofresources. It decides when and where an instruction is executed.

ng
We can keep track of CPU resources during instruction scheduling by using
fE
a reservation table which illustrated in Fig 6.23. Rows in the table represent
instruction execution time slots and columns represent resources that must
O
be scheduled.
e

Time Resource A Resource B

g

t X
le

t+ X X
ol

X
C

t+2
t+3 X
u
ad

Fig 6.23 A reservation table forinstruction scheduling

Before scheduling an instruction to be executed at a particular time, we can
iln

check the reservation table to determine whether allthe resources needed by

m

the instruction are available at that time.

Ta

After scheduling the instruction, we update the table to note all resources
used by that instruction. Various algorithms can be used for the scheduling
depends on the types of resources and instructions involved,
Software Pipelining:
A soflware pipelining is a compile-time scheduling technique for reordering

instructions across several loop iterations that is, overlaps subsequent loop
iterations to reduce the pipeline operations.
<br>

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Embedded Systems and 10T Design

6.28

(4) Instruction Selection

instructions, to implement each operation is a dificult task
Selecting the
that can be used to accomplish
There may be a several different instructions
may have different execution times.
the same goal, but they
one part of the program may affect the instructions
Using one instruction for

g
technique for generating the

in
that can be used in adjacent code. One useful
in Fig 6.24.
code is template matching which is illustrated

e er
Multiply

in
cost = 1

ng
fE Add
cost = 1
O
Code
g e
le

Multiply-add
cost = 1
ol
C

Instruction templates
u
ad

Fig 6.24 Code generation by template matching

Directed Acyclic Graph (DAG):
iln

The DAG is used to represent the structure basic blocks, to visualize the
of
m

flow of
values between basic blocks, and to provide an optimization techniques
Ta

in the basic block.

o
If we a
DAG that can represent
have want to
the expression for which we
generate code. To be able to match up instrutions and operations,
represent instructions using the same DAG
representation.
We code
shaded the instruction template nodes
to distinguish them from
nodes. Bach node has a cost, which may of the
be simply execution time the
instruction or may include factors for size, power on.
consumption, and so
<br>

Page 244 of 440

CPUS 6.29

In this case, we have shown that each instruction takes the same amount of
time, and thus all have a cost of 1.

68 PROGRAM-LEVEL PERFORMANCE ANALYSIS

g
6.8.1 Introduction

in
* Embedded systems helps to perform functions in real time, we often need to

er
know how fast a program runs. The techniques we use to analyze program

e
execution time are also helpful in analyzing properties such as power

in
consumption.

ng
PipelineA

fE
O
eg
le
ol

Cache
Total execution time
C

Fig 6.25 Execution time of a program

u
ad

Consider the Fig 6.25, the CPU pipeline and cache act as windows into
our
*
program. To understand the total execution time of our program, we must look at
iln

an execution paths, which in general are far longer than the pipeline and cache
m

windows.
Ta

a
The pipeline and cache influence execution time, but execution time is global
property of the program. It is _very difficult to calculae the execution time of
programs because of the following reasons:
(1) The execution time of a program often varies with the input data values
program.
because those values select different execution paths in the

() The cache has a majoreffect on program performance but the cache's

program.
behavior depends in part on the data values input to the
<br>

Page 245 of 440

Embedded Systems and 10T Design

6.30
the
Execution times may vary even at the instruction level. In general,
(i1)
a pipeline depends not only On that
execution time of an instruction in
pipeline.
instruction but also on the instructions around the

6.8.2' Measuring Execution Speed

g
ways:

in
We can measure program performance in several

er
which
() Some microprocessor manufacturers supply simulators for their CPUs
can runs on a workstation or PC that takes as input datas, and simulates the

e
in
execution of that program. Some of these functional simulations also

ng
measure the execution time of the program.

(ii) A timer connected to the microprocessor bus can be used to measure the
fE
performance of executing sections of acode.
O
(ii) A logic analyzer that can be connected to the microprocessor bus is used to
measure the start and stop times of a code segment.
g e

Three different types of performance measures on programs are,

le

(i) Average- Case Execution Time (ACET):

ol

This execution time would expect for typical data. First, we

C

clearly define
the typical inputs.
u

(ii) Worst-Case Execution Time (WCET):

ad

This is the longest time that the program can

spend on any input sequence.
iln

We can check whether the system meets

the deadlines.
m

(ii) Best-Case Execution Time (BCET):

Ta

It is the shortest time that the pogram can

spend on any input sequence. Tns
measure can be important in multirate
real-time systems.

6.8.3 EIlements of Program Performance

Program execution time can be simply expressed as,
Execution Time = Program Path + Instruction
Timing
The path is the sequence of instructions executed
by the program. The instruction
timing is determined based on the sequence
of instructions traced by the prograu
<br>

Page 246 of 440

CPUs
6.31
nath, which takes into account
the data dependencies, pipeline behavior,
and
caching.
(1) Instruction Timing
o Once we know the
execution path of the program, we
have to measure the
execution time of the instrüctions that are

g
executed along that path.

in
o The simplest estimate is
to assume that every instruction takes the same

er
number of clock cycles, which means we need only to count
the instructions
and multiply by the execution time of one instruction to obtain the

e
program's

in
total execution time.

ng
Drawbacks:
fE
The simplest estimation method is an easiest one but this technique has
following
difficulties:
O
(i) All instructions do not take the same amount of execution times.
g e

() Execution times of instructions are not independent.

le

(ii) The execution time of an instruction may depend on operand values.

ol

4 Caching Effects:
C

Cache memory, which is also a type of random access memory which does not
u
ad

need to be refreshed. It is built directly ino the CPU to give the processor the
fastest possible access to memnory locatios and provides nanosecond speed
iln

access time to frequently referenced instructions and data.

m
Ta

6.8,4 Measurement-Driven Performance Analysis

(1)Program Traces:
o Most of the methods that measures the program performance by combining
the determination of the execution path and the timing of that path.
we can observe the
When the program executes, it chooses a path and
execution time along that path.
<br>

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J6.32 Embedded Systems and IOT Désign

Definition:
The record of the execution path of a program is known as aprogam trace (or)
a trace. It can be valuable for other purposes, such as analyzing the cache
behavior oftheprogram.

g
in
(2) Measurement lssues
o One of the challenging problems in measuring program perforrmance is to find

er
out the useful set of inputs to give the program.

e
in
First, we have to determine the actual input values. By using a simple

ng
program, we may be able to analyze the algorithm to determine the inputs that
cause the worst-case execution time.
fE
A Software Scaffolding:
O
Software scaffolding means creating a temporary structure
for your project
e

that you can use as the foundation to develop the real and more'complex
g

project. It gives you a quick and simplified (but temporary) structure for
le

your project.
ol

It also used to feed data into the program and get data out.
C

(3) Profiling
u

o Profiling is a simple methodfor analyzing the

ad

software the performance. It is

achieved by instrumenting either the program source
code or its binary
iln

executable form using a tool called a profiler (or) code

profiler.
o Profilers may use a number
m

of different techniques, such as event-based,

Ta

statistical, instrumented, and simulation methods.

o A profiler does not measure execution
time instead, it counts the number of
times those procedures or basic blocks in the program are
executed.
(4) Hardware, Traces
Some CPUs have hardware facilities for automatically
generating the trace
information. If we record only traces, we can reconstruct
the instructions
executed within the basic blocks while greatly reducing the amount memory
of
required to hold the trace.
<br>

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CPUS
6.33
Simulation Based Performance
(5) Measurement
A CPUsimulator is a program
that takes an input as memory
image for a CPU
and performs the operations on
that memory image that the actual
nerform, leaving the results CPU would
in the modified memory image.
Cycle-Accurate Simulator:

g
in
For the performance analysis of program
level, the most important type,0

er
CPU simulator is a cycle-accurate simulato,
which performs a sufficiently

e
detailed simulation
of the processor's internals that it can determine the

in
exact number of clock cycles
required for execution.

ng
This simulator is built with a detailed knowledge
fE of how the processor
works, so that it can take into account all the possible behaviors
of the
O
microarchitecture that may affect an execution time.
e

A Instruction-level Simulator:
g
le

A simulator that functionally simulates instructions but does not provide

timing information is known as an instruction-level simulator.
ol
C

6.9 TWO MARKS QUESTIONS AND ANSWERS

u

.
ad

Differentiate data and status registers.

iln

Data registers hold values that are treated as data by the device, such as the data
read or written by a disk.
m

Status registers provide information about the device's operation, such as

Ta

Whether the current transaction has completed.

2.
microprocessor system communicate VO devices.
How a

In a microprocessor system, there are two methods of interfacing input/output

(UO) devices:

) Memory-mapped I/0, and

(i) VO mapped I/O.
<br>

Page 249 of 440

3. What is meant by memory-mapped II0?

In memory-mapped VO, input/output devices are mapped to the memory
address space of the microprocessor. This means that the T/O devices are
treated like memory locations and can be accessed using the same read and
write instructions as memory.
4. What do you mean by I/O inapped IVO?

g
In /O mapped VO, input/output devices are mapped to a separate I/O address

in
er
space which is different from the memory address space. The microprocessor
uses special instructions to access the I/O devices using specific IO address

e
in
signals, which are separate from the memory address signals.

ng
5. Give the comparison between memory-mapped I/O and I/O napped /O
Features Memory Mapped I/O
fE I/O Mapped I/O
I/O devices are accessed like any They cannot be accessed like
O
Addressing
other memory location. any other memory location.
g e

Address Size They are assigned with 16-bit |They are assigned with 8-bit
le

address values. address values.

ol

Instructions The instruction used are LDA The instruction used are IN and
C

Used and STA, etc. OUT.

u
ad

Instruction set Uses the same instructions for Special instructions are used for
accessing both memory and I/O accessing I/O devices
iln

devices
m

Design Simple to implement and design More complex to implement

Ta

complexity and design

6. What is busy-wait I/0?

The simplest way to communicate with devices in a
program is busy-wait
JO. Devices are typically slower than the CPU and may require many cycles
complete an operation.
<br>

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CPUs 6.35
1.
foreground program.
Define

The program that runs when no interrupt is being handled is often called the
foreground program.
8.
What do you mean by nasking?

g
The priority mechanism must ensure that a lower-priority interrupt
does not

in
occur when a higher-priority interrupt is being handled, process
then the decision

er
is known as masking.

e
9. What is NMI?

in
The highest-priority interrupt is normally called as Non-Maskable Interrupt

ng
(NMI). It is usually reserved for interrupts caused by the power failures which
cannot be turned off. fE
Name the interrupts available in ARM processor.
-
10.
O

The ARM processor has two levels of external interrupt:

g e

Fast Interrupt Requests (FIQs), and

le

(ii) Interrupt Requests (RQs).

ol
C

11. What is FIQ?

Fast Interrupt Requests (FIQ) is a specialized type of interrupt request, which is a
u

standard technique used in computer CPUs to deal with events that need
to be
ad

processed as they occur, such as receiving data from a network card, or keyboard
iln

or mouse actions.
m

FIQs is a fast and low-latency interrupt handler.

Ta

12. What do you mean

by
An Interrupt Reguest (IRQ) is a signal sent to computer's processor to
a
a
momentarily stop (intèrrupt) its operations. The signal is úsually sent.by
some time to
hardware device to interrupt the processor so that the device gets
run its own operation.
13.
Name modes of ARMprocessor.
the different operating
The ARM processor has seven different modes of operation.
<br>

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Embedded Systems and 10TDesign

(1) User mode,

(ii) Fast Interrupt Request(FIQ) mode,

(iii) Interrupt Request(IRQ) mode,

(iv) Supervisor mode,

(v) Abort mode,

g
in
(vi) Undefined mode, and

er
(vi) System mode.

e
14. What is meant by supervisor mode?

in
Supervisor mode is an automatic selected mode when a computer is powered on

ng
that is, a processor enters supervisor mode on reset.
fE
When a program is in user mode, wants to execute a privileged task,
for example
allocating more memory, it needs to make a system call. So that,
O
the operating
system performs instructions to do the privileged task, which
is achieved, by the
e

program executing the supervisor call (SVC) instruction.

g
le

15. List tlhe features of supervisor mode in ARM processor.

ol

Some of the important features of supervisor mode are as follows:

C

(i) It handles different types of commands but mostly deals with privileged.
u

instructions.
ad

(i) The operating system selects supervisor mode for the low level tasks that
require complete access to the system hardware.
iln

(iii) It can create the memory address spaces as well as updating them.
m

(iv) Various interrupts can be enabled or disabled using the supervisor mode. It
Ta

also contributes to the loading of the proçessor status.

(v) The supervisor mode can access the various data structures available inside
the operating system.
16. Define exceptions.
a way for Wite
An exception is an internally detected error. This mechanism provides
the program to react for an unexpected events such
as resetting ARM core, th
fetching instructions and illegal memory accesses.
failure of
<br>

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CPUS
6.37|
17. What is meant by trap?
an is an instruction that explicitly generates an
exception condition
lea known as a software interrupt. which is
The most common use a trap
mode. of to enter
is the
18. Write the function of DFG.

g
The Data Flow

in
Graph (DFG) model translates
the data processing requirements
into a graph. This

er
model emphasizes on the data
which transforms and operations on the data
the input data to output data.

e
in
19. What do you mean by CDFG?

ng
The fundamental model programs
for is the Control/Data Flow Graph
constructs the model (CDFG). It
and control operations (conditionals).
fE
for both data operations (arithmetic and
other computations)
O
A CDFG uses a data flow
graph as an element and adding constructs to describe
the control. The basic CDFG,
e

have two types of nodes:

g

(i) Decision nodes, and

le

(ii) Data flow nodes.

ol

20. What is compilation

C

process?
The compilation process in C is converting an understandable
u

human code into a

ad

machine understandable code.

U. Name the steps involved in conpilation process.

iln

Compilation process in C involves four steps:

m

() Preprocessing,
Ta

(i) Compiling,
(i) Assembling, and
(iv) Linking.
22, W
Write
the function of compiler.
A
compiler
software that converts the source code (or) high-level language
is
a

into the
instruction-level program in the form of human-readable assembly
language.
<br>

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6.38 Embedded Systems and TOT Design

23. WIhat is assembler?

The assembler's job is to translate symbolic assembly language statements intoa

bit-level representations of instructions known as object code.

g
24. What is the need of loader?

in
The program that brings the program into memory for execution is called a

er
loader.

e
25. Define absolute addressing.

in
The simplest formn of the assembler assumes that the starting address

ng
of the
assembly .language program has been specified by the programmer. The
fE
addresses in such a program are known as absolute addresses.
In absolute addressing, you can specify
O
the actual address of a memory location
which is called as absolute address.
e

26. What is relative addresses?

g
le

Relative addresses means an address

specified by indicating its distance from
ol

another addrss which is called as

the base address that is start
of the file.
C

27. Write the function of linker.

u

A linker is a software tool

that plays a crucial role in the
ad

program. It takes compilation process of a

the object code generated by an
assembler and combines with
other necessary libraries and it
iln

modules to creàte an executable

file.
28. Define entry point
m

and external reference.

The place in the file where a
Ta

label is defined is known as an

place in the file where entry point. The
the label is used is called an
external reference.
29. What is DLL
in linker?
A Dynamic Link Library
(DLL) is defined as a
and resources that can file type containing code,
be shared among multiple programs dat,
specific tasks. DLLs
offer common functionality to accomplisn
into memory and executes on to programs that can
demand. be loadeu
<br>

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CPUS
6.39
20 What the terms reentrant and recursive represent in program?
program is reentrant it can. be interrupted
A
if by another call to the function
without changing the results of either call.

A program is recursive If the program changes the value

of global variables, it

g
may give a different answer.

in
31. Which one is called as reloacatable program?

er
A program is relocatable ifit can be executed when loaded into different parts
of

e
memory. It requires some sort of support from hardware that provides address

in
calculation.

ng
32. What is compilation process?
fE
The compilation is a process of converting the source code into object code. It is
done with the help of the compiler and an assembler. The compiler checks the
O
source code for the syntactical or structural errors, and if the source code is error
e

free, then it generates an assembly code. Then this assembly code is converted
g

into object code by using an assembler.

le

Compilation = Translation + Optimization

ol
C

33. Define SP and FP.

A Stack Pointer (SP) defines the end of the current frame, while a Frame Pointer
u

(FP) defines the end of the last frame.

ad

34. What do you mean by loop unrolling?

iln

Loop unrolling is a loop transformation technique that helps to optimize the

m

execution time of a program. It increases the program's speed by eliminating

Ta

loop control istruction and loop test instructions.

35, Define loop distribution.
in
Loop distribution (or) Loop fission is a compiler optimization technique
range with each
which a loop is bioken into multiple loops over the same index
taking only a part of the original loop's body.
can split a task
This optimization is most efficient in multi-core processors that
into multiple tasks for each processor.
<br>

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6.40| Embedded Systems and

I0T Design
36. What is dead code?
Dead code is the code that can be never
executed. It can be generated by the
programmers, either inadvertently or
purposefully and also by the compilers.
37. What do you nean by register allocation?

g
Register allocation is an important method in
the final phase of the compiler.

in
Registers are faster to access than cache memory and registers are
available in

er
small size up to few hundred kB Thus, it. is necessary to use a
minimum

e
number of registers for variable allocation.

in
38. What is meant by scheduling or instruction
scheduling?

ng
Instruction scheduling is a process of mapping a series
of instructions into
execution of resources. fE
It decides when and where an instruction is executed.
39. Definê software pipelining.
O
A software pipelining is a compile-time scheduling technique
for reordering
e

instructions across several loop iterations that is, overlaps

g

subsequent loop
le

iterations to reduce the pipeline operations.

ol

40. What is cache effects?

C

Cache memory, which also is a type of random access memory

which does not
need to be refreshed. It is built directly into the CPU to
u

give the processor the

ad

fastest possible access to memory locations and provides

nanosecond speed
access time to frequently referenced instructions
and data.
iln

41. Wht do you nnean by program trace?

m

The record of the execution path of a program is known as a program

Ta

trace (or) a
trace: It can be valuable for other purposes, such as
analyzing the cache behavior
of the program.
42. What is meant by software scaffolding?.
Sofware scaffolding means creating a temporary structure for your
project that
you can use as the foundation to develop more
the real and complex project. It
gives you a quick and simplified (but temporary) structure for your project.
It is also used to feed data into the program and get data out.
<br>

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CPUs
6.41|
43.
WWrite
thefunction of
cycle-accurate simulator.
Eor the performance analysis
of program level, the most important type CPU
eimulator is a cycle-accurate of
simulator, which performs a sufficiently
detailed
eimulation of the processor's internals
that it can determine the exact number
clock cycles required for execution.
of

g
in
6.10 REVIEW QUESTIONS

er
L.
Explain in detail about programming input and output.

e
Write a note on.

in
2.

ng
() Supervisor mode,
(i) Exceptions, and fE
(ii) Traps.
O
3. Discuss in detail about models of prograns.
e

4. Explain with neat sketches about assembly, linking and loading processes.
g
le

5. With neat sketches, explain about compilation techniques.

ol

6. Discuss about program level performance analysis.

C
u
ad
iln
m
Ta
<br>

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UNIT- III

g
Chapter 7

in
er
PROCESSES AND

e
in
ng
OPERATING SYSTEMS
7.1 STRUCTURE OF
A
REAL-TIME SYSTEM
fE
O
7.1.1 Introduction
e

A Real Time System:

g

some specific tasks. It

Real-time system is a system which is used for performing
le

is a computational system which is used for various hard and

soft real-time tasks.
ol

These specific tasks are mainly related with time constraints. The tasks
assigned
C

a time interval.
to real-time systems need to be completed in given
u

are formed by the

Embedded Systems are integrated systems which
ad

a function.
combination computer hardware and software for specific
of
iln

tasks are
The embedded systems which are designed to perform real-time
or Real-time Embedded Systems.
m

known as Embedded Real-time Systenms

Ta

e Types of Embedded Real-time System systems:

There are two types of embedded real-time
0) Hard Embedded Real-time System:
are used to perform hard real-time tasks are
The embedded real-time systems that
are designed in a very
called as Hard embedded real-time system. These systems
complicated way and are accurate systems.
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Embedded Systems and 10T Design

7.2|
(ii) Soft Embedded Real-time System:
are used to perform soft real-time
These are embedded real-time systems that
are chances of inaccuracy.
tasks. These are simple designed systems and there

7.1.2 Structure of Embedded System

g
in
Application SW

er
e
MS

in
Operating System

ng
Device Drivers
fE
O
MH
Memory
Processor WO Devices
Devices
g e

Fig 7.1 Different layers of embedded system

le

Figure 7.1 shows the different layers of an embedded system. The lower layer is
ol

the embedded hardware which consists of:

C

The processor, which is the main system controller.

u

The memory devices, where instructions and datas are stored.

ad

I/O devices through which communication between the processor and the
iln

external world is enabled.

m

The upper layer is the embedded software. This layer changes according to the
Ta

design of the system being built. In some systems, some

of these layers may be
combined or totally ignored. Generally, embedded software consists of:
Device drivers, which are software written to directly control the embedded
hardware and provide an Application Programming Interface (API) to the
upper software layers. Device drivers abstract hardware details from
application programmers.
Operating system is a software that manages the systems resources.
<br>

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Processes and Operating Systemns. 7.3

Application software is the software that performs

the main function that the
system was built for.

Software

g
Application Software

in
er
Middleware

e
Operating System (GPOS,RTOS)

in
ng
Firmware
fE
O
Hardware
g e

Peripherals Sensors Actuators

le
ol

Computer buses(Signal converters

C

Memory WO devices
Processor
u
ad

System on Chip System on Module

iln

Fig 7.2Embedded systems structure

m
Ta

7.1,3 Structure of Embedded Real-time System

The structure of a real-time system includes various hardware and software
can bè performed in
devices embedded in such a way that specific tasks
allowed constraints.

* Fig 7.3 represents the structure of Embedded Real-time System.

<br>

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Design
Embedded Systems and 10T
7.4
Sensor
Actuator

Sensor
Actuator HComputation Processing

g
Processing

in
er
Environment

e
in
7.3 Structure of Enbedded Real-time System

ng
(0) Sensor: fE
to sense the environment periodically. It is used for conversion
Sensor is used a
or characteristics into electrical signals. This is
O
some physical events
of
environment and gives output to the
hardware device that takes input from
e

processed to determine the

system. The sensed data from the environment is
g
le

necessary corrective actions.

ol

(iü) Sensor Processing

C

sensor, it makes data ready for

When data is sensed from environment via
processes. This
computation process. It involves both conditioning and other
u
ad

in
process is required to obtain data in compatible form for computation
system:
iln

(i) Computation
m

to be
Computation is a process of calculation and operations needed for task
Ta

completed. This is main process that happens inside real-time system. It takes
data input from sensor and gives output to actuator of real-time system.

(iv) Actuator Processing

It is just like sensor processing but does reverse work. It takes input from
system and gives this to an actuator of system. This is basically used to make
output compatible with environment so that the user can easily understand an
obtained output.
<br>

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Processes and Operating Systems

7.5|
(v) Actuator
Actuator is a reverse device of sensor. is
It used to convert electrical signals into
nhysical events or characteristics. It takes
input from the system and gives output to
an environment. The output
obtained from actuator may be in any form physical
of
action. Motors and heaters are some

g
of the commonly actuators.
used

in
7.2 TASK ASSIGNMENT AND SCHEDULING

er
7.2.1 Introduction

e
# Real-time systems are systems that carry real-time tasks. These taskS need to be

in
performed immediately with a certain degree of urgency. In particular,

ng
these
tasks are related to control of certain events (or) reacting to them. Real-time
fE
tasks can be classified as hard real-tine tasks and soft real-time tasks.
A,
hard real-time task must be performed at a specified time which could
O
otherwise lead to huge losses. In soft real-time tasks, a specified deadline can
e

be missed. This is because the task can be rescheduled (or) can be completed
g

after the specifted time.

le
ol

7.2.2 Task Assignment

C

A Definition:
u

Task assignment is the process of allocating specific tasks or responsibilities to

ad

individuals or teams within an organization. t

involves determining who is
iln

responsible for conmpleting a task, by providing them with the necessary

information and resources, and setting clear expectations for the desired
m

outcome.
Ta

Task assignment is important for the following reasons:

ensures that work is distributed eftciently and effectively among team
() I
members.
(i1)
t allowsfor better utilization of individualskills and expertise.
(ii) It helps in balancing workload and avoiding bottlenecks or overload.
iy) I promotes accountability and clarity regarding responsibilities.
() It inproves productivity and task completion within the desired timelines.
<br>

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|7.6|
Embedded Systems and 10T Design
(vi) It facilitates effective collaboration and coordination among
team members.
When assigning tasks, we will consider the following factors:
) Individual skills, knowledge, and expertise required for the task.
(ii) Availability and workload of team members.

g
in
(ii) Deadlines and priority of tasks.

er
(iv) Communication and collaboration requirements.

e
(v) Dependencies and relationships between tasks.

in
(vi) Consideration of individual developmént or growth opportunities.

ng
(vi) Balancing workload and avoiding overbutdening or underutilization.
fE
7.2.3 Scheduling
O
4 In real-time systems, the scheduler is considered as the most important
e

component which is typically focusing to reduce the response time associated

g

with each of the associated processes when handling the deadline.

le
ol

Definition:
C

The way that time is allocated between tasks is termed as "scheduling". The
scheduler is the software that determines which task should run next. The logic of
u
ad

the scheduler and the mechanism that determines when it should be run is the
scheduling algorithm.
iln

Task 1 Task 2 Task 3 Task 1

m

Stop start start

Star stop Stop
Ta

Time

Fig 7.4 Scheduling

4 Preemptive scheduling is used in real-time systems where the tasks are usually
configured with diferent priorities and time critical tasks are given higher
priorities. A higher priority task can stop a lower priority one at any time, grab
and use the CPU until it releases it.
<br>

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Processes and Operating Systems

7.7
Preemptive scheduling is the most commonly used scheduling
algorithm in real
time systems. Here, the tasks are prioritized
and the task with the highest priority
among all other tasks gets the CPU time:
Task priority
Task 3

g
in
Task 2 Task 2

er
Task 1
Task 1

e
in
Time

ng
Fig 7.5 Preenptive scheduling
fE
* In the case of a non-preemptive scheduling, even if the highest priority is
allocated to the task, it needs to wait until the completion of the current task.
O
This task can be either slow (or) lower priority, which can lead to a longer
e

wait.
g

non
A better approach is designed by combining both preemptive and
le

preemptive scheduling. This can be done by introducing time-based interrupts

ol

means the currently running process is

in priority based systenns which
C

a process is present in
interrupted on a time-based interval and if higher priority
u

a ready queue, it is executed by preempting the

current process.
ad

Algorithms:
72.4 Classifications of Task Scheduling
iln

a
priority does not change with mode. In
* In stati priority algorithms, the task
m

with time.
priority algorithms, the priority can clhange
4namic
Ta

on schedulability, implementation (static or dynamic), and the result

*Based classified
analysis, the scheduling algorithm are further
(Self or dependent) of
as follows:
(0)
Static Table-Driven approaches:
perform a static analysis associated with scheduling
These algorithms usually a
are advantageous. This helps in providing
and capture the schedules that which the execution must be started at
out a task with
schedule that can point
run time.
<br>

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|7.8 Embedded Systems and 10T Design

(ii) Static Priority-Driven Preemptive approaches:

These types of algorithms also use static analysis of scheduling. The difference is
that instead of selecting a particular schedule, it provides a useful way of
assigning priorities among various tasks in preemptive scheduling.

g
(ii) Dynamic Planning-based approaches:

in
Here, the feasible schedules are identified dynamically (at run time). It carries
a

er
certain fixed time interval and a process is executed if and only if satisfies the

e
time constraint.

in
(iv) Dynamic Best Effort approaches:

ng
These types of approaches consider deadlines instead of feasible schedules.
fE
Therefore, the task is aborted if its deadline is reached. This approach is used
widely in most of the real-time systems.
O

7.2.5 Advantages
e

The advantages of scheduling in real-time systems are,

g
le

(i) Meeting Timing Constraints:

ol

Scheduling ensures that real-time tasks are executed within their specified
C

on time,
timing constraints. It guarantees that critical tasks are completed
preventing potential system failures or losses.
u
ad

(ii) Resource Optimization:

ensures
Scheduling algorithms allocate system resources effectively which
iln

efficient utilization of processor time, memory, and other resources. This hlps
m

maximize system throughput and performance.

Ta

(ii) Priority-Based Execution:

Scheduling allows for priority-based execution, where higher-priority tasks are
given prcedence over lower-priority tasks. This ensures that time-critical tasks
are promptly executed, leading to improved system responsiveness and
reliability.
(iv) Predictability and
Determinism:
Real-time scheduling provides predictability and determinism
in task execution.
It enables developers to analyze and guarantee
the worst-case execution tins
and response time of tasks, ensuring
that critical deadlines are met.
<br>

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Processes and Operating Systems |7.9

(v) Control Over Task Execution:

Scheduling algorithms allow developers to have finc-graincd control over
how
tasks are executed, such as specifying task priorities, deadlincs, and inter-task
dependencies. This control facilitates the design and implementation
of
complex real-time systems.

g
in
7.3 MULTIPLE TASKS AND MULTIPLE PROCESSES

er
7.3.1 Introduction

e
A Definition:

in
In embedded systems, multitasking or multiple tasking refers to the ability to

ng
effetively carry out several tasks or processes at once. It enables an embedded
fE
system to manage nmultiple tasks concrrently. as opposed to single-tasking
systems, which can only handle one activity at a time. This increases system
O
responsiveness and efficiency.
e

A Real-Time Operating System (RTOS) allows us to run several programs

g

concurrently which helps build more complex systems using several programs
le

that run concurrertly.

ol
C

7.3.2 Tasks and Processes

u

Tasks:
ad

A task is a unit of execution or unit ofwork in a sofware application. Typically.

task execution in an embedded processor is managed by the Operating System
iln

(0S).
m
Ta

P1 P2

P3

Fig7.6 A task made of tliree subtasks

<br>

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7.10| Embedded Systems and IOT Design

Fig 7.6 shows a task that consists of three subtasks and the arrows in the task
graph show data dependencies. P3 cannot start before it receives the results of P1
and P2 where both can execute in parallel.

a Process:
A process is a single execution

g
of a program. run the same program two
If we

in
diferent times, then we have two different processes. Each process has its own

er
state that includes both its registers as well as its memory.

e
In some operating systems, the memory management unit is used to keep each

in
process in a separate address space. In other hand, particularly
lightweight

ng
RTOSs, the processes run in the same address spaçe.
fE
Uncompressed Serial line
Compr essor
Serial line Compressed
O
data data
g e
le
ol
C
u

Compressor
ad

Character Bit queue

iln
m

Compr ession table

Ta

Fig 7.7 Compression box

a Threads:
Processes that share the same address space are often called threads.
Fig 7.7 shows a device which is connected to serial ports on both ends.The input
to the b0x is an uncompressed stream of bytes. The box emits a compressed
string of bits on the output serial line based on a predefined compression table.
<br>

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Processes and Operating Systems

7.11
may be used, to compress
This box
data being sent to a
modem.
I1) Variable Data Rates
There is a need to receive
and send data at different rates.
program may emit two For example, the
bits for the first byte and then seven bits
for the second
hvte. This will reflected in
the structure of the code.

g
in
We need to create a clean data structure
that simplifies the control structure
of

er
the code and also ensure that we process
the inputs and outputs at the proper

e
rates.

in
(2) Asynchronous Input

ng
ò Asynchronous data means it is transmitted and received at variable time
fE
intervals. A single bus architecture was used on early computers.
But Modern
systems are more complex and actually contain a hierarchy of different
O
busses.
e

o For example, the control panel of the compression box may include a
g

compression mode button that disables or enables compression so that the

le

input text is passed through unchanged when compression is disabled.

ol

o Keeping up with the input and output data while checking the button can
C

introduce some very complex control code into the program

u
ad

One solution is to introduce a counter into the main compresion loop so that a
subroutine is used to check the input button which is called once every n times
iln

the compression loop is executed.

m

7.4 MULTIRATE SYSTEMS

Ta

7.4.1 Introduction
A Definition:
are called the
Dystems that use different sampling rates at aifferent stages
multirate systems. These techniques are used to convert the given sampling rate
lo the desired sampling rate and to provide diferent sampling rates through the
system.
<br>

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7.12 Embedded Systems and 1OT Design

We are commonly using the multirate embedded computing systems such as

automobile engines, printers, and cell phones. In all these systems,. certain
operations must be executed periodically, and each operation is executed at its
oWn rate.

g
7.4.2 Timing Requirements on Processes

in
er
Deadline

e
in
P1:

ng
Release time Time
A periodic process
fE
Deadline
O
P1
g e

Release time Time

le

Period
Periodic process initiated at start of period
ol
C

Deadline
u

P1
ad

Release time
Time
iln

Period
Periodic process released by event
m
Ta

Fig 7.8 Definitions of initiation times and deadlines

Based on the application, processes can have different types of timing
requirements.
The timing requirements on a set of processes strongly influence the type of
scheduling. A scheduling policy must define the timing requirements that uses to
determine whether a schedule is valid.
Fig 7.8 illustrates different ways to define two important requirements on
processes: initiation time and deadline.
<br>

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Processes and Operating Systems

|7.13|
Initiation Tme:
The initiation time is the time
at which the process goes fromn the waiting to
the
ready state which is also known as release time.

4 An aperiodic process is the process which is initiated by an event, such as an

g
external data arriving or data computed by another process.
The initiation time is

in
generally measurd from that event, although the system may want
to make the

er
process ready at some interval after the event itself.

e
4 For a periodically executed processes, there are two common possibilities:

in
ng
In simpler systems, the process may become ready at the beginning
of the
period.
fE
The sophisticated systems may set the initiation time at the arrival time of a
O
certain data that time may be after the start of the period.
e

a Deadline
g
le

deadline specifies when a computation must be finished.

A
ol

The deadline for an aperiodic process is, generally measured from the initiation
C

time because that is the only reasonable time reference.

u

The deadline for a periodic process may in general occur at some time other than
ad

.
the end of the period. Some scheduling policies make the simplifying assumption
iln

that the deadline occurs at the end of the period.

m

A Period: Initiation Interval

Ta

The period ofa process is the time between successive executions.

The process's rate is the inverse of its period and in a multirate system, each
Process executes at its own distinct rate.

Fig 7.9 illustrates process execution in a system

ith four CPUs. The various
execution instances of program Pl have been subscripted to distinguish their
initiation times.
<br>

Page 270 of 440

7.14| Embedded Systems and 10T Design

CPU1 Pl Pij+4

CPU2 Pi+1 P1;+5

CPU3 Pli+2 P1;+6

g
CPU4 Plj+3 P1j47

in
er
Time

e
Fig 7.9A sequence ofprocesses with a high initiation rate

in
In this case, the initiation interval is equal to one fourth of the period. It is

ng
possible for a process to have an initiation rate less than the period even in a
single-CPUsystems. fE
a
O
Jitter
Jitter ofa task means it is the allowable variation in the completion of the task.
g e
le

P1 P2
P5
ol
C

P3
u
ad

P6
P4
iln

Fig 7.10Data dependencies anong processes

m

The timing constraints between processes may be constrained when the processes
Ta

pass data among each other. Fig

7.10 shows a set of processes with data
dependencies among them.

Before a process can become ready, all the processes on

which it depends must
complete and send their data to it.
The data dependencies define a partial
ordering on process execution. In this
case, Pl and P2 can execute any
in order but must both complete before P3, and
P3 must complete before P4.
<br>

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Processes and Operating Systems

|7.15

a Task Graph
A set of processeswith
data dependencies is known as a task graph.
The communication among processes of different rates
is very common. Fig 7.11
illustrates the communication required among
three elements of an MPEG

g
audiovideo decoder.

in
er
System Video Audio

e
in
ng
Fig 7.11Communication among processes at
fE
4 Data come into- the decoder in the system format, which multiplexes
diferent rates
audio and
O
video data. Then the system decoder process demultiplexes
the audio and video
data and distributes it to the appropriate processes with different rates.
g e

7.4.3 CPUUsage Metrics

le

A The simple, direct and basic measure of the efficiency of CPUuse is utilization
ol

(U). It is defined as, "the ratio of the CPU time that is being
C

used for useful

computations to the total available CPU time",
u
ad

CPUtimefor useful work

U= Total available CPU time
iln

This ratio ranges between 0 to 1. One means that all ofthe available CPU time is
m

being used for system purposes. Utilization is often expressed as a percentage.

Ta

7.4,4 Process State and Scheduling

* The main function of the operating system is to determine the process that runs
next. The work of choosing the order. of running processes is known as
scheduling.

* The operating system always process to be in one of the following three basic
scheduling states:

(i) Waiting,
<br>

Page 272 of 440

7.16| Embedded Systems and 10T Design

(i) Ready, and

(iii) Executing.

Executing

g
in
er
Chosen
Needs Gets data, CPU ready
to run
data

e
in
Preempted

ng
Ready Waiting
Received data
Needs data fE of aprocess
Fig 7.12 Scheduling states
O
Fig 7.12 shows the possible transitions between states available to a process. A
process goes into the waiting state when it needs data that it has not yet received
g e

or when it has finished all its work for the current period.
le

A process goes into the ready state when it receives its required data (or) when it
ol

enters a new period. A process can go into the executing state only when it has
C

all its data and it is ready to run. The scheduler selects the process as the next
process to run.
u
ad

Scheduling Policy:

scheduling policy defines how processes are selected

iln

for promotion from the

ready state to the running state.
m

7.4.5 Running Periodic Processes

Ta

We need to find a programming

technique that allows us to run periodie
processes at different rates.
Consider a process as subroutines and we
will call
them p1(0, p2(), etc., for simplicity.
Our goal is to run these subroutines a
different rates determined
by the
system designer.
(1) First Step: while loop
Considera very simnple programthat runs our process
subroutines repeatedly:
<br>

Page 273 of 440

Processes and Operating Systems |7.17

while (TRUE ) {

pl ();
p2 ();

g
in
But it does not control the rate at which the processes execute. The
loop runs

er
as quickly as possible, starting a new iteration as soon as the previous iteration
has finished. But, all the processes run at the same rate.

e
in
(2) A Timed Loop

ng
A timer is a much more reliable way to control execution of the loop. So, we
can use the timer to generate periodic interrupts. Let us consider the pal( )
fE
function which is a timer's interrupt handler. Then this code will execute each
process once aftera timer interrupt:
O
void pall (){
e

pl ();
g
le

p2 ();
ol
C

(3) Multiple Timers

u

Now, we have to execute different processes at different rates. If we use the

ad

a rate:
several timers, we can set each timer to different
iln

void pA (O{
/* processes that run at rate A*/
m

pl ():.
Ta

p3 ();

void pB (){
/* processes that run at rate B*/
p2 ();
p4 ();
p5 ();
<br>

Page 274 of 440

7.18| Embedded Systems and 1OT Design

7.5 PREEMPTIVE REAL-TIME OPERATING SYSTEMS

7.5.1 Introduction
(RTOS) solves the fundamental
* A prcemptive Real-Time Operating System
processes based
problems of a cooperative multitasking system. It executes the

g
upon timing requirements provided by the system designer.

in
to build a
The most reliable way to meet timing requirements accurately is

er
process that
preemptive operating system and to use priorities to control the

e
are used to build a basic real
needs to run at any given time. These two concepts

in
ng
time operating system.

7.5.2 Two Basic Concepts fE

To makc our operating system work, we need to simultaneously introduce two
O
basic concepts:
Preemption as an alternative to the function call as a way to control the
e

) C
g

execution.
le

(i) Priority-based scheduling as a way for the programmer to control the order
ol

in which processes run.

C

(1) Preemption
u

To get the full advantage of the timer, we must change our notion of a
ad

process:
iln

Timer Kernel Task 1 Task 2

m
Ta

Fig 7.13 Sequence diagram for preemptive

execution
<br>

Page 275 of 440

Processes and Operating Systems 7.19

allow jumping from one subroutine to another at any
will
point in the
We

program. Together with the timer, this will

allow us to move between
Aunctions whenever necessary based upon the system's timing
constraints.
Ba 7.13 shows an example of preemptive execution of an operating system.
We want to share the CPU across two processes.

g
in
Kernel:

er
The kernel is the part of the operating system that determines what process is

e
raning, which is activated periodicallyby the timer.

in
ng
A Time Quantum:
The length of the timer period is known as the time quantum which is ihe smallest
fE
increment in that we can control CPUactivity.
O
o The kernel determines what process will run next and causes that process to
run. On the next timer interrupt, the kernel may pick the same process or
g e

another process to run.

le

o We can use the timer to control loop iterations, with one loop iteration
ol

including the execution of several complete processes. In general, the time

C

quantum is smaller than the execution time of any of the processes.

u

(2) Context Switching

ad

The set ofregisters that defines a process is known as its context, and switching
iln

Jrom one process 's register set to another is known as context switching.
The

holds the state of the process is known as the record.

m

data structure that

Ta

3) Process Priorities

u We assign each taska numerical priority, then the kernel can simply look at the
Processes and their priorities, and then select the highest-priority process that is

eady to run. This mechanism is both flexible and fast.

7.53 Processes
and Context
Fig 7.14 shows
a sequence diagram in FreeRTOS.org. Here, process is known
a
m FreeRTOS.org
as a task.
<br>

Page 276 of 440

7.20 Embedded Systems and 10T Design

potSAVE_cONTEXTporRESTORE_CONTEXTVTaskSwitchContext task 1
task 2
timer VProemptiveTick

g
in
e er
in
ng
Fig 7.14 Sequence diagram for a FreeRTOS.org context switch
fE
This diagram shows the application tasks, the hardware timer, and
all the
functions in the kernel that are involved in the context
switch:
O
vPreemptiveTick () is called when the timer ticks.
e

SIG OUTPUT_ COMPAREA1A responds to

the timer interrupt and uses
g

portSAVE_CONTEXT() to swap out the current

le

context. task
VTaskIncrementTick( ) updates the time
ol

and vTaskSwitchContext
chooses a new task.
C

portRESTORE_CONTEXT() Swaps in the new context.

u
ad

7.5.4 Processes and Object-Oriented Design: UMI

UML often
Active Objects
processes
refers to as active objects,
iln

that is, objects tht have

independent threads of control. The class
that defines an active object is known
m

as an active class.
Ta

processClass1

myAttributes

myOperations( )

Signals

start
resume.

Fig 7.15An active class in UML

<br>

Page 277 of 440

Processes.and
Operating Systems
7.21

7.15 shows an example of a UML active class. It has all the nomal
# Fig
a-
characteristics of class, including a name, attributes, and operations. also
It
provides. a set ofisignals that can be used to communicate with
the process.

A signal is an object that is passed between processes for asynchronous

*

g
communication.

in
a: rawMsg

er
ahat: fullMsg
pl: processClass1 W: WrapperClass

e
master: masterClass

in
ng
Fig 7.16 A collaboration diagram witlh active and normal objects
a
We can mix both the active objects and normal objects. Fig 7.16 shows simple
fE
an interface between two
collaboration diagram in which an object is used as
O
processes.
data before the data is sent to the master
e

4 pl uses the w object to manipulate its

g

process.
le

ANSWERS
7.6 TWO MARKS QUESTIONS AND
ol

.
C

What do you mean by real-time system?

some specific tasks. It
used for performing
Real-time system is a system which is
u

real-time tasks.
used for various hard and soft
ad

IS a computational system which is

The tasks assigned
are mainly related with time constraints.
iln

Ihese specific tasks

interval.
completed in a given time
Oreal-time systems need to be
m
Ta

What is real-tine embedded systenis?

real-time tasks are
which are designed to perform
The embedded systems
or. Real-time Embedded Systems.
known as Embedded Real-time Systems

3, List the types

of embedded
real-time systems.
real-time systems:
There are
two types of embedded

) Hard Embedded Real-time System: reai-time

systems that are used to perform hard
real-time
he embedded embedded real-time system. These systems
are
as Hard
asks are called
way and are accurate systems.
designed in a very complicated
<br>

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7.22 Embedded Systems and IOT Design

(ii) Soft Embedded Real-time System:

These are embedded real-time systems that are
used to perform soft real-time
tasks. These are simple designed systems and there are chances of
inaccuracy.

g
4. Define task assignments.

in
Task assignment is the process of allocating specific tasks or
responsibilities to

er
individuals or teams within an organization. It involves deternmining
who is

e
responsible for completing a task, by providing them
with the necessary

in
information and resources, and setting clear expectations for the desired outcome.

ng
5. List the reasons for task assignment.
fE
Task assignment is important for the following reasons:
(i) It ensures that work is distributed efficiently
O
and effectively among team
members.
e

(iü)) It allows for better utilization of individual skills

g

and expertise.
le

(ii) It helps in balancing workload and avoiding bottlenecks or

overload.
ol

(iv) It promotes accountability and clarity regarding

responsibilities.
C

(v) It improves productivity and task completion within

the desired timelines.
u

(vi) It facilitates effective collaboration and

coordination among team members.
ad

6. What is scheduling?
iln

(or)
Why the sclheduling status considered iin
m

a
process? [APR/MAY-2023]
The way
Ta

that time is allocated between tasks is termed as "scheduling".

The
scheduler is the software that determines which task
should run next. The logic of
the scheduler and the mechanism that determines when it should
be run is the
scheduling algorithm.
7. Write about scheduling states present in the embedded system
design.
[NOVDEC-2016|
There are three basic scheduling states present in the embedded system design:
<br>

Page 279 of 440

Processes. and Operating Systems

|7.23
Waiting,
)
(i) Ready, and
(i) Executing.
Differentiate betveen preemptive
and not-preemptive scheduling.

g
Preemptive scheduling

in
is the most commoniy used schcduling
aigorithm in real
time systems. Here, the

er
tasks are prioritized and the task with the
among all other
highest priority
tasks gets the CPU time.

e
in
In the case of a non-preemptive scheduling, even the highest
if priority is

ng
allocated to the task, needs to
it wait until the completion of the current
This can task.
task be either slow (or) lower priority, which can
9.
fE lead to a longer wait.
Why preemptive scheduling
is preferred in real time operating systems?
O
[APRMAY-2019)
e

Preemptive scheduling is used in real-time systems

g

where the tasks are usually

configured with different priorities and
le

time critical tasks are given higher

priorities. A higher priority task can stop a
ol

lower priority one at any time, grab

and use the CPUuntil it releases it.
C

10. Write the advantages of scheduling in real-time systems.

u
ad

The advantages of scheduling in real-time systems are,

() Meeting timing constraints,
iln

(i) Resource optimization,

m

(in) Priority-based execution,

Ta

() Predictability and determinism, and

() Control over task execution.

Define
multitasking or multiple tasking.

(or)
What is
the concept of multitasking? Whatt does it sigify? [NOVIDEC-2018]
In embedded
systems, multitasking refers to the ability to effectively carry out
Several
tasks or processes at once. It enables an embedded system to manage
<br>

Page 280 of 440

7.24 Embedded Systems and 10T Design

multiple tasks concurrently, as opposed to single-tasking systems, which can only

.handle one activity at a time. This increases system responsiveness and efficiency.
12. Whatis RTOS?
A Real-Time Operating System (RTOS) allows us to run several programs

g
concurrently which helps build more complex systems using several programs

in
that run concurrently.

er
13. Define tasks and processes. [NOVIDEC-2016]

e
A task is a unit of execution or unit of work in a software application. Typically,

in
task execution in an embedded processor is managed by the Operating System

ng
(OS).
fE
A process is a single execution of a program. we run the same program two
If
different times, then we have two different processes. Each process has its own
O
state that includes both its registers as wellas its memory.
e

14. Define threads.

g
le

Processes that share the same address space are often called threads.
ol

15. Define multirate systems and give two real-time exanples. [APRIMAY-2023]
C

Systems that use different sampling rates at different stages are called the
u

multirate systems. These techniques are used to convert the given sampling rate
ad

to the desired sampling rate and to provide different sampling rates

through the
system.
iln

Examples:
m

Traffic control unit & Online trading system.

Ta

16. What is initiation time?

The initiation time is the time at which the process goes
from the waiting to the
as
ready state which is also known release time.
17. What do you mean by deadline andjiter?
A deadline specifies when a computation must be finished.
Jitter of a task means it is the allowable variation in the completion
of the task.
<br>

Page 281l of 440

Processes and Operating Systems 7.25

J8. Define utilization() of CPU.

(or)

Define CPU usage metrics.

The simple, direct and basic measure of the efficiency
of CPU use is utilization

g
(U), It is defined as, "the ratio of the CPU time that is being used for useful

in
computations to the total available CPU tme".

er
CPUtime for useful work

e
U= total available CPU time

in
This ratio ranges between 0 to l.

ng
19.
fE
Write the function of scheduling policy.
O
A scheduling policy defines how processes are selected for promotion from the
e

ready state to the running state.

g

20. Define kernel.

le

The kernel is the part of the operating system that determines what
process is
ol

running, which is activated periodically by the timer.

C

21. What is time quantum?

u

as the time quantum which is the

ad

The length of the timer period is known

Smallest increment in that we can control CPU activity.
iln

22. Define context switching in RTOS. [APRIMAY-2018]

m

a process is known as its context, and switching

The set of registers that defines
Ta

Irom one process's register set to

another is known as context switching.

43. Define active objects and active class.

as active objects, that is; objects that have
UML often refers to processes
an active object is known
Independent threads of control. The class that defines
as an active class.

7.7 REVIEW QUESTIONS

of a real-time system.
Discuss in detail about the structure
structure of embeddedreal-time system.
*With neat sketches, explain the
<br>

Page 282 of 440

7.26 Embedded Systems and IOT Design

3. Explain in detail about task assignment and scheduling.

4. Give brief note on scheduling of real-time systems.
5. List the advantages of
schedulingin rea-time systems.
6. Discuss in detail about multitasking and multiprocessing. [NOVDEC-2016]

g
in
7. Sumnarize the services of operating system in handling nmultiple task and

er
multiple processes. [APRMAY-2018]
Explain how multiple processes are handled by preemptive real time operating

e
8.

in
system. [NOVDEC-2017]

ng
9. Discuss why preenptive scheduling is preferred in real time operating systems.
fE [APRMAY-2019]
10. With neat sketches, explain about nultirate ystems.
O
II. Explain in detail about preemptive real-time operating systems.
g e
le
ol
C
u
ad
iln
m
Ta
<br>

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UNIT - III
Chapter 8

g
NETWORKS AND

in
e er
MULTIPROCESSORS

in
ng
8.1 PRIORITY-BASED SCHEDULING
fE
8.1.1 Introduction
O
The operating system's fundamental job is to allocate resources in the computing
e

system among programs that request them. So scheduling the CPU is one
of
g

most important job of the operating system.

le

In priority scheduling, a task can be stopped or suspended in order to allow a

ol

task of higher priority to run. In the case of two tasks of the same high priority
C

each is given an equal time slice.

u

(1) Round-Robin Scheduling

ad

A common scheduling algorithm in general-purpoe operating systems is

iln

round robin, in which all the processes are kept on a list and scheduled one
m

after the other.

Ta

Round-robin scheduling provides a chance for all processes to execute, but it

does not guarantee the completion time of any task. As the number of
processes increases, then the response time of all the processes gets increases.
2) Process Priorities
A common way to choose the next executing process in an RTOS is based on
the process priorities. Each process is assigned a priority which is an integer
valued number. The highest-valued priority ready process will be selected for
execution.
<br>

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8.2 Embedded Systems and 10T Design

Process Priority Execution time

Pi 1
10

P2 2 20

g
P3 3 30

in
er
Table: 8.1 Process priority table

e
8.1.2 Rate- Monotonic Scheduling (RMS)

in
Rate-Monotonic Scheduling (RMS) was one of the first scheduling policies

ng
developed for real-time systems and it is still very widely used. The
priority is
decided according to the cycle time of the processes that are involved. The
fE
process with a small job duration (shortest
period), has assigned a highest
O
priority.
e

If a process with highest priority starts execution, then it will preempt

the other
g

running processes. The priority of a process is inversely

le

proportional to the
period it will run for.
ol

RMS is a stati scheduling policy because it assigns

C

fixed priorities to processes

which effectively schedule the processes many
in situations. The RMS uses Rate
u

Monotonic Analysis(RMA)which is summarized as follow:

ad

Allprocesses run periodically on a single CPU.

iln

Context switching time is ignored.

m

There are no data dependencies between processes.

Ta

The execution time for a process is constant.

Alldeadlines are at the ends of their periods.

The highest-priority ready process is always selected

for execution.
a Response Time:
The response time of a process is the time at which the process finishes.
<br>

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Nenworks and Multiprocessors

8.3
Critical Instant:

The critical instant for a process is defined as the

instant during execution at
suhich the task has.the largest response time.

Utilization:
() CPU

g
The RMS is the optimal static-priority schedule but it
does not allow the

in
Svstem to use 100% of the available CPUcycles.
A set of processes can be

er
scheduled only if they satisfy the following equation:

e
C

in
M
n - 1).
S (21/n

ng
i =1

Where,
n -Number of processes (tasks) in the process set,
fE
O
C- Computation time of the process,
e

T,- Time period for the process to run, and

g

-
U
Processor utilization.
le

o For 'n' tasks, the maximum processor utilization is

ol

- 1)
C

U= n(21/n
willnot be
of two tasks under RMS scheduling, the CPUutilization
u

For a set
ad

greater than 2 (22-1)

=
0.83. As n approaches infinity, thenUwill be 0.69
that is, the CPU willbe idle 31%
of the time.
iln

(2) Example
m

Execution time (C) Time period (T)

Ta

Processes
3 20
P1
5
2
P2
2 10
P3
Solution:

Number of processes, n =3
U= n(21/n - 1)
<br>

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8.4| Embedded Systems and IOTDesign

=
= 3
(23-1) 3(20.33- 1)

=3(1.257- 1)=3 (0.257)

U
=0.77

(or)

g
2

in
n
2
3
-0o ++o= 0.15 +
0.4+ 0.2

er
i=1

U= 0.75

e
in
It is less than 1-or 100% utilization. The combined utilization of three

ng
processes is less than the threshold of these processes which means the
above set of processes is schedulable and thus satisfies the above equation of
fE
the algorithm.
O
(i) Scheduling time
For calculating the scheduling time of the algorithm we have to take the LCM
e

of the time period of all the processes. In the above example, LCM (20, 5, 10)
g
le

is 20. Thus, we can schedule it by 20-time units.

ol

(ii) Priority
C

The priority will be the highest for the process which has the least running
u

time period. Thus, P2 will have the highest priority, and after that P3 and
ad

lastly P1.
iln

P2 > P3 > P1
2
m

2 2 2
P2
Ta

5 10 20
15
2
2
P3
10 20

3
P1
0 20

Fig 8.1 Representation and flowgraph

<br>

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Networks and Multiprocessors

8.5|
. Process
P2 will execute two times for every
5 time units, Process
execute two times for every 10 P3 ill
time units and Process P1 will execute
times in 20 time units. This has to three
be kept in mind for understanding
entire execution of the algorithm below: the

P2P2 P3| P3 P1 P2| P2 P1 P1

P2 P2 P3 P3 | P2 P2

g
0 1
2 3 4 5 6 7 8

in
10 11 12 13 14 15 16 17 18 19 20

er
Fig 8.2 Total execution time

e
(3) Advantages and Disadvantages

in
E Advantages

ng
The advantages of RMS are,

() It is easy to implement.
fE
O
(ii) If any static priority assignment algorithm can meet the deadlines then rate
monotonic scheduling can also do the same. It is optimal.
g e

(ii) It consists of a calculated copy of the time periods.

le

B Disadvantages:
ol

() It is very difficult to support aperiodic and sporadic tasks under RMA.

C

(i) RMA is not optimal when the task period and deadline differ.
u
ad

8.1.3 Earliest-Deadline-First (EDF) Scheduling

iln

Earliest Deadline First (EDF) is an optimal dynamic priority scheduling

m

algorithm sed in real-tine .systems. EDF uses priorities for scheduling which
Ta

assigns priorities to the task according to the absolute deadline.

* The task whose deadline is closest gets tlhe highest priority. The priorities are
assigned and changed in a dynamic fashion. EDF is very eficient as compared to

other scheduling algorithms in real-time systems. It can make the CPU utilization
l0 about 100% while still guaranteeing the deadlines of all the tasks.
<br>

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8.6 Embedded Systems and IOT Design

S.No RMS EDF

Achieves lower CPU utilization. Higher CPUutilization.
2 Easier to ensure that all deadlines Hard to ensure deadlines.
will be satisfied.

g
in
3 Static priority scheduling. Dynamic priority scheduling.

er
4 Not expensive to use in practice. Expensive to use in practice.
- period process gets

e
5 Shortest Process closest to its deadline has

in
highest priority. highest priority.

ng
Table 8.l Comparison between RMS and EDF

3.1.4 Shared Resources

fE
O
A process may need more read and write values to and from memory. It may use
the shared memory locations to communicate with other processes.
g e

(1) Race Condition

le

An I/O device has a flag that must be tested and modified by a process.
ol

If
combinations of events from the two tasks operate on the device
in the wrong
C

order, we may create critical timing race or race condition that causes
u

erroneous operation.
ad

A Definition:
iln

A race condition is an undesirable situation that occurs when a

device or system
m

attenpts to perform two or more operations at the same time, but because of the
nature of the device or system, the operations must be done in the proper
Ta

sequence and it need to be done correctly.

(2) Critical Sections

The critical section refers to the segment of code where processes access
shared resources, such as common variables and fles, and perform write
operations on them.
<br>

Page 289 of 440

Networks and
Multiprocessors 8.7

The critical section problem is used to design a protocol followed by a group

of processes, so that when one process has entered its critical section, no other
process is allowed to execute in its critical section.

Process

g
Entry Section

in
er
Critical Section

e
Exit Section

in
ng
Fig 8.3 Critical section fE
(3) Semaphores
O
a Definition:
e

Semaphores are just normal variables that are used to coordinate the activities
g

are used to enforce mutual

of multiple processes in a computer system. They
le

exclusion, avoid race conditions, and implement synchronization between

ol
C

processes.
o The process of using semaphores provides two operations: wait (P) and
u
ad

signal ().
signal
o The wait operation decrements the value of the semaphore, and the
iln

operation increments the value of the semaphore.

m

0 .The semaphore use to gain access fo the protected resource and VO to

Ta

P()
release it.

*/
/*some nonprotectedoperations here
P();/*wait for semaphore */

work here */
/* do protected
V();/*release semaphore */
<br>

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8.8 Embedded Systems and IOT Design

8.1.5 Priority Inversion

* Priority inversion is a situation that can occur when a low-priority process
resources. The
blocks the execution of a higher-priority process by holding its
most common method for dealing with priority inversion is priority inlheritance.

g
in
a Priority Inheritance:

er
The basic idea to promote the priority of any
of the priority inheritance is
process when it requests a resource from the operating system. The priorily of

e
the process temporarily becomes higher than that of any other
process that may

in
ng
use the resource.

8.2 INTERPROCESS COMMUNICATION MECHANISMS

fE
O
8.2.1 Introduction
Processes often need to communicate with each other. Inter process
e

communication mechanisms are provided by the operating system as part of the

g
le

process abstraction.
In general, a process can send a communication in one of two ways:
ol

() Blocking, and
C

(ii) Nonblocking.
u

After sending in a bocking communication, the process goes into the waiting
ad

state until it receives a response. Nonblocking communication allows the

process to continue execution after sending the communication.
iln

There are two modes through which processes can communicate with each other:
m

() Shared memory, and

Ta

(ii) Message passing.

The shared memory region shares a shared menmory between the processes. On
the other hand, the message passing lets processs exchange information through
messages.

8.2.2 Shared Memory Communication

Fig 8.4 illustrates how shared memory communication works in a bus-based
system. Here, a CPU and an VO device is communicated through a shared
<br>

Page 291l of 440

Netvorks and Multiprocessors 8.9|

memory location. The software on the CPU
has been designed to know the
address of the shared location which has also been loaded into proper the register
of the I/O device.

g
Shared

in
CPU location /O device

er
Nemo

e
in
Write

ng
Read

fE Bus

Fig 8.4 Slhared memory commumication inplemented on a bus

O
4 If the CPU wants to send data to the device., it first writes to the shared location.
e

The I/O device then reads the data from that location.
g
le

8.2.3 Message Passing

ol

4 In the message pussing node, proccsses interact with each other through
C

messages with assistance from the anderlying operating system.

u
ad

Process A M
Writes
Data
iln

Process B M
Reads
m

Dala
Ta

Kernel M

Fig 8.5 Message passing communication

<br>

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8.10| Embedded Systems and 10T Design

other through
In Fig 8.5, two processes A, and B are communicating with each
message passing. Process A sends a message M to the operating system (kernel).
This message is then read by process B.
own message send/receive
Each communication entity (CPUor process) has its

g
unit.

in
(1) Queues

er
queue uses a FIFO
A queue is a common form of message passing. The

e
discipline and holds records that represent the messages.

in
The FreeRTOS.org system provides a set of
queue functions which allows

ng
queues to be created and deleted so that the system may have as many queues
as necessary. fE
Process P1
O
Process P2
g e
le

Message Queue
ol

Kernel
C

Fig 8.6 Message queue

u
ad

8.2.4 Signals
iln

An interprocess communication commonly used in Unix is the signal which does

not pass data.
m
Ta

A signal a notification to a process indicating the occurrence of an event.

is

Signal is also called software interrupt and it is not predictable to know its
occurrence; hence it is also called as an asynchronous eyent.

UML signal is an object which can carry parameters as object attributes.

4 Fig 8.7 shows the use of a signal in UML. The sigbehavior () behavior of the
class is responsible for throwing the signal, as indicated by <<send>>, The signal
object is indicated by the <<signalb> stereotype.
<br>

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Netvorksandd Multiprocessors 8.11|

someClass

<signal>>
aSig <<send>>
sigbehavior)

g
p: integer

in
er
Fig 8.7 Use ofa UML signal

8,2.5 Mailboxes

e
in
The mailbox is a simple mechanism for asynchronous communication. It has a

ng
fxed mumber of bits and can be used for small messages. Some architectures
define mailbox registers.
fE
# We can implement a mailbox by using P( ) and V( ) in main memory for the
O
mailbox storage. A very simple version of a mailbox that it holds only one
message at a time.
g e
le

Task2
ol
C

Mailbox

-I
u

Task3
ad
iln

Task4
m
Ta

Fig 8.8 Relation betiveen task and mailbox

DISTRIBUTED EMBEDDED SYSTEMS: NETWORKS FOR IoT

.3
8.3.1 Introduction
A Distributed Embedded System:
In a distributed embedded system, several Processing Elements (PEs)
are

connected by a nehvork that allows them to communicate. Processing elements

may includes DSP. CPU or microcontroller. Nonprogrammable unit such as the

ASTCs is also used to implement as PE.

<br>

Page 294 of 440

|8.12 Embedded Systems and 10T Design

or multiprocessor with the reason that its

It differs from parallel computing
messages.
individual nodes have much higher independence for passing the
a embedded system, it is required to
For analyýzing the performance of distributed
are associated with it along with its problems and
know many basic terms which

g
to 'solve these problems include simulation

in
the ways to solve it. The approaches
as scheduling technique.
technique and also scheduling technique such holistic

e er
8.3.2 Network Abstractions: The 0SI Model

in
services while
Networks are complex systems which ideally provide high-level

ng
hiding many of the details of data transmission from the other
components in the
system. fE
Application End-use interface
O

Presentation Data format

g e

Session Application dialog control

le

Transport
ol

Connections
C

Network End-to-end service

u

Data link Reliable data transport

ad

Physical Mechanical, electrical

iln

Fig 8.9 The OSI model layer

m

The International Standards Organization (1So) has developed a seven-layer

Ta

model for networks known as Open Systemn Interconnection (0S) models. This
OSI layers will help us to understand the details of real networks.

The seven layers of the OSI model is shown in Fig 8.9 which are proposed to
cover a broad spectrum of networks and their uses. Some networks may not need
the services of one or mor layers because the higher layers may be totally
missing or an intermediate layer may not be necessary.
Any data network should fit into the OSI model which includes seven levels of
abstraction known as layers:
<br>

Page 295 of 440

Networksand Multiprocessors
8.13
(0 Physical Layer:
This layer defines the basic
properties of the interface between systems which
includes the physical connections
(plugs and wires), electrical properties,
functions of the electrical and physical components,
basic
and the basic procedures for
exchanging bits.

g
in
(ü) Data link Layer:

er
The primary purpose of this layer is error detection and control across a single

e
link.

in
(ii) Network Layer:

ng
This layer defines the basic end-to-end data transmission service
fE which is
particularly important in the multi-hop networks.
O
(iv) Transport Layer
This layer defines connection-oriented services which ensures that data are
g e

delivered in the proper order and without errors across multiple links. This layer
le

may also try to optimize network resource utilization.

ol

(v) Session Layer

C

A session layer provides mechanisms for controlling the interaction of end-user

u

services across a network, such as data grouping and check potnting.

ad

(vi) Presentation Layer

iln

to
This layer defines data exchange formats and provides transformation utilities
m

an application programs.
Ta

(vil) Application
Layer
between the network and
Ihe application layer provides the application interface
end-user programs.

A simple embedded network provide physical, data

link, and network services.
Anincreasing number of embedded systems provide Internet service that requires
of functions in the OSI model.
implementing the full range
<br>

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Embedded Systems and 10T Design

8.14|

8.3.3 CAN Bus

a Definition:
to
Controller Area Network (CAN bus) is a vehicle bus standard designed
A

allow icrocontrollers and devices to communicate with each other's

g
applications without a host computer.

in
Microcontroller

e er
in
CAN controller

ng
fE
CAN Transceiver
O
e

SDL
g

CAN Bus lines

le

SCL
ol

Fig 8.10 CAN interface ir' embeddedsystem

C

The CAN bus was designed for automotive

electronics and first used in
u

production cars in 1991. It is well

ad

suited to the requirements

electronics such as reliability, low power of automotive
consumption, low weight,
and low cost.
iln

CAN uses bit-serial communication and runs

at rates of 1 Mb/s over a twisted
m

pair connection of 40 m. An optical

link can also be used, This
bus protocol
Ta

supports multiple masters on the bus.

(1) Physical Layer

In Fig 8.11, each node in the CAN bus
has its own electrical drivers and
receivers that connect the node to the bus in wired-AND
fashion, In CAN
terminology, a logical I on the bus is called a
recessive and logical 0 is
dominant.
<br>

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Nenworks and Multiprocessors

8.15
1= recessive

0
dominant

g
in
e er
in
ng
Node Node

fE a
Fig 8.11 Plysical and electrical organization of
CAN bus
O
When all nodes are transmitting ls, the bus is said to be in the recessive state;
when a node transmits a), the bus is in the dominant state. Data are sent on
eg

the network in packets known as data frames.

le

CAN is a synchronous bus because all transmitters must send at the same
ol

time for bus arbitration to work.

C

(2) Data Frame

u

The format of a CAN data frame is shown in Fig 8.12. A data frame starts
ad

with a 1 and ends with a string of seven zeroes. The first field in the packet
contains the packet's destination address which is known as' the arbitration
iln

field.
m

Transmission
The destination identifier is 11 bits long. The trailing Remote
Ta

to request data from thé

Request (RTR) bit is set to 0 if the data frame is used
device specified by the identifier.
When RTR = 1, thepacket is used to write data to the destination identifier.
The control field provides an identifier extension
and a 4-bit length for the

data field with a 1 in between them.

on the value given in the
The data feld is from 0 to 64 bytes, depending
is used for error detection.
control field. A Cyclic Redundancy Check (CR)
<br>

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8.16| Embedded Systems and 10T Design

The acknowledge field is used to check whether the frame was correctly
received.
12 6 0 to 64 16 2

Start

g
Arbitration field
Acknowledge End of

Control field Data field CRC field

in
field frame

er
Value=1 Value =0

e
in
transmissiorj

ng
ldentifier
Remote request
bit
Data
length
fE ACK ACK
slot delimiter
code
O
e

11 1 1
g

4
1 1
le

Fig 8.12 The CAN dataframe

format
ol

(3) Arbitration
C

Control of the CAN bus is

arbitrated using a technique
Sense Multiple Access with known as Carrier
u

Arbitration on Message
Priority (CSMA/AMP).
ad

CAN encourages a data-push

programming style. Network
synchronously, so that they nodes transmit
all start sending their identifier
iln

fields at the same

time.
m

When a node hears a dominant

bit in the identifier
if it tries to send a recessive
Ta

bit, it stops transmitting.

a Remote Frames:
A remote frame is used to request data from another
node.
(4).Architecture
o
Fig 8.13 shows the basic architecture
of a typical CAN controller which
implements the physical and data link layers; because CAN is a bus. it does
not need network layer services to estäblish end-to-end connections.
<br>

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TENeKorks and Multiprocessors

|8.17

Status/control
Protocol registers
CAN controller Host +Host
bus interface
Message

g
objects

in
er
Receive

e
buffer

in
Fig 8.13 Architecture of a CAN

ng
COntroller
The protocol control block is
responsible for determining
fE
messages, whena message when to send
must be resent due to arbitration
a message should be received. losses, and when
O
e

8.3.4 Distributed Computing

in Cars and Airplanes.
g
le

Cars provide an ideal opportunity

for message passing style multiprocessing.
A.
ol

car is controlled
by a network of processors that each has its own
responsibility
C

and also communicate with other processors to

make sure that the different
subsystems act together.
u
ad
iln

Engine
m
Ta

Transmission

ABS

Fig 8.14 Major elements

of
anautomobile network
<br>

Page 300 of 440

Fig 8.14 shows a car network and

three major subsystems in the car
mechanical system that is controlled which are
by a processor:
i) Engine,
(ii) Transmission, and
(ii) Anti-lock Breaking System(ABS).

g
Aircraft electronics are known as

in
avionics. The most fundamental
between avionics and automotive difference

er
electronics is certification.
Anything that is
permanently attached to the aircraft
must be certified. The certification process

e
for production of aircraft is in two

in
phases:

ng
(i) Design is certified in a process
is known as type certification,
(iü)
and
The manufacture of each aircraft fE
is certified during production.
The traditional architecture for an
avionics system has a separate
O
function: artificial horizon, engine unit for each
control, flight surfaces, etc.
These units are
e

known as Line Replaceable Units

(LRUs) and are designed to
g

and unplugged into the aircraft during be easily plugged

le

maintenance.
ol

8.3.5 I'C Bus

C

The Inter Integrated Circuit

(I) bus is used to interconnect
u

within small-scale embedded systems. is a peripheral devices

ad

It well-known bus commonly used to

link microcontrollers and other modules into the systems. .
iln

M Advantages
m

() Easy to implement,
Ta

(ii) Low cost, and

(ii) Moderate speed up to 100 kbis/s for the standard bus and up to 400 kbis/s
for the extended bus.
(1) Physical Layer
IC uses only two lines:
() Serial Data Line (SDL) for data, and
<br>

Page 301l of 440

Networks and Multiprocessors 8.19|

G) Serial Clock Line (SCL) indicates when there is a valid data on the data
line.

Master 1
Slave 1

g
SDL

in
er
SCL

e
in
Master 2

ng
Fig 8.15 Structure of an FC bus system
fE
Fig 8.15 shows the structure 'of a typical I'C bus system. Every node in the
O
network is to both SCL and SDL. Some nodes may be able to act as
connectd
may act
bus masters and the bus may have more than one master. Other nodes
g e

as slaves that only respond to requests from masters.

le

(2) Data Link Layer

ol

a
A bus transaction is comprised of series of 1-byte
transmissions and an
C

address followed by one or more data bytes.

u

When a master wants to write slave, it transmits the

a slave's address followed
ad

a transfer, the master must send a

by the data. Because a slave cannot initiate
iln

read request with the slave's address and

the slave transmit the data.
m

Device address RW
Ta

1 bit
7 bits

address transmission
Fig 8.16 Format of anIC
is shown in Fig 8.16. An address
The format of an address transmission
1
bit for data direction:
transmission includes the 7-bit address and
(1) 0 - Writing from the
master to the slave, and
master.
(1) 1-Reading from the slave to the
<br>

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|8.20 Embedded Systems and 10T Design

A master can write and then read (or) read and then write by sending a start
after the data transmission, followed by another address transmission and then
more data.
o The basic state transition graph for the master's actions in a bus transaction is
shown in Fig 8.17.

g
in
Address

er
Start
Address, 0

e
Idle Start

in
Address,

ng
Start
Stop Get
Data fE Data Send
read data write data
O
Stop
e

Fig 8.17 State transition graplh for an IC bus master

g

The formats of some bus transactions are

le

shown in Fig 8.18. In the first one,

the master writes two bytes to the addressed
ol

slave. In the second, the master

requests a read from a slave.
In the third, the master writes one byte to
C

the
slave and then sends another to initiate a
read from the slave.
u

Start
ad

7-bit address 0 Data Data

Write
iln

s7-bit address 1
m

Data P Stop
Read From slave
Ta

s 7-bit addr ess 0 Data 7-bit address 1

Data P
Write
Read From slave
Fig 8.18 Typical bus transactions on the FC bus
(3) Application Interface
o Fig 8.19 illustrates a typical system has a 1-bit hardware interface with
routines for byte level functions. The
IC device takes care of generating the
<br>

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Networks and Multiprocessors

8.21|
clock and data. The application
code calls routines to send an
address, a data
byte, and so on, which then generates
the SCL and SDL and acknowledges.

SCL SDL
Application
Interrupt

g
Bytes
Driver

in
Microprocessor

er
device
Bits

e
Memory

in
Control
Data

ng
Microcontroller fE
O
Fig 8.19 An IC interface in a microcontroller
Microcontroller's timer is typically used to control the length of bits on
e

the
g

bus. Interrupts may be used to recognize bits and masters to initiate their own
le

transfers.
ol

8.3.6
C

Ethernet
Ethernet is very widely used as a Local Area Network (LAN) for.general -
u
ad

purpose computing. Because of its ubiquity and the low cost of Ethernet
interfaces, it is used as a network for embedded computing.
iln
m
Ta

A B C

Fig 8.20 Ethernet plhysical orgaization

PIg 8.20shows the physical organization of an Bthernet. The network is a bus
WIth a single signal path. Ethernet standard allows for several different
implementations such as twisted pair and coaxial cable.
<br>

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8.22 Embedded Systems and 10T Design

(1). Arbitration Scheme:

The Ethernt arbitration scheme is known as Carrier Sense Multiple Access
with Collision Detection (CSMA/CD). This algorithm is outlined in Fig 8.21.

Start

g
in
er
Ethernet Increment
No

e
Yes

in
ng
Transmit

Yes
fE
<Collision? Abort Wait backup
O
No
e

No
g

Done?
le

Yes.
ol

Finish
C

Fig 8.21 Ethernet CSMA/CD algorithm

u

A node that has a message waits for the bus and then starts transmitting. It
ad

simultaneously listens to check whether any another transmission that

iln

interferes with this transmission. If anything means it stops transmitting and

m

waits for retransmit.

Ta

The waiting time is random, but weighted by an exponential function of the

number of times the message has been aborted.
(2) Ethernet (|EEE 802.3) Packet Format (or) Frame Format
DESTINATION: SOURCE
PREAMBLE LENGTH DATA
ADDRESS ADDRESS CRC
D

7 Bytes 1 Byte 6 Bytes 6 Bytes 2 Bytes 46-1500 4

Bytes
Bytes

Fig 8.22 Ethernet packet format

<br>

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Networks and Multiprocessors

|8.23|
o Fig 8.22 shows the basic format of an Ethernet
packet. It provides addresses of
both the source and destination and Cyclic
Redundancy Check(CRC)
provides error detection.

Preamble
()
Ethernet packet starts with a 7-bytes Preamble. This is a pattern
of alternative

g
0's and 1's which indicates starting of the frame and allow sender and receiver

in
to establish bit synchronization.

er
() Start of Frame Delimiter (SFD)

e
in
This is a 1-byte field that is always set to 10101011. SFD indicates that

ng
upcoming bits are starting the packet, which is the destination address.

(i) Length fE
Length is a 2-byte field, which indicates the length of the entire Ethernet
O
packet.
e

(iv) Data
g
le

This is the place where actual data is inserted which is also known as
payload.
ol

8.3.7 Internet Protocol (IP)

C

Definition
u
ad

The internet layer defines an official packet format and protocol called Internet
Protocol (1P) that provides a connectionless, best-effort delivery service of
iln

packets across the Internet.

m

Industrial automation is a good application area for Internet-based embedded

Ta

systems.

* The term Internet generally means the global nework of computers connected by
the Internet Protocol. In general, an Internet packet will travel over several
different networks from source to destination. The rçlationship between IP and
ndividual networks is illustrated in Fig 8.23.
<br>

Page 306 of 440

8.24 Embedded Systems and 10T Design

Application Application
IP

Transport Transport

Network Network Network

g
Data link Data link Data link

in
Physical Physical Physical

er
Node A Router Node B

e
in
Fig 8.23 Protocol utilization in Internet communication

ng
IP works at the network layer. When node A wants to send data to node B, the
application's data pass through several layers of the protocol stack to get to the
fE
Internet Protocol.
O
IP creates packets for routing to the destination, which are then sent to the data
link and physical layers. A node that transmits data among different types
e

af
networks is known as a router.
g
le

In general, a packet may go through several routers to get to its destination. At

ol

the destination, the IP layer provides data to the transport layer

and ultimately the
C

receiving application. The IP packet data are encapsulated

in packet formats
appropriate to each layer.
u

a
ad

Best- effort Delivery:

Best-effort delivery describes a network service in
which a network does not
iln

provide any guarantee that data is effectively delivered or that delivery meets
any quality of 'service.
m
Ta

(1) IP Packet Structure

The basic format of an IP packet is shown in Fig 8.24. The header and data
payload are both of variable length. The maximum total length of the header
and data payload is 65,535 bytes.
Each IP packet contains both a header (20 or 24 bytes long) and data (variable
length). The header includes the IP addresses of the source and 'destination.
plus other fields that help to route the packet.
<br>

Page 307 of 440

Networks and Multiprocessors

8.25
4 bytes (32 bits)
Version Header Service
length type Total length

Identification
bytes
Flags Fragment offset
Header Time to live
Protocol

g
24 Header checksum

in
Source address

er
Destination address

e
Options and padding

in
ng
Data
payload Data
fE
O
Fig 8.24 IP packet structure
e

(a) Version (VER)

g

It specifies the IP protocol version of the packet. For

le

IPv4, its value is 4.

ol

(b) Header Length (HLEN)

C

Header Length tells the number of 32-bits (or) 4 byte word in the header
and it is
used to describe its length.
u
ad

(c) Services: 8 bits

iln

It specifies the type of service.

(d) Total Length: 16-bit
m

This field defines the entire packet size, including header and data, in bytes.
Ta

(e) Identification: 16-bit

It is primarily used for uniquely identifying fragments of an original IP datagram.
) Flags: 3 bits

tis used to control (or) identify fragments. They. are,

zero.
bit0: Reserved; must be
bit 1: Don't Fragment (DF)
bit 2: More Fragments (MF)
<br>

Page 308 of 440

8.26 Enbedded Systens and IOT Design

M
D:Do not fragment
O D| M:More fragments

Fig 8.25 Flags in IPy4

(e) Fragment Offset: 13 bits

g
It is a pointer that shows the offset ofa particular fragment data in the original

in
unftagmented (original) IP packet.

er
(h) Time To Live (TT): 8 bits

e
This shows the number of stations a packet can travel before it is discarded.

in
ng
(i) Protocol: & bits
It defines which upper-layer protocol data are encapsulated in the datagram, such
fE
as TCP, UDP, ICMP and IGMP.
O
Välue Protocol
e

1
ICMP
g

2 IGMP
le

6 TCP
ol

17 UDP
C

89 OSPF
u

Table 8.2 Protocol values

ad

ü) Header Checksum: 16 bit

iln

This checksum field is used for error-checking of the header.

m

(k) Options: 32 bits

Ta

The options field gives more functionality to the IP datagram. It can carry fields
that control routing, timing, management, and alignment.
(2) IP Services
The Internet also provides higher-level services built on top of P. The
Transnission Control Protocol (TCP) providesa connection-oriented service
that ensures that data arrive in the appropriate order, and it uses
an

acknowledgment protocol to ensure that packets arrive.

<br>

Page 309 of 440

Networks and Multiprocessors

8.27
Many higher-level services,are built on top
of TCP, then the basic protocol is
often referred to as TCP/IP.

FTP HTTP SMTP Telnet SNMP

g
TCP

in
UDP

er
IP

e
in
Fig 8.26 The Internet service stack

ng
o
Fig 8.26 shows the relationships between IP and higher-level Internet services.
fE
Using IP as the foundation, TCP is used to provide File Transport Protocol.
(FTP) for batch file transfers and Hypertext Transport Protocol (HTTP) for
O
World Wide Web service.
g e

o Simple Mail Transfer Protocol (SMTP) for e-mail, and Telnet for virtual
le

terminals. A separate transport protocol, User Datagram Protocol (UDP) is

ol

used as the basis for the network management services that is provided by the
C

Simple Network Management Protocol (SNMP).

u
ad

8,4 TWO MARKS QUESTIONS AND ANSWERS

iln

I. How does priority scheduling improve multitask execution?

[APRMAY-2019/
m

In priorityscheduling, a task can be stopped or suspended in order to allowa task

Ta

of higher priority to run. In the case of two tasks of the same high priority each is
given an equal time slice.
Z. What is Rate Monotonie Scheduling? [NOVDEC-2018|
Rate-Monotonic Scheduling (RMS) was one of the first scheduling policies
developed for real-time systems and it is still very widely used. The priority is
decided according to the cycle time of the processes that are involved. The
Process with a small job duration shortest period), has assigned a highest
piority.
<br>

Page 310 of 440

8.28 Embedded Systems and 10T Design

3. Define response tie.

The response time of a process is the time at which the
process finishes.

4. What is critical instant?

at
The critical instant for a process is defined as the instant during execution

g
which the task has the larget response time.

in
er
5. Write the advantages of RMS.

e
The advantages of RMS are,

in
(i) It iseasy to implement.

ng
() If any static priority assignment algorithm can meet the deadlines then rate
fE
monotonic scheduling can also do the same. It is optimal.
(ii) It consists of a calculated copy of the time periods.
O
6. What is EDF scheduling?
g e

Earliest Deadline First (EDF) is an optimal dynamic piority scheduling

le

algorithm used in real-time systems. EDF uses priorities for scheduling which
ol

assigns priorities to the task according to the absolute deadline.

C

The task whose deadline is closest gets the highest priority. It can make the CPU
u

utilization to about 100% while still guaranteeing the deadlines of all the tasks.
ad

7. Compare RMS and EDF. (NOVDEC-2018]

iln

S.No RMS EDF

m

1 Achieves lower CPU utilization. Higher CPUutilization.

Ta

2. Easier to ensure that all deadlines Hard to ensure deadlines.

will be satisfied.
3 Static priority scheduling. Dynamic priority scheduling.

4 Not expensive to use in practice. Expensive to use in practice.

5 Shortest -periodprocess gets Process closest to its deadline has

highest priority. highest priority.
<br>

Page 31l of 440

Metworks and Multiprocessors 8.29|

&
Defne critical timing race or race condition.

A race condition is an undesirable situation that occurs when a

system
device or

attempts to perform two or more operations at the same time, but because of the
nature of the device Or system, the operations must be done in the proper

g
sequence and it need to be done correctly.

in
. What is critical sections? (or)

er
What is the need of criticalsections?

e
of code where processes access shared
The critical section refers to the segment

in
resources, such as common variables and files, and perform write operations on

ng
them.
fE
The critical section problem is used to design a protocol followed by a group of
processes, so that when one process has entered its critical section, no other
O
process is allowed to execute in its critical section.
e

10, Define Semaphore. [APRMAY-2017]

g
le

Semaphores are just normal variables that is used to coordinate the activities of
ol

are used to enforce mutual

multiple processes in a computer system. They
C

exclusion, avoid race conditions, and implement synchronization between

processes.
u
ad

(APRMAY-2017& APRMAY-2019)
I. What is Priority Inversion?
a process blocks
Priority inversion is a situation that can occur when low-priority
iln

resourçes. The most

(he execution of a higher-priority process by holding its
m

inheritance.
Common method for dealing with priority inversion is priority
Ta

12, What is priority inheritance? [APRMAY-2019]

any process
The basic idea of the priority inheritance is to promote the priority of
When it requests a resource from the operating system. The priority of
the process
process that may use the
emporarily becomes higher than that of any other
resource.
13. What
are
the ways of communication used in aprocess?
one of two ways:
In general., a procèss can send a communication in
<br>

Page 312 of 440

Embedded Systems and|IOTT Design

830|

() Blocking, and

(ii) Nonblocking. goes

process into the waiting
After sending in a blocking communication, the
a response.
Nonblocking communication allows the process
state until receives
it

sending the communication.

g
to continue execution after

in
interprocess communication.
14. List out the major styles of

e er
(or)

in
Name the two modes used in interprocess communication.

ng
There are two modes through which processes can communicate with each
other:

(i) Shared memory, and

fE
O
(i) Message passing.
e

The shared memory region shares a shared memory between the processes. On
g

the other hand, the message passing lets processes exchange information through
le

messages.
ol

15. What do you mean by mailbox?

C

The mailbox is a simple mechanism for asynchronous

communication. It has
u

fxed number of bits and can be used for small messages.

ad

Some architeou
define mailbox registers.
iln

16. What is a distributed

embedded system?
m

(or)
Ta

What is a distributed
embedded architecture?
In a distributed embedded are
system, several (PEs)
connected by a Processing Elements
network
that allows elements
may
includes DSP, CPU or
them to communicate. Processing
microcontroller. such as
ASICs is also
used Nonprogrammable unit
to implement as
PE.
17. List the
OSI layers fromlowest to highest
The OSI 1ayers level of abstraction.
fromthelowest
to highestlevel of are described as,
() Physical layer. abstraction
<br>

Page 313 of 440

Nvarks and Multiprocessors

8.31|
Data link layer.
()
layer.
(i) Network
(iv) Transport
layer.

() Session layer.

(i) Presentation layer.

g
in
(vi) Application layer.

er
J8. What is CAN bus?

e
in
A
Controller Area Network (CAN
bus) is a vehicle bus standard designed
to

ng
allow microcontrollers and
devices to communicate with each
applications without a host computer.
other's

19, What is meant by avionics?

fE
O
Aircraft electronics are known as
avionics which are the electronic systems
is used on aircraft, artificial
that
satellites, and spacecraft.
e

20.
g

Write the function of

PCbus.
le

The Inter Integrated Circuit (IC) bus is used to interconnect peripheral

ol

devices
within small-scale embedded systems. It is a
well-known bus commonly used to
C

link microcontrollers and

other modules into the systems.
u

I. Name the arbitration sclhemes used in distributed embedded systems.

ad

For Ethernet, Carrier Sense Multiple Access with Collision Detection

(CSMA/CD)
iln

is used.
For CAN bus, Carrier Sense Multiple Access with Arbitration on Message
m

Priority (CSMA/AMP).
Ta

4 Define
Internet Protocol (1P).
The
internet
Protocol
layer defines an official packet format and protocol called Internet
(IP) that provides a connectionless, best-effort delivery service of
datagrams
across the Internet.
23, What
is best-effort delivery?
Best-effort
delivery describes a a
network service in which network does not
provide
any guarantee that data is effectively delivered or
that delivery meets
anyquality
of service.
<br>

Page 314 of 440

8.32 Embedded Systems and IOT Design

8.5 REVIEW QUESTIONS

I. Discuss in detail about priority-based scheduling with neat sketches.
2. Explain in detail about Rate Monotonie Scheduling with an example.

[NOVIDEC-2016]

g
3. Elucidate on schèduling policies with suitable examples. APRMAY-2018]

in
4. -
Explain in detail about Earliest Deadline First scheduling. [APRMAY-2017|

er
5. Compare RMS. versus EDE.

e
NOVDEC-2018]

in
6. With neat sketches, explain the interprocess communication mechanism.

ng
[APRMAY-2017, NOVDEC-2017 & APRAMAY-2018
7. fE
Demonstrate about inter process communication mechanisns.

[APRMAY-2019)
O
8. Discuss about the distributed embedded system
e

[NOVIDEC-2016, APRMAY-2018 & NOVDEC-2018]

g
le

9. Explain in detail abont the OSI model layers, with neat

sketches.
ol

10. With neat diagram explain the working of CAN bus.

[APRIMAY-2017]
C

11. Explain in detail aboutCAN architecture.

u

12. With neat diagram explain the working of PC.

[APRMAY-2017]
ad

13. With aneat diagram, describe

the typical bus transactions on the PCprotocol.
iln

[NOV/DEC-2018]
m

14. Discuss in detail about Ethernet with neat sketches.

Ta

15. Draw the frame format of Ethernet and explain.

16. With neat diagram explain the working of InternetProtocol.

17. Draw and explain the IP packet structure.

<br>

Page 315 of 440

UNIT -II
Chapter 9

g
MPSOCs AND SHARED MEMORY

in
er
MULTIPROCESSORS

e
in
9.1 MPSoCs AND SHARED MEMORY MULTIPROCESSORS

ng
9.1.1 Introduction fE
& MPSoC:
O

MultiProcessor System on Chip (MPSoC)means a System-on- Chip (SoC) with

e

two or more CPU cores. The multiprocessor is a parallel processor with a single
g
le

shared memory.
ol

Shared memory processors are well suited to applications that requires a large
C

amount of data to be processed. Most of the MPSoCs are shared memory

systems.
u
ad

Process A Process A writes into

shared memory
iln

Shared
m

Process B reads from

Process B
shared memory
Ta

Kernel

Fig 9.1 Shared memory

<br>

Page 316of 440

Embedded Systems and 1OT Design

9.2
are mainly used to build integrated system.
the. complex
MPSoCs
the fastest
Multiprocessors have the highest performance and faster than
runs on
processing program means a single program that
uniprocessor. Parallel
multiple processors simultaneously

a Shared Memory:

g
in
Shared memory is a memory that shares between two or more processes. Each

er
process has its own address space; if any process wants to comnmunicate with

e
some information from its own address space to other processes, then it is only

in
possible with IPC (inter-process communication) techniques.

ng
9.1.2 Heterogeneous Shared Memory Multiprocessors
fE
Many high-performance embedded platforms are heterogeneous multiprocessors:
O
Diferent Processing Elements (PEs) can perform diferent functions. The
memory system may be heterogeneously
distributed around the machine, and
e

the interconnection network between the PEs and

g

the memory may also be

le

heterogeneous.
The PEs may be programmable processors with
ol

different instruction sets or

specialized accelerators that provide little or no
C

programmability.
Processors with different instruction sets can
perform different tasks by using
u

less energy. Accelerators provide even

faster and lower-power operation for a
ad

narrow range of functions.

iln

9.1.3 Accelerators
m

&Accelerator is a Processing Element (PE)

for embedded multiprocessors which
Ta

can provide large performance

increases for applications with computational
kernels that spend a great deal of time
ina small section ofcode.
Accelerators can also provide critical speedups
for low-latency VO functions.
Fig 9.2. illustrates a CPUaccelerator which is attached
to the CPU bus. The CPU
is often called the host and it communicates to the
accelerator through data and
control registers in the accelerator. These registers allow the CPU to monitor the
accelerator's operation and to give the accelerator commands.
<br>

Page 317 of 440

MPSOCs and Shared.I Memory Multiprocessors

9.3
CPUbus

Accelerator
Memory

Accelerator

g
CPU

in
e er
in
registers

ng
registers

Accelerator
logic
Data fE
Control
O
e

Fig 9.2 CPU accelerators in a system

g

The CPUand the accelerator may also communicate via shared memory and use
le

synchronization mechanisms to ensure that they do not destroy each other's data.
ol
C

An accelerator interacts with the CPU through the programming model interface
which does not execute instructions. Its interface is functionally equivalent to an
u

but it does not perform either an input or output.

ad

VO device,

The first task in designing an accelerator is to determine that our system actually
iln

run
needs one, We have to make sure that the function we want to accelerate will
m

more quickly on our accelerator than it will execute as software on a CPU.

Ta

Finally, we will have to design the CPU-side interface to the accelerator. The
the data to it
application software will have to talk to the accelerator, providing
and also telling it what to do next?
teld-Programmable Gate Arrays (FPGAS) provide one useful platform for

Custom
a
accelerators. An FPGAhas fabric with both programmable logic gates
implement a specific
and programmable interconnect that can be configured to
function.
<br>

Page 318 of 440

Embedded Systems and IOT Design

9.4
9.1.4 Accelerator Performance Analysis
or
The speedup factor depends on whether the system is single threaded
multithreaded, that is, whether the CPU is most of the time idle while the
accelerator runs in the single-threaded case or in the multithreaded case, the
CPU can do useful work inparallel with the accelerator.

g
in
Flow of control Flow of control Split

e er
in
A1 A1

ng
P3
Accelerator Accelerator
(P4)
fE P4 -- Join
CPU
CPU
O
Execution time
Execution time
e

Accelerator
g

A1 Accelerator
A1
le
ol

CPU P1 P2 P3 P4 CPU P1 P3
P2 P4
C

Time
Time
Single-threaded
u

Multi-threaded
Fig 9.3 Single- threaded vs. mnultithreaded
ad

control of an accelerator
4 Fig 9.3 shows that data dependencies
allow P2 and P3 to run
iln

the CPU, but P2 relies on independently on

the results of the Al process
that can be implemented
m

by the accelerator.
Ta

In the single threaded case,

the CPU blocks to wait for
the results of its computation. the accelerator to return
a
As result, it does not matter
runs next on the CPU. whether P2 or P3
In the nmultithreaded case,
the CPU continues to do
accelerator runs, so the useful work while the
CPUcan start P3 just after
starting the accelerator and
finish the task earlier.
<br>

Page 319 of 440

MPSOCsand I Shared Memory Multiprocessors

9.5
(4) Accelerator Execution Time

Memory
Inputs

g
in
Outputs
W=ab- c*d:
CPU X=e*f,

e er
in
Accelerator

ng
Fig 9.4 Components of execution time for am accelerator
fE
Fig 9.4 shows that an execution time for the accelerator depends not only on the
O
time required to execute the accelerator's function but also depends on the time
required to get the data into the accelerator and back out of it.
g e

A simple accelerator will read all its input data, perform the required
le

computation, and then write all its results. Then the total execution time is
ol

expressed as,
C

= lin
Lacoel
t t+ tout
u

where,
ad

are available, and

I
- Execution time of the accelerator assuming all data
iln

in and tout are the times required for reading and writing the
required variables.
m

respectively.
may take in one or more streams of data and
Ta

Fig 9.5, shows an accelerator that

(S) for a kernel can be
produce an output as a stream. The otal speedup
expressed as,
S =n (tcPU-acce)
= n [tcPU-(imtytlou))
where
on the CPU, and
"CPU - Execution time of the equivalent function in software
will be executed.
n - Number of tinmes the function
<br>

Page 320 of 440

9.6 Embedded Systems and 10T Design

a[-1]

b[t-1]
Inputs a [t]

g
b []

in
e er
out [i] = a Q*b [0:

in
ng
fE Accelerator
O
Out [t-1]
Outputs
e

Out [t]
g

Fig 9.5 Streaming data into and out

le

of an accelerator
(2) System
ol

Speedup
Ina single-threaded system, the evaluation of the accelerator' s speedup to the
C

total system speedup is simple that is, the system

u

execution time is reduced

by S.
ad

Fig 9.6 shows that the single thread

of control gives us a single path whose
iln

measured length can be used to determine

the new execution speed.
Fig 9.7. shows the multithread implementation
m

which has more than one

execution path. The total system execution
Ta

time depends on the longest patlh

from the beginning of execution to the end of execution.
In this case, the system execution time depends on the
relative speeds of P3 and
P2 plus A1. If P2 and Al together takes most of
the time, then P3 will not play
a role in determining the system execution time.
If P3 takes longer time, then P2 and Al will not be considered. To determine
the system execution time, we must label each node in the graph with its
execution time.
<br>

Page 32 of 440
1l

WPSOCs and Shared Memory Multiprocessors

Flow of control 9.7

P2
S

g
in
P3

e er
in
P4!

ng
fE
Fig 9.6 Evaluating systenn speedup in a single-threaded implementatioin
O
Flow of control
g e

P1
le
ol
C
u

2
ad
iln
m
Ta

Fig a multithreaded inmplementation

9.7 Evaluating System speedup in
\,15
Scheduling and Allocation
communication on the
We must which includes
sclhedule operations in time
network Processing Elements (PEs).The scheduling of
and Computations on the are linked.
operations communications between the PEs
on the PEs and the
may interfere with another
If One PE computations too late, it
finishes its
result to the PE that needs
it.
Communication as it tries to send its
on the network
<br>

Page 322 of 440

9.8 Embedded Systems and 1OT Design

This is not good for both the PE that needs the result and the other PEs whose
communication is interfered with.
We must allocate computations to the PEs and detemines what communications
are required. If a value computed on one PE that is needed PE, must
ôn another it
be transmitted over the network.

g
in
9.2 DESIGN EXAMPLE: AUDIO. PLAYER

er
9.2.1 Theory of Operation and Requirements

e
Audio players are often called MP3 players.

in
The earliest portable MP3 players
were based on compact

ng
disk mechanisms and the modern MP3
nmemory
players use either
aflash or disk drives to store music.
fE
An MP3 player performs three basic functions:
(i)) Audio storage,
O
(ii) Audio decompression, and
e

(iii) User interface.

g
le

(1)Audio Decompression
ol

The incoming bit stream has

been encoded using a Huffman
must be decoded. style code, which
C

The audio data itself are applied

along with a few other parameters. to a reconstruction filter,
u

Audio compression is a
lossy process that relies on
ad

coder eliminates certain features perceptual coding. The

encoded in fewer bits. It of the audio stream so that
the result can be
iln

tries to eliminate features

by the human audio system. that are not easily perceived
m

Masking isone perceptual

phenomenon that is exploited
Ta

One tone can be masked by perceptual coding.

by another if the tones are
frequency. Some audio sufficiently close in
features can.also be masked
time after another feature. if they occur too close in
In MP3 players, the following
three layer standard
compression: defines the audio
(i) Layer 1(MP1)
It uses a lossless compression
of subbands which is a simple
model. masking
<br>

Page 323 of 440

MPSOCs and. Shared Memory Multiprocessors

9.9
(i) Layer 2 (MP2)
It uses a more advanced
masking model.
(üi) Layer 3(MP3)
It performs additional processing to provide a
lower bit rates.
The various layers that supports several

g
different input sampling rates, output

in
bit rates, and modes such as mono, stereo, etc.

e er
Scale factor

in
ng
Mux
Filter
Quantizerlencoder
bank
fE o 0101.
O
Masking
FFT model
e

Fig 9.8 MPEG layerl encoder

g
le

path
a diagram of a layer I encoder. The main processing
o Fig 9.8 gives block
ol

the
the quantizer/encoder. The filter bank splits
includes the filter bank and
frequency domain
C

subbands that are equally spaced in the

signal into aset of 32 range of the audio.
u

cover the entire frequency

and together
ad

a narrower band, so splitting into

within
signals are more correlated
OAudio
iln

rate.
the encoder to reduce the bit
Subbands helps driven by a
separate Fast
m

factors, which is
model selects the scale could be used for masking,
The masking principle
Ta

O
The filter bank
Fourier Iransform(FFT). results.
provides better which can
but Separate FFT for the subbands,
the scale factors output of the
o model chooses multiplexer at the
The masking stream. The
audio
change along with the required data.
all the
encoder passes along
Aux
Subband
Scale data
samples
Bit factors
CRC allocation
Header format
layer-l data frame
MPEG
Fig 9.9
<br>

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9.10| Embedded Systems and IOT Design

MPEG data streams are divided into a frame which carries the basic MPEG
data, error correction codes, and additional information. Fig 9.9 shows the
format of an MPEG layer 1
data frame.
Scale
factor

g
Demux
Inverse

in
quanlize Inverse
0101..

er
filter

L Expand
bank

e
in
Step

ng
size

Fig 9.10 MPEG layer-l decoderfE

o A block diagram of MPEG layer 1 decoder is shown
in Fig 9.10. After
O
disassembling the data frame, the data are unscaled
and inverse quantized to
e

produce sample streams for the subband.

g

An inverse filter bank then reassembles the

le

subbands into the uncompressed

signal.
ol

The requirements table for the audio player is

C

given in Table 9.1.

Name
u

Audio player
ad

Purpose Play audio from files.

Flash memory socket, on/off,
iln

Inputs play/stop, menu

up/down.
m

Outputs Speaker
Ta

Display list of files in flash memory,

Functions select file to
play, play file.
Performance Sufficient to play audio files at
required rate.
Manufacturing cost Approximately $25
Power 1AAA battery
Physical size and weight Approx. 1
in x 2 in, less than 2 oz
Table 9.1: Requirements for the audio player
<br>

Page 325 of 440

MPSOCs and,Shared I Memory Multiprocessors

9.11
Specification
9,2.2
Start

displ = 0;

g
in
er
Send Files[displ].name

e
to display

in
ng
button
fE
O
down
Play
g e
le

displ=wraparound(i-1) displ=wraparond(i+1) Play Files(displ]

ol
C

Fig 9.11 State diagram for file display and selection

u
ad

& Fig 9.11 shows a state diagram for file display/selection. This specification
assumes that allfiles are in the root directory and that all files are playable audio.
iln

* Fig 9.12 shows the state diagram for audio playback. The detals of this operation
m

depend on the format of the audio file.

Ta

Ms state diagram refers to sending the samples to the audio system because
playback and reading the next data frame must be overlapped to ensure
continuous operation.
%
The details depend on the hardware platform selected mostly DMA
of playback
transfer
is used.
<br>

Page 326 of 440

9.12 Embedded Systems and 10T Design

Start

Open file

g
in
er
Read frame

e
in
ng
Parse frame
fE
O
Decode frame
g e

Send samples to audio

le

system
ol
C

F Last
frame?
u
ad
iln

End
m

Fig 9.12 State diagram for audio playback

Ta

9.2.3 System Architecture

The Cimus CS7410 is an audio controller
designed for CDIMP3 players.
The
audio controller includes two processors:
() 32-bit RISC processor is used to perform system
A

control and audio

decoding.
() A 16-bit DSP is used to perform audio effects
such as equalization.
<br>

Page 327 of 440

MPSoCs.and Shared Memory Multiprocessors

9.13

RISC processor
DSP Audio
interface

CD
CD interface
drive SRAM

g
Memory controller

in
er
ROM

e
in
ng
flash, DRAM, SRAM
Fig 9.13 Architecture of a Cirrus audio processor fE
for CDMP3 player
Fig 9.13 shows the Cirrus chip uses two processors: a
RISC and a DSP. The
O
memory controller can interfaced to
be several different types of memory: flash
e

memory can be used for data or code storage and DRAM can
be used as a buffer
g

to handle temporary disruptions of the CD data stream.

le

4 The output an audio interface unit is in audio formats that can

ol

of
be used by A/D
converters. General-purpose I/O pins can be used to decode buttons, run displays,
C

etc. Cirrus provides a reference design for a CD/MP3 player

u
ad

9.2,4 Component Design and Testing

iln

The audio decompression object can be implemented from existing code or

m

Created as a new software. It is necessary tocreate an audio compression program

to create test files.
Ta

The file
system can either implement known standard such as DOS FAT or can
a

implement a new file system. The file system and an user interface can be tested
Independently of the audio decompression system.
&
The audio
output system should be tested separately from the compression
System. Testing of audio decompression requires sample audio files.
<br>

Page 328 of 440

9.14 Embedded Systems and TOT Design

9.2,5 System Integration and Debugging

* Any file access and audio output that operate concurrently should be tested
separately by using an easily recognizable test signal. Simple test signals such as
tones will more readily show problems such as missed or delayed samples.

g
9.3 ENGINE CONTROL UNIT (ECU)

in
er
We will design a simple Engine Control Unit (ECU) which controls the operation
of a fuel-injected engine based on the several measurements taken from the

e
in
running engine.

ng
9.3.1 Theory of Operation and Requirements
fE
Injection
O
Fuel pulse width
injection
RPM
Engine
e

Throttle Spark
g

Spark
le

advance
ol
C

Intake air volume

u
ad

Intake air temperature,

exhaust oxygen,
battery voltage
iln
m

Fig 9.14 Engine block diagram

Ta

We can design a basic engine controller

for a simple fuel injected engine as
shown in Fig 9.14. The tlirottle is the
command input and the engine measures
throttle, RPM, intake air volume, and other variables.

The engine controller computes injector pulse width

and spark. This design does
not compute all the outputs required by a real
engine, we only concentrate on a
few essentials. Our requirements chart for the ECUis shown in table 9.2.
<br>

Page 329 of 440

A

MPSOCs and Shared. Memory Multiprocessors 9.15

Name ECU
Purpose Engine controller for fuel-injected engine

lnputs Throttle, RPM, intake air volume, intake manifold pressure

|Outputs Injector pulse width, spark advance angle

g
in
Functions Compute injeçtor pulse width and spark advance angle as a
function of throttle, RPM, intake air volume, intake manifold

er
pressure

e
in
Performance |Injector pulse updated at 2-ms period, spark advance angle
updated at 1-ms period

ng
Manufacturing
cost |Approximately $50
fE
O
Power Powered by engine generator

4 in x 4 in, less than 1 pound.

e

Physical size andApprox

g

weight
le

Table 9.2 Requirements for the engine controller

ol
C

9.3.2 Specification
& The engine controller must deals many processes with different rates. Table 9.3
u
ad

shows the update periods for the different signals. ANE and AT represents the
change in RPM and throttle position, respectively.
iln

Variable Update
m

Signal In/Out
name period(ms)
Ta

Throttle T Input 2
NN

NE Input 2
RPM
Intake air volume VS Input 25

Injector pulse width PW Output 2

1
Spark advance angle S Output

Intake air temperature THA Input 500

<br>

Page 330 of 440

9.16 Enbedded Systems and IOT Design

Exhaust oxygen OX Input 25

Battery voltage +B Input 4

Table 9.3: Periods for data in the engine controller

Our controller computes two output signals. injector Pulse Width (P) and

g
as,
Spark advance angle (S) using initial values of these variables

in
.. (1)

er
1
PW = 22.5 x VS x 10-k, AT
NE

e
.(2)

in
S =k,x A NE- k; VS

ng
The controller then applies corections to these initial values:
()
fE
As the intake air temperature (THA) increases during engine warm-up, then
the controller reduces the injection duration.
O
(i) As ihe throttle opens, the controller temporarily increases the injection
e

frequency.
g

(ii) The controller adjusts duration up or down based upon readings from the
le

exhaustoxygen sensor (OX).

ol

(iy) The injection duration is increased as the battery voltage (+B) drops.
C
u

9.3.3 System Architecture

ad

a Fig 9.15 shows the class diagranm for the engine controller. The two major
iln

processes are pulse-width and an advance-angle.

m

The control parameters are computed for the spark plugs and injectors. The
control parameters rely on changes in some of the input signals. We will use the
Ta

physical ensor classes to compute these values.

Each change must be updated at the variable's sampling rate. The update process
is simplified by performing it in a task that runs at the required update rate.
so
Fig 9.16 shows the state diagram for throttle sensing, which saves both the
current value and change in value of the throttle. We can use similar control flow
to compute changes to the other variables.
<br>

Page 33 of 440
1l

MPSoCs and Shared. Memory Multiprocessors

9.17

Throttle

Pulse-width Spark

g
RPM"

in
Advance
Injector*

er
angle
Air
volume*

e
in
ng
Intake-air
temp*

Exhaust
fE
Oxygen*
O
e

Battery
g

voltage*
le

Fig 9.15 Clas diagram for the engine controller

ol
C
u

Update previous
ad

values
iln

Save T
m
Ta

Compute AT

position sensing
Fig 9,16 State diagran for throttle
* Fig 9.17 pulse width, and Fig 9.17 (b)
(a) shows the state diagram for injector
shows angle. In each case, the value is
the state diagram for spark advance
followed by a correction.
Computed
intwo stages, first an initial value
<br>

Page 332 of 440

Embedded Systems and IOT Design

9.18

Compute Compute
initial PW initial S

Correct PW Correct S

g
in
er
Fig 9.17 State diagrams

e
in
The pulse-width and advance-angle processes generate the spark and injector
waveforms which must be carefully timed to the engine's current state.

ng
Each spark plug and injector must fire at exactly the right time in the engine
fE
cycle and consider the engine's current speed as well as the control parameters.
The main processor is a PowerPC processor. The enhanced Modular 10
O
Subsystem (eMIOS) provides 28 input and output channels controlled by timers.
e

Each channel cn perform a variety of functions.

g

The Output Pulse Width and Frequency Modulation Buffered (OPWFMB)

le

mode will automatically generate a waveform whose period and duty cycle can
ol

be varied by writing registers in the eMIOS. The details of the waveform timing
C

are then hndled by the output channel hardware.

u
ad

9.3.4 Component Design and Testing

The various tasks must be coded to satisfy the requirements
of RTOS processes.
iln

Variables that are maintained across task execution, such as the change-of-state
m

variables, must be allocated and saved in appropriate memory locations. The

Ta

RTOS initialization phase is used to set up the task periods.

Some of the output variables depend on changes in state. These tasks should be
tested with multiple input variable sequences to ensure that both the basic and
adjustment calculations are performed correctly.

9.3.5 System Integration and Testing

Engines generate huge amounts of electrical noise that can damaged the digital
electronics. They also operate over very wide temperature ranges: hot during
engine operation, potentially very cold before the engine is started.
<br>

Page 333 of 440

MPSOCs and Shared.Memory Multiprocessors

9.19
4 Any testing performed on an actual engine must be
conducted using an engine
controller that has been designed to withstand
the harsh environment of the
engine compartment.

9,4 VIDEO ACCELERATOR

We consider the design
of a video accelerator which is specifically a

g
motion

in
estimation accelerator. Digital video
is still a computationally intensive
task, so it

er
is well suited for acceleration.

e
A video accelerator significantly speeds up
the updating of images on a screen

in
which makes CPUfree to take care of other tasks.
Simply, it act as a video card

ng
with integrated processor and memory. It is mainly , used
fE
1) To increase the overall capabilities of video graphics.
O
(ii) To provides critical speed ups for low-latency I/O functions.
e

9.4.1 Video Compression

g
le
ol

Variable
Motion
DCT length Buffer
estimator
C

coder
u
ad
iln

DCT-1
Picture
m

store/
predictor
Ta

of MPEG-2conpression algorithm
Fig 9.18 Block diagram
Fig 9.18 shows the block diagram for MPEG-2 video compression algorithm
uses several
which is the basis for US HDTV broadcasting. This compression

Omponent algorithms together in a feedback loop.

also plays a key role in
Ihe Discrete Cosine Transform (DCT) used in JPEG
DCT of a block of pixels is
MPEG-2. In still image compression, the
the
<br>

Page 334 of 440

9.20 Embedded Systems and 10T Design

quantized for lossy compression and then subjected to lossless variable-length
coding to further reduce the number of bits required to represent the block.
* The MPEG-2 encoder also uses a feedback loop to further improve image
quality.
(1) Motion-Based Coding

g
in
MPEG uses motion to encode one frame in terms of another. Some frames are

er
sent as modified forms of other frames using a technique known as block

e
motion estimation.

in
a Block Motion Estimation:

ng
A
block matching algorithm is a way of locating the matching macroblocks in
fE
a sequence of digitalvideo frames for the purpose motion estimation.
of
During encoding, the frame is divided into macroblocks which is identified
O
from one frame in other frames using correlation.
e

The frame can then be encoded using the motion vector

that describes the
g

motion of the macroblock from one frame to

le

another without explicitly

transmitting all of the pixels.
ol
C

Search
area
u
ad

Previous frame
iln

Current frame
m
Ta

Macroblock

Best match of macroblock

onto sear ch area
Fig 9.19 Block motion estimnation
<br>

Page 335 of 440

MPSOCs and Shared Memory Multiprocessors 9.21|

concept of block motion estimation is illustrated
o The in Fig 9.19. The goal is to
perform a two-dimensional correlation to find the best match between regions
in the two frames.

.We divide the current frame into 16X16 macroblocks, For every macroblock in

g
the frame, we want to find the region in the previous frame that closely matches

in
to the macroblock.

er
We measure similarity using the following sum-of- diferences measure:

e
in
| M(iJ) - S(i –o,j -o,)

ng
1
sijsn
where
- Intensity of
fE
themacroblock at pixel i, j,
MiJ)
O
- Intensity of the search region,
S(i,j)
one dimension, and
n - Size of the macroblock in
e

search region.
g

(o, o,) Offset between the macroblock and

le

MBSIZE
ol
C
u
ad
iln

XCENTER, YCENTER
m
Ta

SEARCHSIZE

center)
(measured from
Limit of search

MBSIZEI2

0,0 parameters
search
Block motion
Fig 9.20
<br>

Page 336 of 440

Embedded Systems and 10T Design

9.22
9.4.2 Requirements
We will build the. system using an FPGA connected to the Periplheral
a
Component Interconnect (PCI) bus of a personal computer. We clearly need
high-bandwidth connection such as the PCI between the accelerator and the CPU.

g
Name Block motion estimator

in
Purpose Perform block motion estímation within a

er
PC system

e
|Inputs Macroblocks and scarch areas

in
Outputs Motion vectors

ng
Functions Compute motion vectors using full search
algorithms
Performance
fE
As fast as we can get
Manufacturing cost Hundreds of dollars
O
Power Powered byPC power
supply.
e

Physical size and weight Packaged as PCI card for PC

g
le

Table 9.4: Requirements of video accelerator

ol

9.4.3 Specification
C

Motion-vector Macroblock
u

Search-area
ad

X, y pixels[]
pixels[]
iln
m

Fig 9.21 Classes describing basic data types in the video accelerator
Ta

Fig 9.21 defines some classes that describe basic

data types in the system:
) Motion vector,
(ii) Macroblock, and

(iii) Search area.

The system behayior is very simple. So we need to define only two classes to
describe it: the accelerator itself and the PC which are shown in Fig 9.22.
<br>

Page 337 of 440

MPSoCs and
Shared Memory Multiprocessors
9.23
PC Motion-estimator

memoryt 1

Compute-mv()

g
Fig 9.22 Bastc classes for the video accelerator

in
The PC makes its memory accessible to the accelerator.
The accelerator provides

er
a behavior
compute-mv() that performs the block motion estimation algorithm.

e
in
:PC :Motion-estimator

ng
compute-mv( ) fE
O
Search memory []
area
g e
le

memory 0
Macroblock
ol
C

motion-vector
u
ad
iln

video accelerator
Fig 9.23 Sequence diagram for the
m

Fig 9.23 shows a sequence diagram that describes the operation of compute-mv().
Ta

When initiating the behavior. the accelerator reads the search area and
macroblock from the PC. Ater computing the motion vector, it returns it to the
PC.

9.4,4Architecture
The accelerator on a card connected to a PC's
will be implemented in an FPGA
PCI slot.
We have to use a external memory to the FPGA but on the accelerator
board to hold
the pixels.
<br>

Page 338 of 440

Embedded Systems and 10T Design

9.24|

PEo

PE

g
in
Network

er
control PE2 Comparator
Motion

e
vector

in
ng
Macroblock

Network

fE
PE15
O
Fig 9.24 An architecture for the motion estimation accelerator
e

An architecture for the motion estimation accelerator is shown in Fig 9.24. The
g
le

machine has two memories: one for the macroblock and the another are for the
ol

searcl memories.
C

It has 16 Processing Elements (PEs) that is ysed to perform

the difference
calculation on a pair of pixels. The comparator sums them up and selects the best
u

value to find the motion vector.

ad

This architecture can be used to implement algorithms

other than a full search by
iln

changing the address generation and control.

Depending on the number of
m

different motion estimation algorithms

that you want to execute on the machine
the networks connecting the memories to
Ta

the PEs may also be simplified.

4 Fig 9.25 shows the object diagram for the
video accelerator. The system includes
the two memories for pixels, a single-port memory
and one
the other is dua
ported.
A bus interface module is responsible
for communicating with the PCI bus
the rest of the system. The estimation engine reads
pixels from the M ano
memories, and it takes commands from
the bus interface and returns the motion
vector to the bus interface.
<br>

Page 339 of 440

Memory Miultiprocessors
MPSOCs andd Shared. 9.25
interfacel Takes commands,
Interface: PCI
returns
motion vector

M memory.
PC memory fetch:

g
memory fetch unit single-port memory

in
Estimator engine:
motion estimator

er
S memory.

e
dual-port memory

in
Fig 9.25 0bject iagramn for the video accelerator

ng
9.5 TWO MARKS QUESTIONS AND ANSWERS

1 Expand MPSoC.
fE
O
MultiProcessor System on Chip (MPSoC) means a System-on- Chip (SoC) with
cores. The multiprocessor is a parallel processor with a single
e

two or more CPU

g

shared memory.
le

2 Define shared memory.

ol

more processes. Each

isa memory that shares between two or
C

Shared memory
process has its own address space; if any process wants to communicate with
u

space to other processes, then it is only

information from its own address
ad

SOme

techniques.
pOSSible with IPC (inter-process communication)
iln

What is meant by accelerator?

m

m
which
for embedded I multiprocessors
Accelerator
is a Processing Element (PE)
Ta

provide large performance increases for

applications with computational
kernels that section of code.
great deal of time in a small
spendla
4. List
thebasic functions of an audio player.
An MP3 functions:
(or) audio pplayer performs three basic
0) Audio storage,
() Audio decompression, and
(i) User interface.
<br>

Page 340 of 440

Embedded Systems and 10T Desien

9.26
S. Name the layers used in audio compression.

In MP3 players,the following three layer standard defines the audio compression:

(i) Layer 1(MP1)

It uses a lossless compression of subbands which is a simple maskino

g
model.

in
(i) Layer 2 (MP2)

er
It uses a more advanced masking model.

e
in
(iii) Layer 3 (MP3)

ng
It performs additional processing to provide lower bit rates.

6. What is data compressor? fE [APRMAY.2018]

Data compressor is a process of reducing the amount of data needed for storage
O
or transmission of a given piece of information using encoding techniques.
e

7. Specify the MPEG layer-l data frame format for the audio player application.
g
le

[NOVIDEC-2016]
ol

CRC
Bit Scale Subband Aux
Header
C

allocalion factors samples data

u

8. Listout the major components of

audio player. (NOVDEC-201I8]
ad

The major components of audio player are,

iln

(i) RISC processor.

m

(ii) DSP.
Ta

(iil) Audio interface.

(iv) CD interface.

(v) Memory controller.

(vi) SRAM.

(vii)ROM.

(vii)lnputs/ Outputs.
<br>

Page 34lof 440

Shared Memory Multiprocessors

PSOCs and 9.27
video accelerator?
What is
(OR)

What is the
need for video accelerator?
APR/MAY-2019)
(OR)

ol.at are the. advantages of video accelerator? [APRMAY-2017&

g
in
NOVDEC-2017
hdeo accelerator is a motion estimation accelerator. Digital video is still a

er
computationally intensive task, so it is well suited for acceleration.

e
in
A
video accelerator significantly speeds up the updating
of images on a screen

ng
uhich makes CPUfree to take care of other tasks. Simply, it acts as a
video card
with integrated processor and memory. It is mainly used,

() To increase the overall capabilities of video graphics.

fE
O
(Gi) To provides critical speed ups for low:-latency l/O functions.
e

10. What is block motion estimation?

g
le

A block matching algorithm is a way of locating the matching macroblocks in a

ol

sequence of digital video frames for the purpose of motion estimation. During
C

cncoding, the frame is divided into macroblocks which is identified from one
frame in other frames using correlation.
u
ad

Determine the requirements of block motion estimator. [APRMAY-2018]

iln

Name Block motion estimator

Purpose Perform block motion estimation within a
m

PC system
Ta

Inputs
Macroblocks and search areas
Outputs
Motion vectors
Functions
Compute motion vectors using full search
algorithms
Performance
As fast as we can get
Manufacturing
cost Hundreds of dollars
Power
Powered by PC power supply
Physical size
and weight Packaged as PCI card for PC
<br>

Page 342 of 440

Embedded Systems and 1oT Design

9.28|

9.6 REVIEW QUESTIONS

om
1. Explain how the concepts of Multiprocessor System-on-Chip (MPSoC
slhared memory multiprocessors are used in embedded application.
NOVDEC-2017 &APRMAY-20197
Write a note on accelerator.

g
2.

in
3. of an audio player.
With neat diagrams, explain the design

er
4. Iustrate the working of Engine Control Unit with a iagram.

e
[APRMAY-2017, NOVDEC-201, NOVDEC-2018 & APRMAY-20197

in
5. Write in detail about the embedded concepts in the design of video accelerator.

ng
NOVDEC-2016, NOVDEC-2018 & APRMAY-20191
fE
O
g e
le
ol
C
u
ad
iln
m
Ta

A
<br>

Page 343 of 440

UNIT- IV

Chapter 10
INTERNET OF THINGS (|oTs)

g
in
er
10.1 INTRODUCTION

e
in
4 The Internet of Things (1oT) describes the netvork of pltysical objects which are

ng
considered as "things" that are embedded wih sensors, sofhware, and other
technologies for the purpose of conecting and exchanging data with other
fE
devices and systems over the Internet.
O
Today, we are using more than 10 billion connected IoT devices, experts
predicting that this number will grow up to 22 billion by 2025. Oracle has a
g e

network of device partners.

le

10.1.1 Applications
ol
C

Homo
Appliancos
u

Smart phonos
ad

and
Computers
Woarablo
iln

Eloctronlcs
m

Printers
Ta

loT Industrial
Dovicos Machines

Cars

Hoalth
care

Sonsors

Camera

of loT
Fig 10.1Applications
<br>

Page 344 of 440

Embedded Systems and loT Design

10.2 growing so faster
applications and
a wide variety of
IoT technology has application areas of IoTs, it has bea
different
depending upon the
designed/developed. homes
span a wide range of domains which includes
The applications of IoT and.
logistics, industry, agriculture

g
energy systems, retail,
cities, environment,

in
health as outlined in Fig 10.1.

er
(i) Homes

e
as smart lighting that adapt the
IoT for homes has several applications such

in
lighting to suit the ambient conditions, smartappliances that can be remótely

ng
detectors,
monitored and controlled, intrusion detection systems, snart smoke
etc.
fE
Cities
O
(iü)

For cities, IoT has applications such as smart parking systems that provide the
e

status updates on available slots, smart lighting that helps in saving energy,
g

smart roads that provide information on driving conditions and structural

le

health monitoring systems.

ol
C

(ii) Environment
For environment, IoT has applications such as weather
u

monitoring, air and

noise pollution, forest fire detection and river flood detection systems.
ad

(iv) Energy Systems

iln

For energy systems, loT has applications

such as smart grids, grid integration o
m

renewable energy sources and prognostic health management

systems.
Ta

(v) Retail Systems

For retail
domain, IoT has applications
such as
payments and smart vending inventory management, Smart
machines.
(vi) Agricuture
Foragriculturc domain, IoT has
applications such as
that help in saving water which smart irrigation systens
enhances productivity
systems. and green house control
<br>

Page 345 of 440

Mernetef
2hings
10.3|
Industrial
i) Industrial applications of IoT include
machine diagnosis
and prognosis systems
that helps in predicting faults and determining the cause of
faults and indoor air
quality systems.

wilHealth and Life

Style

g
Eorhealth and lifestyle, loT has applications such as

in
health and fitness
monitoring systens and wearable electronics.

e er
10.1.2 Definition and Characteristics of IoT

in
4 The Internet of Things (oT) has been defined as,

ng
A Definition: fE
A dymamic global network infrastructure with selfconfiguring capabilities based
O
on standard and interoperable communication protocols where physical and
virtual "tlhings" have identities, physical attributes, and virtual personalities and
e

intelligent interfaces, and are seamlessly integrated into the information

g

usSe
le

network, often communicate data associated with users and their emvironments.
ol

* The characteristics of loT are,

C

0 Dynamic and Self-Adapting

u

to dynamicaly adapt with

loT devices and systems may have the capability
ad

on their operating conditions,

the changing contexts and take actions based
iln

user's context, or sensed environment.

a
Surveillance cameras can adapt their modes based on whether it is
Example:
m

day or night.
Ta

Self- Configuring
a large number of
self-configuring capability that allow
loT devices may have
certain functionality.
devices to work together to provide
IoT
to configre themselves with the
Ihese devices haye the ability
fetch the latest software upgrades
infrastructure, setup the networking, and
With minimal manual or user intervention.
<br>

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Embedded Systems and loTDesign

10.4|

Protocols
(i) Interoperable Communication communication protocols and
IoT devices may support a number of interoperable
can communicate with other devices.

(iv) Unique ldentity:

a
Each IoT devices has a unique identity and unique identifier
such as an Ip

g
in
address or a URI.

er
(v) Integrated into Information Network:

e
loT devices are usually integrated into the information network that allows
them

in
to communicate and exchange data with other devices and systems.

ng
10.2 PHYSICAL DESIGN OF IOT fE
10.2.1 Things in IoT
O
The "Things" in loT usually refers to IoT devices which have unique identities
e

and can perform remote sensing, actuating and monitoring capabilities.

g
le

IoT devices can exchange data with other connected devices and applications
either directly or indirectly, or collect data from other devices and process the
ol

data locally or send the data to a centralized servers.

C
u

Connectivity Processor AudioVideo WO Interfaces

Interfaces (for sensors,
ad

USB Host HDMI

actuators, etc.)
CPU
iln

3.5mm audio
RJ45/Ethernet UART
m

RCA video
Ta

SPI
Memory Interfaces Graphics Storage Interfaces
12C
NANDINOR GPU SD

MMC CAN
DDR1/DDR2/DDR3
SDIO

Fig 10.2 Generic block diagram of an IoT device

<br>

Page 347 of 440

ere
a
Fig 10.2 shows block diagram
|10.5
of atypical
severalI interfaces for connections IoT device
to other devices: which may
consists
VO interfaces for sensors, of
()
Interfaces for Internet connectivity,
()
(i). Memory andIstorageinterfaces, and
(i) Audio. Video interfaces.

g
in
An IoT device
can collect
various types of

er
data from
sensors, such as temperature, the on-board or
humidity, light intensity attached

e
den he communicated etc. The sensed data can
either to other devices or

in
cloud-based servers/storage.
1 IoT devices are many

ng
in types such as wearable sensors, smart
light automobiles and industrial machines. watches, LED
fE
10.2.2 IoT Protocols
O
() Link Layer
g e

o Data link layer protocols determine that how the data is

plysically sent over
le

the network's physical layer or medium such as copper wire, coaxial cable or
ol

a radio wave.
C

over
Using link layer protocols, hosts on the sanme lnk exchange data packets
u

to the context
the link layer. Some of the link layer protocols which is relevant
ad

of IoT are as follows:

iln

0) 802.3 Ethernet:
m

standards for the link layer.

Ethernet
802.3 is a collection of wired
Ta

EE standard for 10BASES Ethernet that

uses coaxial
IEEE 802.3 is the
cable as a shared medium.
10BASE-T Ethernet over copper
the standard for
IEEE 802.3.i is
twisted-pair connections. over fiber optic
for
10BASE-F Ethernet
IEEE 802.3.j is the standard
connections. over fiber.
Gbit's Ethernet
standard for 10 ven
IEEE 802..3ae is the data rate from
10Mb/s to 40 Gb/s and
All provide
the above standards
higher.
<br>

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Embedded Systems and loT Design

10.6|

(ü) IEEE 802.11: Wi-Fi

Network (WI AM
IEEE 802.11 is a collection of Wireless Local Area
communication standards.
802.11 a operats in the 5 GH band.
802.11 b and 802.11 g operates in the 2.4 GHz band.

g
in
802.11n operates in the 2.4/5 GH, bands.

er
802.11ad operates in the 60 GH band.

e
These standards provide data rates fromn I Mb/s to 6.75 Gb/s.

in
(iüi) IEEE 802.16: WiMax

ng
IEEE 802. 16 is a collection of Wireless broadband communication standards
fE
that provide the data rates from 1.5 Mb/s to 1Gb/s.
a
The recent update (802.16m) provides data rates of 100 Mbit/s for mobile
O
a
station and I Gbit/s for fixedstations.
e

(iv) IEEE 802.15.4: LR-WPAN

g

IEEE 802.15.4 is a collection of standards for Low-Rate Wireless Personal

le

Area Netvorks (LR-WPAN) which provides the data rates from 4OKb/s to 250
ol

Kb/s. These standards form the basis of specifications for higher level
C

communication protocols such as ZigBee.

u

These standards provide low-cost and low-speed communication for the

ad

power constrained devices.

iln

(v) 26/3G/4G: Mobile Communication

The second generation (2G) includes GSM and CDMA, third generation (30)
m

includes UMTS and CDMA 2000 and the fourth generation (4G) incudes
Ta

LTE.
IoT devices based on these standards can communicate over cellular networks
with the data rates of 9.6 Kbs for 2G upto 100 Mb/s for 4G.

(2) Network Layer (or) Internet Layer

from
The network layerresponsible for sending of IP datagrans (packets)
is
host
the source network to the destination network. This layer performs the
addressing and packet routing.
<br>

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tlhings
ernetef
10.7
The datagrams contains a source
and destination address
routethem fromthe source to the
that are used to
destination across
the multiple networks.
Internet Protocol version 4 (IPv4)
an internet
IPy4 is protocol that is used to
identify the devices on a network
using a hierarchical I addressing scheme.
bit

g
It uses 32- address scheme that allows
total of 2 or 4,294,967,296

in
addresses. If more and more devices got
connected to the Internet then, we

er
can use IPv6.
Internet Protocol version

e
6 (|Pv6)
(ü)

in
It is the newest versions of internet protocol
and successor to IPv4. IPv6 uses

ng
128-bit address schemes that allows total
of22 or 3.4 x 10
addresses.
Ii) 1PV6 oVer Low Power Wireless Personl Area Networks (6 LoWPAN)
fE
This standard supports low power devices which have limited processing
O
capability. It operates in the 2.4 GHz frequency range and provides the data.
transfer rates of 250 Kb/s.
e

6LoWPAN works with the 802.154 link layer protocol and defines
g

compression mechanisms for IPvó datagrams over TEEE 802.15.4 based

le

networks.
ol

(3) Transport Layer

C

o The transport layer protocol provides end-to-end message transfer capability

u

can
independent the underlying network. The message transfer capability
of
ad

as TCP or without
be set up on connections, either using handshake such
iln

handshakes/ acknowledgements such as UDP.

0 The functions of the transport layer are,
m

() Error control,
Ta

() Segmentation,
(ii) Flow control, and
(iv) Congestion control.
)
Transmission Control Protocol(TCP):

most widely used transport layer protocol that is used by the web
1P is the programs (SMTP application layer
browsers along with HTTP, email

protocol) and file transfer (FTP).

<br>

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Embedded Systems and loT Design

10.8
When IP protocol deals
oriented and stateful protocol.
TCP is a connection
transmissions of packets in an
packets, TCP ensures reliable
with sending the
provide error detection capability so that the duplicate
order. TCP also
retransmitted.
can be discarded and lost packets are
packets
ensures that ráte at which the sender sende

g
capability of TCP
The flow control

in
not too high for the receiver to process. The congestion control
the data is

er
congestion.
capability of TCP helps in avoiding network

e
User Datagram Protocol (UDP)

in
(i)
time-sensitive applications

ng
UDP is a connectionless protocol, it is useful for
that have very small data units to exchange and do
not want the overhead of
connection setup.
fE
O
UDP does not provide guaranteed delivery, ordering of messages and

duplicate elimination. UDPis described in RFC 768.

g e

Application Layer
le

WebSockets
ol

HTTP CoAP
C

MQTT XMPP DDS AMQP

u
ad

Transport Layer

TCP UDP
iln
m

Network Layer
Ta

IPy4 IPv6 6LoWPAN

Link Layer

802.3- Ethernet 802.16- WiMax 2G/3G/LTE

802.11 - WiFi Cellular
802.15.4 - LR-WPAN

Fig 10.3 IoTprotocols

<br>

Page 351l of 440

things
mernet
f |10.9
Application Layer
9
Aplication layer protocol defines how the
applications interface with the
lowerr layer protocols to sendd the data over
the network.
The application data are typically
in files which is encoded
by the application
and

g
layer protocol Iencapsulated in the transport layer
protocol which provides

in
connection or transaction oriented communication over
the network.

er
Application layer protocols enable process-to-process
connection using ports.

e
The ports numbers are used for application addressing.

in
ng
Example: Port 80for HTTP and Port 22 for SSH.

() Hypertext Transfer Protocol (HTTP) fE

HTTP is an application layer protocol that forms the foundation of World Wide
O
Web (WWW).This protocol follows a request-response model where a client
e

sends request to the server using the HTTP commands.

g

An HTTP client can be a browser or an application running on the client.

le

Example: An application running on an loT device.

ol

to identify HTTP
HTTP protocol uses Universal Resource Identifiers (URIs)
C

resources. HTTP is described in RFC 2616.

u

() Constrained Application Protocol (COAP)

ad

(M2M)
COAP is an application layer protocol for Machine-to-Machine
uses a request-response model
applications. It is a web transfer protocol and
iln

and runs on top of UDP.

m

uses a client-server arclitecture where clients communicate with

COAP
Ta

Servers using connectionless datagrams.

(in) WebSocket:
communication over single socket
duplex
Websocket protocol allows full server.
between client and
connections for sending messages
messages to be sent back and
allows streams of
Websocket is based on TCP and connection open. The
server while keeping the TCP
forth between the client and is
application and an loT device. WebSocket
client Can be a browser, a mobile
described in RFC 6455.
<br>

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Embedded Systems and loT Design

10.10
(iv) Message Queue Telemetry Transport (MQTT)
on the publisl -subscribe
MQTT is a ligh-weight messaging protocol based
- (such as an IoT
model. It uses a client server architecture where the client
publishes
device) connect to the server (also called the MQTT Broker) and
messages to topics on the server.

g
to topics. MOTT
The broker forwards the messages to the clients subscribed

in
specifications are available on JBM developer works.

er
Extensible Messaging and Presence Protocol (XMPP)

e
(v)

in
XMPP is a protocol for real-time communication and streaming XML data
between network entities. XMPP supports wide range of applications

ng
including messaging, presence, data syndication, gaming, multi-party chat and
voice /voice calls.
fE
XMPP is a decentralized protocol and uses client-server architecture. It
O
supports both client-to-server and server-to-server communication paths.
e

XMPP allows real-time communication between loT devices.

g
le

(vi) Data Distribution Service (DDS)

DDS is a data- centric middleware standard for device-to-device (or) machine
ol

to- machine communication.

C

DDS uses a publish-subscribe model where publishers (e.g devices that

u

generate data) create topics to which subscribers (e.g., devices that want to
ad

consume data) can subscribe.

iln

Publisher is an object responsible for data distribution and the subscriber is

responsible for receiving published data. DDS provides Quality of Service
m

(QoS) control and configurable reliability.

Ta

(vii) Advanced Message Queuing Protocol (AMQP)

AMQP is an open application layer protocol for business messaging. AMQ

supports both point-to-point and publisher/subscriber models, routing
nd
queuing.
AMQP brokers receive the messages from publishers
ánd route them o

connections to consumer. Publishers publish the messages to

exchange w

then distribute message copies to queues.

<br>

Page 353 of 440

hings
ernet of
10.11|
Messages are either delivered
by the broker
subscribed to the queues or to the Consumers which
the consumers can pull have
the messages
fromthe queues:
LOGICAL DESIGN OF IOT
10.3L
Logical design of an loT
system refers to
# an abstract
entities and processes without
representation of
going into the the

g
low-level-specifications
inyplementation. of the

in
er
10.3,1 IoT Functional Blocks

e
in
Application

ng
Services fE
Managemenl
Security
O
Communication
g e
le

Device
ol

Fig 10.4 Functional blocks of IoT

C

* An loT system comprises of a number of functional blocks that provide the system
u
ad

capabilities for identification, sensing, actuation, communictioí and management as

shown in Fig 10.4. These functional blocks are described as follows:
iln

) Device:
m

An loT system comprises of the devices that provide sensing, actùation, monitoring
Ta

and control functions.

li) Communication:
This
communication block handles the communication for the loTsystem.
(ii) Services:

An loT of loT services such as services for device

system uses various types
monitoring, publishing services and services for device
deyice control services, data
discovery.
<br>

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Enbedded Systems and loT Design

10.12|

(iv) Management:
functions to govern the loT system.
These functional blocks provide various
(v) Security:
secures the loT system and by providing functions such
Security functional block

g
and data
authorization, message and content integrity,

in
as authentication,

er
security.

e
(vi) Application:
users can use to control and monitor

in
IoT applications provide an interface that the
system. Applications also allow users to view the

ng
the various aspects of the IoT
system status and also to view or analyze the processed data.
fE
10.3.2 IoT Communication Models
O
(i) Request- Response:
e

sends
Request-response is a communications model in which the client
g

request to the server and the server responds to the requests.

le

When the server receives a request, it decides how to respond, fetches the
ol

data, retrieves resource representations, prepares the response, and then sends
C

the response to the client.

u

It is a stateless communication model and each request-response pair is

ad

independent of others. Fig 10.5 shows the client-server interactions in the

request-respönse model.
iln
m

Client Server
Receives requests
Ta

Request from client,

Sends processes
requests to
server Response requests, looks Resources
up/fetches
resources,
prepares
response and
sends response
to client

Fig 10.5 Request-response communication model

<br>

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7htngs
lernetef
|10.13|
publlsh-Subscribe:
communication model that
It is a involves publishers,
brokers and consumers.
Publishers arc the source of data and send the data
to the topics which is
managcd by the broker. Publishers are not aware
of
the consumers.
Consumcrs subscribe to the topics that are managed by the broker. Once

g
Lenker rcccives the data for a topic from
the

in
the publisher, it sends the data to all
the subscribed consumers,

e er
Publishor Broker

in
Consumer-1
Message published

ng
Topic-1
to Topic-1
Sends Subscribers:
messages to Consumer-1,
topics
fE
Consumer-2 Consumer-2
Message published
O
Topic-2
to Topic-2
Subscribers:
Consumer-3
e

Consumer-3
g
le

communication model
ol

Fig 10.6 Publish-Subscribe

C

(fi) Push-Pull:
which the data producers pushes the
u

acommunication model in queues.

Push- pull is consumers canpull the datafrom the
ad

queues and the between the producers

and
ata in to the decoupling the
messaging a
when there is
iln

Queues help in helps in situations

also acts as a buffer which pushes the data and
the
COnsumers. It producers
m

between the rate at which the

nismatch
consumers pulls the data.
Ta

rate at which the

Publisher
Queues Consumer-1

Messages pulled
Sends queues
from
messages to Messages pushed Consumer-2
queue to queues

model
communication
Duch-Dull
-ng
<br>

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Embedded Systems and loT Design

10.14
(iv) Exclusive Pair ueor
duplex communication model that
bi-directional, fully
Exclusive pair is a server.
connection between the client and the
apersistent request to
setup it remains open until the client sends a
Once the condition is messages to each other after

g
server can send
close the connection. Client and

in
connection setup.

er
communication model and the server is aware of all
Exclusive pair is a stateful

e
10.8 shows the client-server
interactions in the

in
the open connections. Fig.

ng
exclusive pair model.

fE
Request to setup Connection
O
Response accepting the request
g e
le

Message from Client to Server

Client Server
ol
C

Message from Server to Client

u

Connection close request

ad
iln

Connection close response

m
Ta

Fig 10.8 Exclusive paircommnunication model

10.3.3 IoT Communication APIS

(1) REST-Based Communication APls:
o Representational State Transfer (REST) is a set of architectural principles
which yOu can design web
services and web APls that focus on a system
resources and how resources states are
addressed and then transferred.
<br>

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Mernet of
Ihings
|10.15
REST follows the request- response
API
o communication model.
architectural constraints apply to The REST
the components, connectors,
within a distributed hypermedia and data clements,
system.

HTTP Client HTTP Packet

HTTP Server
HTTP Command

g
REST GET PUT

in
Aware Authorization
POST DELETE
HTTP Client

er
REST-full Web
REST Payload Service

e
JSON

in
XML

ng
fE Resourcos
O
URI URI

Representations Representations
g e

Resource Resource
le
ol

Fig 10.9 Communication with REST APis

C

o The REST architectural constraints are as follows:

u
ad

0) Client-Server:
concerns.
principle behind the client-server constraint is the separation of
iln

The

For example, clients should not be concerned with the storage of data which
is
m

a concern
of the server.
Ta

the user interface which is

Dmiarly, the server should not be concemed about
Concern of the client, So, this separation allows client and server to be

hdependently developcd and updated.

) Stateless:
Each must contain all the information necessary
rcquest from client to server
any stored context on
to understand and cannot take advantage of
the requcst,
the server.
<br>

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Embedded Systems and loT Desiep

|10.16|

(ii) Cache-able:
a response to a request he
Catch constraint requires that the data within
or non-cacheable.
implicitly or cxplicitly labeled as cache-able
reuse thos
Ifa response is cache-able, then a client cache is given the right to

g
response data for later.

in
Caching can be partially or completely eliminate
some interactions and the

er
improve efficiency and scalability.

e
in
(iv) Layered System:

ng
The layered system constraint just reflects the constraints the behavior of the
components such that cach component cannot see beyond the immediate layer
fE
with which they are interacting.
O
The system scalability can be improved by allowing intermediaries to respond
e

the requcsts instead of the end server.

g
le

(v) Uniform Interface:

ol

Uniform interface constraints require that the method of communication

C

between a client and a server must be uniform. Resources are identified in the
requests and are themselves separate from the representations
u

of the resources
ad

that are returned to the client.

When a client holds a representation of a resource it has all
iln

the information
required to update or delete the resource. Each message includes enough
m

information to.describe how to process message.

the
Ta

(vi) Code on Demand:

Servers can provide executable code or scripts

for clients to execute in hen
context.
Fig 10.10 shows the interactions REST.
A
in the request-response model used by
RESTful web service is a REST
"web API" implemented using HTTP and
principles.
<br>

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hings
hernet of
|10.17|
REST
Client
Server

Request (GET, PUT, UPDATE or

DELETE)
with payload (JSON.or XML)

g
in
Response (JSON or XML)

er
Request (GET, PUT, UPDATE or DELETE)

e
with payload (JSON or XML).

in
ng
Response (JSON or XML)
fE
O
Fig 10.10 Request-response model used byy REST
e

(2) Web
Socket-Based Communication APls
g

WebSocket Protocol
le

Client
Server
ol
C

Request to setup WebSocket Connection

u

lInitial Handshake
ad

Response accepting the request | (over HTTP)

iln

Data frame
m

Data frame
Bidirectional Communication
Ta

(over persistent
Data frame WebSocket connection)

Data frame

Connection close request

Closing Connection
Connection close response

WVebSocket APIs
Pig 10.11 Exclusive pair model used by
<br>

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Embedded Systems and loT Desien

10.18

WebSocket APls allow bi-directional, full duplex communication between the

client and a server as shown in Fig 10.11.
Websocket communication begins with a connection setup request send by the
client to the server. This request is called as a WebSocket handshake which is

g
sent over HTTP and the server interprets it as an upgrade request.

in
If the server supports WebSocket protocol, then the server responds to the

er
WebSocket handshake response. After the connection.is setup, the client and

e
the server can send data/messages to each other in full-duplex mode.

in
ng
WebSocket is suitable for loT applications that have low latency or high
througlput requirements. fE
10.4 IoT ENABLING TECHNOLOGIES
O

10.4.1 Wireless Sensor Networks (WSNs)

g e

WSN comprises of distributed devices with the sensor which are used to monitor
le

the environmental and physical conditions. A WSN consists

ofa number of
end
ol

nodes and routers and a coordinator.

C

End nodes have several sensors attached to them.

End node can also act as
u

routers which are responsible for routing the data packets from
end-nodes to the
ad

coordinator.
iln

The coordinator node collects the data from all the

nodes. Coordinator also acts
as a gateway that connects the WSN to
the Internet. Some of the WSNs used in
m

IoT systems are described as follows:

Ta

Weather nonitoring systens use WSNs in

which the nodes coleus
temperature, humidity and other data,
which is aggregated and analyzed.
Indoor air quality monitoring systems use WSNs to
-indoor air quality and concentration of
'collect data n
ue
various gases.
Soil moisture monitoring systeins use moisture at
WSNs to monitor soil
various locations.
Surveillance systens use WSNs for collecting the
surveillance data.
Smart grds use WSNs for monitoring the grid at various points.
<br>

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Ihings
emet of
10.19
WSNs are enabled by wireless communication
protocols such as
Wsecifications are based on 1EEE IEEE 802.154.
802.15.4 which one
is of the most
popular wireless technologies used by WSNs.

ZigBee can operates

at
2.4
GHfrequencyand offers
data rates up to 250 Kb/s
and
ranges from 10m to 100
depending on m
the output power and

g
environmental conditions.

in
The self-organizing capability

er
of WSN makes network that can reconfigure itself
uhen there is a failure
of some nodes or an addition of new nodes to the network.

e
in
10.4.2 Cloud Computing

ng
fE
O
Cloud Computing
g e
le
ol

Servers Storage
C

Virtual Software Application.

Desktop Platform Data
u
ad

Internet
iln

Router Switch
m

End User
Ta

Mobile Desktop Desktop Desktop

Laptop Printer
architecture
Fig 10.12 Cloud computing
ADefinition:
Cloud as data storage,
COmputing refers to the use hosted services, such
of

The data is stored

Servers,
databases, networking, and softhware over the Internet.
onphysical a service provider. Computer
servers, which are maintained by cloud
<br>

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Embedded Systems and IoT Desion

10.20
power, are available
system resources, especially data storage and computing
user in cloud computing.
on-demand, without the direct management by the
Instead of storing files on a storage device or hard drive,
a user can save them on
as
cloud, making it possible to access the files from anywhere, as long they heve
access to the web. The services hosted on cloud can be broadly divided as:

g
in
(i) Infrastructure-as-a-Service (laaS):

er
IaaS is a form ofcloud computing that provides virtualized computing

e
resources over the Internet. In the laaS model, the cloud provider manages IT

in
infrastructures such as storage, server and networking resources, and delivers

ng
them to subscriber organizations via virtual machines accessible through the
Internet. fE
laaS can have many benefits for organzations, such as potentially making
workloads faster, easier, more flexible and also more cost.
O
g e
le
ol

Multi-cloud Infrastructure Data Center (Servers)

C

Service Provider
u
ad
iln
m

Application Clients (End Users) & Applications

Ta

Fig 10.13 IaaS

(ii) Platform-as -a Service (PaaS)
PaaS provides a runtime environment.
It allows programmers to casily elce
test, run, and deploy web applications.
You can purchase these applications
from a cloud service provider on a pay-as-per
use basis and access them using
the Internet connection.
In PaaS, the back end scalability is so
managed by the cloud service provider,
end- users do not need to worry about
managing the infrastructure.
<br>

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things
aernel of 10.21|
Software-as-a--Service(SaaS)

SaaS is a software licensing and delivery model

basis and
in which software is
licensed
a -subscription is centrally hosted.
on SaaS is also known as
on-demand.software, web-based's
soflware, or web-hosted software.
It is a
software distribution model
in which services are hosted by a cloud

g
service provider. These services are available
to end-users over the Internet so,

in
Ae end-users.do not need to install any software on
their devices to access

er
these services.

e
in
10.4,3 Big Data Analytics

ng
. Big data is defined as a collection of data set whose volume is so large that it is
fE
diffcult to store, manage, process and analyze the data using traditional
database and data processing tools.
O

4 The following steps are involved in big data analytics:

g e

() Data cleaning,
le

() Data munging (or) wrangling,

ol

() Data processing and visualization.

C

IoT systems are described as follows:

Some examples of big data generated by
u

as monitoring stations.
Sensor data generated by IoT system such weather
ad

)
sensors embedded in industrial and
Machine sensor data collected from
()
iln

monitoring their files and protecting failures.

energy system for
as wearable fitness
m

generated by loT devices such

(ii) Health and fitness data
Ta

bands.
tracking of vehicles.
(iv) Data for location and
generated by IoT system
monitoring systems.
(v) Data generated by retail inventory
1) Characteristics
Theunderlying characteristics of big dataincludes,
) Volume:
considered as big data. The
There volume of data to be
is fixed threshold for
no
difficult to store,
manage and
scale data that is
lerm big data
is used for massive data
processing
architecture.
Process using traditional data bases and
<br>

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Embedded Systems and loT Design

10.22|

(ii) Velocity:
Velocity of data refers to how fast the data is generated and how frequently it
varies. Modern IT, industrial and other systems are generating data at
increasingly higher speeds.

g
(ii) Variety:

in
Variety refers to the forns of the data. Big data comes in various forms such as

er
structured or unstructued data including text data, audio, video and sensor data.

e
10.4.4 Communication Protocols

in
Communications protocols form the backbone of loT system which enables

ng
network connectivity and coupling into the applications.
fE
Communications protocols allow devices to exchange data over the network.
These protocols define the data exchange formats, data encoding, addressing
O
schemes for devices and routing of packets from source to destination.
e

This protocol also support sequence control that helps in ordering the packets to
g

determine the lost packets, flow control that helps in controlling the sender data
le

rate with receiver data rate tp avoid the network overwhelmed and retransmission
ol

of lost packets.
C

10,4.5 Embedded System

u
ad

An Embedded system is a computer system that has computer hardware and

software embedded to perform the specific task. Embedded systems run
iln

embedded operating systems such as Real-Time Operating Systemns (RTOS).

m

Embedded systems ranges from low-cost miniaturized devices such as digital

Ta

watches, digital cameras, vending machines etc. These devices form an integral
part of IoT systems.

10.5 DOMAIN SPECIFIC IoTS

10.5.1 Introduction
TheInternet of Things (IoTs) applications span including
wide range of domains
homes, cities, environment, energy systems, retail, logistics, industry, agriculture and
health.
<br>

Page 365 of 440

fThings
10.23

Lighting
Control Smartphone
Controlled alerts
appliances
Energy
management

g
in
Controlled
iigations

e er
in
ng
Temperature
Control Alarm
Motion detection
|Keyless entry fE control
O

Fig 10.14 An IoT based smart home automation system

g e

10.5.2 Home Automation

le
ol

1) Smart Lighting
energy by adapting the lighting to the
C

o Smart lighting for homes helps in saving

or dimming the lights when needed.
ambient conditions and switching on/off
u
ad

users to
uses loT-enabled sensors, bulbs, or adapters to allow
O Smart lighting
iln

manage their home or office lighting.

controlled through an external device like a

can
m

Omart lighting solutions

be
or
assistant thát can be set to operate on a schedule,
Snartphone -or smart
Ta

Iriggered by sound or motion.

Key Lighting:
Benefits of loT-Enabled Smart
LED bulbs.
Save money byswitching more energy-efficient
to control or
are off when they
aren''t needed
Set schedules lights
to ensure that measure when you re away from
schedules remotely
as a security
,oMng
home or out
oftown. rooms or individual bulbs.
Adjust the color lights
of in diferent
or dimness
<br>

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Embedded Systems and loT Desigy

10.24|

(2) Smart Appliances

Modern homes have a number of appliances such as TVs, refrigerators, music
systems, washer/dryer etc. Managing and controlling these appliances can be a
difficult one because each appliance either having its own controls or remote
controls.

g
in
Smart applianices make the management easier and also provide status

er
information to the user remotely.

e
a What are Smart Appliances?

in
Any appliance can become smart with wireless connectivity and sensors that

ng
allow remote control or autonomous operation through user
input, scheduling,
or Artificial Intelligence and Machine fE
Learning (A/ML).
Sensors combined with wireless connectivity can
provide the end-user with
O
information about the appliance's usage,
temperature, service life,
e

maintenance schedules, or operation anomalies.

g

Ø Advantages
le

(i) Smart appliances enable users

ol

to connect, control, and monitor their

appliances allowing them to save
C

time, energy, and money.

(ii) Additionally, they can remotely
monitor appliances to ensure
u

turned off for safety, even after that they are

ad

leaving home.
(3) Intrusion Detection
iln

Home Intrusion detection

systems use security cameras
m

PIR sensors and door sensor and sensors such

to detect intrusions i
and raise alerts which can be
Ta

in the form of SMS

and an email sent to
the user.
Advanced systems can even
send detailed alerts
short video clip sent as an such as an image grab ora
email attachment.
(4) Smoke/Gas
Detectors
Smoke detectors are
installed in homes
and buildings
typically an early sign
of fire. Smoke
to detect smoke that is
ionization or air detectors use an optical detection,
sampling techniques to
detect smoke.
<br>

Page 367 of 440

Things
ernet of
|10.25
by
Alerts raised Smoke detectors can
be in the form of
system. Gas detectors can detect signals to fire alarm
the presence of harmful gases
monoxide (CO) and Liquid such as carbon
i Petroleum Gas
(LPG).
Asmart smoke / gas detector can
o raise alerts in human voice describing
dhe problem where
is, send an SMS or email to user
the or the local fire safety

g
department and provide visual feedback on status.
its

in
er
10.5.3 Snmart Cities

e
Smart Parking
)

in
o

ng
An loT-based smart parking system provides
real-time data on parking space
availability and payments which' is a helpful tool for -businesses
fE and
Consumers.
O
o Smart parking is also known as a connected parking system which is a
centalized management system that allows drivers to use a smartphone app to
g e

search for and reserve a parking spot.

le

M Features:
ol
C

Design and implementation of a prototype smart parking system based on

Wireless sensor network technology have the following features:
u
ad

) Remote parking monitoring,

iln

() Automated guidance, and

(m) Parking reservation mechanism.
m

2) Smart Lighting
Ta

and buildings can help in saving

0 Smart
lighting systems for roads, parks
can communicate with other lights
energy. Smart lights equipped with sensors
ambient conditions to adapt the
and exchange information on the sensed
lighting.
B) Smart
Roads
can provide information on driving
0 Smart roads equipped with sensors
case off poor driving conditions,
alerts in
conditions, travel time estimates and
<br>

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Embedded Systems and IoT Design

|10.26|
can help us
congestions and accidents. Such information for safe drive
traffic
and in reducing traffic jams.
to clond
Information sensed from the roads can be communicated via Internet
Suck
based applications and social media, the drivers who subscribe
applications can get the information.

g
in
(4) Structural Health Monitoring

er
Structural health monitoring systems uses a network of sensors to monitor the

e
vibrations levels in the structures such as bridges and buildings. The data

in
collected from these sensors is analyzed to assess the health of the structures.

ng
By analyzing the data it is possible to detect cracks and mechanical
fE
breakdowns, locate the damages to a structure and also to calculate the
remaining lifetime of the structure. Using such systems advance warning can,
O
be given in the case of imminent failure of the structure.
e

(5) Surveillance
g
le

Surveillance of infrastructure, public transport and events in cities is required

to ensure safety and security. City wide surveillance infrastructure
ol

comprising
a
of large number of distributed and Internet connected video surveillance
C

cameras.
u
ad

The video feeds from surveillance cameras can

then be aggregated in cloud-based
scalable storage solutions.
iln

(6) Emergency Response

m

IoT systems can be used for monitoring the critical

Ta

infrastructure in cities such

as building, gas and water
pipelines, public transport änd power substation
systems.
IoT systems for fire directions, gas
and water leakage directions can help
generating alerts and minimizing their effects on
the critical infrastructure.
loT systems for critical
infrastructure monitoring enable aggregations and
sharing of information collected
is from large number of sensors. Cloud-based
architectures multi-model
information such as sensor data, feeds
can be analyed in near audio, video
real-time to detect adverse events.
<br>

Page 369 of 440

things 10.27
aernet of

Environment
10.5
Weather Monitoring

IoT-based weather monitoring system can collect data from a number of

sor attached (such as temperature, humidity, presure etc) and send the data

g
to cloud based applications and storage back-ends.

in
The data collected in the cloud can then be analyzed and visualized by cloud

er
based applications.

e
in
Air & Noise Pollution Monitoring

ng
o Air and sound pollution is a growing issue in these days. It is necessary to
monitor the air quality and keep it under control for a better future and healthy
fE
living for all.
O
us to
o An airquality as well as sound pollution monitoring system that allows
e

monitor and check live air quality as well as sound pollution in particular
g

areas through loT.

le

presence of harnmful gases/compounds in the

ol

0 System uses air sensors to sense

air and constantly transmit this data to the
microcontroller. Also system keeps
C

to an online server over IoT.

measuring sound level and reports it
u

microcontroller which processes this 'data and

ad

Ihe sensors interact with

authorities to monitor air pollution
Iransmits it over the Internet. This allows
iln

In different areas and take action against it.

m

B) Forest Fire Detection

Ta

and human life.

natural resources, property
fires can cause damage to
0 Forest

Early deduction of forest fires can help in

minimizingthe damage.

nodes
loT based forest systems can use a number of monitoring
fire detection node collects
deployed a forest. Each monitoring
at a different locations in
temperature, humidity and
measurements on ambiet conditions including
lightlevels.
<br>

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Embedded Systems and loT Design

10.28|
system can alert the local people e
based on the level
IoT forest fire detection IoT can be integrated
with drones
near to them. Also,
severity of fire hazard
GPS and satellite services.

(4) River Floods Detection resources

to the natural and human

g
can cause extensive damage
River flood
rainfall which cause the

in
flood occurs due to continuous
and human life. River

er
to increase rapidly.
river levels to rise and flow rates

e
flow
can be given by monitoring the water level and
Early warnings of floods

in
ng
rate.
uses a number of sensor nodes that
IoT based river flood monitoring system
fE
can monitor the water level using ultrasonic
sensors and flow rate using the
a sensor nodes is aggregated
flow velocity sensors. Data from number of such
O
in a server or in the cloud.
g e

10.5.6 Energy
le

(1) Smart Grids

ol

Smart grid is a data communication network integrated with electrical grid

C

that collects and analyzes the data captured in near real-time about power
u

transmission, distribution and consumption.

ad

Smart grid technology provides protective information and recommendations

iln

to utilities, their suppliers, and their customers on how best to manage the
m

power.
Ta

Smart grids use high speed, fully integrated, two-way communication

technologies for real-time information and power exchange.

Ø Advantages (or) Benefits

() Better billing and better prediction:
(ii) It enables renewable energy generation.

(i) It reduces emission and carbon-heavy electricity.

<br>

Page 371l of 440

hings 10.29
ernet of
Renewable Energy Systems
as
Due to thevariability in the output from renewable energy Sources such
solar and wind, when integrating them into the grid can cause grid stability

and reliability problems.

g
Variable output produces local voltage swings that can impact power quality.

in
can measure
For loT based systems, that are integrates with the transformers

er
the electrical variables and calculate how much
power is fed into the grid.

e
one solution is to simply cut off the
o' To ensure the grid stability,

in
overproduction.

ng
can be used to regulate the
o For wind energy systems, closed-loop controls
voltage at the point
fE
of interconnection which coordinate
wind turbine outputs

and provides reactive power support.

O

(3) Prognostics
e

critical components that must

function
g

0 Energy systems have number of

le

can perform their operations correctly.

correctly, then only the systems
ol

critical components. in operating conditions makes

0 If any sudden changes of
C

information is
failures. In systems such as power grids, real-time
machines
sensors called Phasor Measurement
u

specialized electrical
collected -using
ad

Units (PMU) at the substations.

iln

Sensing
m
Ta

Prognostics and
Diagnosis
Systems Health
Prognostics Management (PHM)

Management

Prognostics system in IoT

Fig 10.15
<br>

Page 372 of 440

10.30 Embedded Systems and loT Design

IoT based Prognostics real-timne Health Management (PIM) system can

predict the performance of machines or energy systems by using sensOrs
information and it was analyzed to predict the failures. So that their reliability
and availability can be improved.

g
in
10.5.7 Retail

er
(1) Inventory Management

e
Inventory management for retail has become increasingly important in the

in
recent years with the growing competition. While over-stocking of products

ng
can result in additional storage expenses and risk.
fE
loT systems using Radio Frequency Identification (RFID) tags can help in
inventory management and maintaining the inventory levels.
O
RFID tags attached to the products that allow them to be tracked in real-time
e

so that the inventory levels can be determined

accurately and the products
g

which are low on stock can be filled.

le
ol

(2) Smart Payments

C

Smart payment solutions such as contact-less payments powered by the

u

technologies such as Near Field Communication (NFC) and Bluetooth.

ad

NFC is a set of standards for smart-phones and other devices to communicate

with each other by bringing them into proximity or by
iln

touching them.
Customers can store the credit card information in their NFC-enabled smart
m

phones and make payments by bringing the smart-phones near

the point
of
Ta

sale terminals.
NFC maybe used in combination with Bluetooth, where NFC
initiates initial
pairing of devices to establish a Bluetooth connection while
the actual data
transfer takes place over the Bluetooth.

(3) Smart Vending Machines

Smart vending machines connected to the Internet allow remote monitoring O

inventory levels, elastic pricing of products, promotions, and contact-less

payments using NFC.
<br>

Page 373 of 440

Internet ofThings
10.31
Smart-phone applications that communicate
with smart vending machines
llow user preferences to be remembered
and learned with time.
Sensors in a smart vending machine
monitor its operations and send the
to the cloud which can be used data
for predictive maintenance.

g
10.5.8 Logistics

in
er
(1) Route Generation & Scheduling

e
Modern transportation systems are driven by the data collected from multiple

in
Sources which is processed to provide a new services to the stakeholders.

ng
It collects large amount of data from various sources and processing the data
fE
into useful information. The data-driven transportation systems can provide
new services such as advanced route guidance and dynamic vehicle routing.
O
o Route generation and scheduling systems can generate end-to-end routes using
e

combination of route patterns and transportation modes and feasible schedules

g

based on the availability of vehicles.

le
ol

(2) Fleet Tracking

C

to track the locations of

Vehicle fleet tracking systems use GPS technology
can analyze the messages sent from the
the vehicles in real-time. This system
u

discrepancies between actual

ad

vehicles to identify unexpected incidents and

actions can be taken,
and planned data, so that the remedial
iln

(3) Shipment Monitoring

m

transportation systems allow monitoring

Shipment monitoring solutions for
Ta

the conditions inside the containers.

its contents to
system monitors the vibration patterns of a container and
Ihe integrity
Teveal the information, related
to its operating environment and its
storage.
during transport handling and
(9) Remote Vehicle DiagnosticS
systems can detect faults in the vehicles
or warn
Remote vehicle diagnostic
use on-board IoT devices for
These diagnostic systems
the impending faults.
status of various vehicle sub-systems.
collectingon vehicle operations and the
<br>

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Embedded Systems and loT Design

10.32
systems with
These data can be captured by integrating on-board diagnostic
IoT devices using protocols such as CAN bus.
Modern commercial vehicles support On-Board Diagnostic(0BD) standards
on the status of vehicle
such as OBD-II. OBM systems provide real-time data

g
sub-systems and diagnostic trouble codes which allow rapidly identifying the

in
faults in the vehicle.

e er
10.5.9 Agriculture

in
(1) Smart Irrigation System

ng
Smart irrigation systems can improve crop yiclds while saving water. Smart
fE
irrigation systems use loT devices with soil moisture sensors to determine the
amount of moisture in the soil and relcases the water flow through the
O
irigation pipes only when the moisture levels goes below a predefined
e

threshold.
g
le

This system also collect moisture level measurements on a server or in the

cloud where the collccted data can be analyzed to plan watering schedules.
ol
C

(2) Green House Control

Green houses are structures with glass or plastic roofs that provide conductive
u
ad

environment for growth of plants. The climatological conditions

inside a green
house can be monitored and controlled to provide the best conditions
iln

for the
growth ofplants.
m

10.5.10 Industry
Ta

(1) Machine Diagnosis & Prognosis

Machine prognosis refers to the prediction
of machine performance by'
analyzing the data on the current operating conditions
and how much
deviations exist from the normaloperating
conditions.
Machine diagnosis deals with the determination
of the cause for machine
fault.
<br>

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ofThings
iernet 10.33|
lndoorAir Quality Monitoring
e
Monitoring indoor air quality in factories
is important for health and safety of
IoT based gas
the workers. monitoring systems can
help in monitoring the
indoor air quality using various gas sensors.

10.5.11 Health &Lifestyle

g
Health. Fitness Monitoring

in
&

er
Wearable IoT devices that allow non-invasive and continuous
monitoring of
physiological parameters can help in continuous health and fitness monitoring.

e
in
These wearable devices may be in various forms such as belts and wrist

ng
bands.

The wearable devices form a type of wireless sensor networks called body
fE
area networks in which the measurements from a number of wearable devices
O
are continuously sent to a master node such as a smart-phone which then
sends the data to a server or a cloud-based back-end for further analysis.
g e

(2) Wearable Electronics

le

Wearable electronics such as smart watches, smart glasses and

wristbands that
ol

us in our daily activities and

provide various functions and features to assist
C

making us to lead a healthy lifestyles.

u

ANSWERS
10.6 TWO MARKSOUESTIONS AND
ad

What is the role of " things" and

Internet in loT?
iln

(LoT) describes the network of physical objects which are

Ihe Internet of Things
other
are embedded with sensors, software, and
m

considered as "things" that

with other
purpose of connecting and exchanging data
Ta

ehnologies for the

devices and systems over the Internet.
*List the applications of
lo1 homes,
a wide range of domains which includes,
The loT span
applications of and
retail, logistics, industry, agriculture
cities, environment, energy systems,
health.
3, Define
IoT. as,
defined
The Intternet of Things (IoT) has been
<br>

Page 376 of 440

Embedded Systems and loT Design

10.34

A dynamic global network infrastructure with self -

contiguring capabilitiee

based on standard and interoperable

communication protocols where physical
and virtual personalities
and virtual “things" have identities, physical attributes,
are seamlessly integrated into the information
and use intelligent interfaces, and
users and their environments
network, often communicate data associated 'with

g
self-configuration?

in
4. Why do loTsystens have to be self-adapting and

er
(i) Self-Adapting
the
IoT devices and systems may have the capability to dynamically adapt with

e
in
changing contexts and take actions based on their operating conditions, user's

ng
* context, or sensed environment.
(ii) Self- Configuring fE
IoT devices may have self-configuring capability that allow a large number of
O
devices to work together to provide certain functionality.
List the characteristics of
IoT.
e

5.
g

The characteristics of IoT are,

le

() Dynamic and self-adapting.

ol

(ii) Self-configuring.
C

(ii) Interoperable communication protocols.

u

(iv) Unique identity.

ad

(v) Integrated into information network.

iln

6. Write the functions of

netsvorklayer in loT.
m

The network layer is responsible for sending of IP datagrams (packets) from the
Ta

source netwotk to the destination network.

This layer performs the host
addressing and packet routing.
7. Mention the functionsof the transport layer.
The functions of the transport layer are,
(i) Error control,
(ii) Segmentation,
(ii) Flow control, and
(iv) Congestion control.
<br>

Page 377 of 440

ternet of
Things 10.35|

What is. the function of

applicationlayer protocol?
Application layer protocol defines howthe applications interface with the lower

layerprotocols to send the data over the network.

data are typically in fileswhich is encoded by the application
The application

g
layer protocol and encapsulated in the transport layer protocol which provides

in
connection or transaction oriented communication over the network.

er
9. What is HTTP?.

e
in
The Hypertext Transfer Protocol (HTTP) is an application layer protocol that
a

ng
forms the foundation of World Wide Web (WWW). This protocol follows

request-response model where a client sends request to the server using the
HTTP commands.
fE
O
10. What do you mean by logical design of an loT?
the entities
of an loT system refers to abstract representation of
e

an
Logical design
g

and processes without going into the low-level specifications of the

le

implementation.
ol

loT system.
C

of
II. Name the functional blocks
The functional blocks of IoT system are,
u
ad

) Device.
(i) Communication.
iln

(ii) Services.
m

(iv) Management.
Ta

(v) Security.
(vi) Application.
12. What
is request-response model?
model in which the client sends request to
Request-response a communications
is requests.
the Server
and the : server responds to the
l3, Name models used in loT.
the communication
) Request-response model.

Publish-subscribe model.
<br>

Page 378 of 440

(ii) Push-pull model.

(iv) Exclusive pair model.
14. What is publisl-subscribe
model?
Publish-subscribe model
is a communication model
brokers and consumers. Publishers are that involves publishers
the source of data and send
topics which is managed the data to the
by the broker. Publishers are

g
consumners. not aware of the

in
Consumers subscribe to the

er
topic that are managed by
broker receives the data for a the broker. Once the
topic from the publisher,

e
subscribed consumers. it sends the data to all the

in
ng
15. Define pusl-pull
model.
Push- pull is a communication fE
model in which the data producers
in to the queues and the consumers can pushes the data
pull the data from the queues.
O
16. What do you mean by
REST based API?
Representational State Transfer
e

(REST) is a set of architectural

you can design principles by which
g

web services and web APls that

focus on a system's resources
le

how resources states are addressed and then and

transferred.
ol

17. What is WSN?

C

Wireless Sensor Networks (WSNs)

comprises of distributed devices
sensor which are with the
u

used to monitor the environmental and

physical conditions. A
ad

WSN consists of a number end-nodes

of and routers and a coordinator.
iln

18. Define cloud computing.

Cloud computing refers to the use
m

servers, databases, networking,

of hosted services, such as data storage,
and software over the Internet. The data is stored
Ta

on physical servers, which are

maintained by a cloud service provider.
Computer
system resources, especially data storage
and computing power, are available on
demand, without the direct management
by the user in cloud computing.
19. What do you mean by big data?

Big data is defined as a collection of data set whose volume is so large that it is
difficult to store, manage, process and analyze the data using traditional database
and data processing tools.
<br>

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1hings
ternet ef 10.37|

Name.the steps
involved in big data analytics.
20
The following steps are involved in big data analytics:

() Data cleaning,

() Data munging (or) wrangling,

(i) Data processing and visualization.

g
in
REVIEW QUESTIONS

er
10.7

Write a note on IoT.

e
1.

in
2 Mention the applications of loT.

ng
3 Discuss in detail about the characteristics of IoT.

4 Explain about the plysical design of IoT. fE

5 With a neat diagram, explain about the loT protocols.
O
6 Eyplain in detail about the logical design of loT with neat diagranms.
e

1 With neat diagranns, explain about communication models used in loT:.

g
le

8. Discuss in detail about tlhe REST based communication APIs.

. loT service that uses publis-subscribe communication
ol

Describe an example
of
C

model.
10. Describe an example
of
IoT service that uses WebSocket-based communication.
u

neat diagrams.
ad

I Eixplain in detail about the loTenabling technologies with

12.
Writea note on
iln
m

(9 Wireless Sensor Networks.

Ta

() Cloud computing.

(i) Big-data analytics.

neat diagrans.
Oscuss in detail about the domain specific loIs, witi
<br>

Page 380 of 440

UNIT -IV
Chapter 11

g
in
MACHINE -TO- MACHINE (M2M)

e er
in
11,1 IoT AND M2M

ng
11.1.1 Introduction
fE
A Definition:
O
A Machine-to-Machine (M2M) connection is 'a connection between two
e

machines without any human interaction that is, it allows two devices to
g
le

communicate autonomously.
M2M devices can autonomously collect and transmit data, facilitating real
ol

time decision-making and improving operational effticiency across various

C

industries.
u

* M2M systems use point-to-point communications between machines, sensors

ad

and hardware over cellular or wired networks, while loT systems rely on IP
iln

based networks to send data collected from IoT-connected devices to gateways in

the cloud or middleware platforms.
m
Ta

1,1,2 M2M Architecture

M2M refers of machines or devices for the purpose of remote
to the networking
monitoring,
control and data exchange. Fig 11.l shows the end-to-cnd
architecture M2M systems which consists of,
for
MZM Area Networks (or) Local Networks,

Communication networks, and

Applications Domain.
<br>

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1l

Embedded Systems and loT Design

112
M2M Core
(or)
M2M Area Communication Network M2M
Network domain Domain Application
Domain

M2M Wired

g
M2M Gateway Network
Devices Service

in
to
Consumer

er
Wireless

e
Network

in
ng
M2M
devices
domain
fE
Fig I1.1 M2M system architecture.
O
(i) Area Networks
e

M2M area network comprises of machines or nodes which have embedded

g

hardware modules for sensing, actuation and communication.

le

The various communication protocols that can be used for M2M local area
ol

networks such as ZigBee, Bluetooth, ModBus, M-Bus, Wireless M-Bus,

C

Power Line Communication (PLC),6LoWPAN, IEEE 802.15.4 etc.

u
ad

These communication protocols provide connectivity between M2M nodes

within an M2M area network.
iln

Gateways:
m

.
M2M Gateway
Ta

Virtual Node
Native Protocol
M2M Node Proxy
Protocol Translation

IP Routing
Virtual Node
Native Protocol
M2M Node Protocol Proxy.
Translation

Fig 11.2 Block diagram of an M2M gateway

<br>

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Vachine-To-Machine (M2M) 11.3

To enable the communication between remote M2M area networks, M2M
gateways are úsed which bridge one or more locally networked devices to
a

iwired or ireless broadband connection. The local network can be wired or

wireless.
M2M gateway acts as
a proxy performing translations from/to native

g
protocols to/from Internet Protocol (IP),

in
er
M2M Core (or) Communication Network

e
The communication network can use either wired or wireless networks

in
use non-IP based communication
P-based) while the M2M area networks

ng
protocols that is, the M2M nodes within one network cannot communicate with
nodes in an external network. fE
(ii) M2M Applications
O
as enterprise applications,
The M2M data is gathered into point solutions such
or remote monitoring applications. M2M has
e

service management applications,

g

as
various application domains follows:
le
ol

Smart metering,
C

Home automation,
Industrial automation, and
u
ad

Smart grids.
iln

M2M
11,1,3Difference between IoT and
m

M2M
Sr.no IoT
Ta

Direct machine-to-machine
1 Internet-based connectivity. communication.

and Specific applications and

Wide range of devices industries.
2
industries..
cellular Uses either an Internet or non
3
Uses the Internet and internet connection.
networks.
Local data processing.
4 Cloud-based storage analytics.
Less scalable.
Most scalable.
<br>

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Embedded Systems and loT Design

11.4
Optimized resource utilization.
6 Efficient resource utilization.
It supports point-to--point
It supports cloud based communication
7 communication.
It is for only Business-to
Itsupports B2B and Business
Business (B2B) types.

g
8 to-customer (B2C) types.

in
Machine normally
Many users can access at a time communicates with single

er
over internets. machine at a time.

e
It uses either proprietary or non

in
10 It uses IIP based protocols. IP based protocols.

ng
11.1.4 SDN and NFV for IoT fE
(1) Software-Defined Networking (SDN)
O

a Definition:
e

uses
Software-Defined Networking (SDN) is an approach to networking that
g
le

software-based controllers or Application Programming Interfaces (APIS) to

ol

communicate with underlying hardware infrastructure and direct traffic on a

C

network.
This model differs from that of traditional networks, which uses dedicated
u

hardware devices (i.e., routers and switches) to control network traffic. SDN
ad

can create and control a virtual network or control atraditional hardware via
iln

software.
m

Fig 11.3 shows the architecture of SDN. The three layers in an SDN
architecture are,
Ta

() Application Layer
This layer contains applications, services running on
the network and decides
how the traffic should move in a network?
(ii) Control Layer

A SDN controller is the software that provides a centralized control over the
entire network. Network administrators use this controller to decide about data
<br>

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ochine-1o-dMachine (M2M)

11.5
route based on the information from applications
packet
using the underlying
infrastructuress and handlethe traffic.

APPLICATION LAYER

g
Business Applications

in
(Northbound Interface)

er
CONTROL LAYER

e
SDN

in
(Control plane) Control
Software

ng
Network Services

(southbound Interface)

INFRASTRUCTURE LAYER
fE
Control Data Plane interface

(e.g., OpenFlow)
O
Network Device Network Device Network Device
g e

|(Data/forwarding Network Device Network Device

Plane)
le
ol

Fig 11.3 SDN architecture

C

(i) Infrastructure/Data Layer

u

This layer contain networking devices such as switches, routers and the
ad

Supporting physical hardware and it receive information from the controller

about where to move the data.
iln

uses a northbound and

O 1o communicate between these layers, SDN
m

northbound
Southbound Application Program Interfaces (API) where the
Ta

layers and the

API communicates betveen the application and the control
layers.
SOuthbound API comunicates between the infrastructure and control
B Limitations:

architectures are,
Ine limitations of the conventional network
Complex
network devices
to improve link speeds and
protocols being implemented
More
and more
reliability.
<br>

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Embedded Systems and loT Design

|11.6|

(i) Management overhead

interfaces from mulinl,
Difficult to manage multiple network devices and
vendors.
(ii) Limited scalability.

g
manage network
Computing environments require highly scalable and easy to

in
architectures with minimal manual configurations. But in conventional networks

er
all are manual configurations.

e
SDN attempts to create a network architecture that is simpler, inexpensive,

in
.
scalable and easy to manage.

ng
M SDN Benefits: Advantages: Key-elements fE
(i) Direct Programmability:
O
SDN network policy is directly programmable because the control functions are
e

decoupled from forwarding functions, which enables the network to be

g

programmatically configured by proprietary or open source automation tools.

le
ol

(ii) Centralized Management: Centralized Network Controller

C

The SDN controller software that maintains a global view of the network, which
appears to applications and SDN network policy as a single and logical switch.
u
ad

(iü) Increased Control with Greater Speed and Flexibility

In SDN, developers can control the flow of traffic over a network simply by
iln

programming an open standard software-based controller.

m

Networking administrators also have more flexibility in choosing the

Ta

networking equipment, since they can choose a single protocol o

communicate with any number of hardware dcvices through a central
controller.
(iv) Customizable Network Infrastructure:

With a SDN, administrators can configure the network services and allocate
virtual resources to change the nctwork infrastructure in real time througu
one centralized location.
<br>

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Machine-1o-Machine (M2M)
11.7

This allows network administrators to optimize the flow of data through the
network and pioritize applications that require more availability.

Standard. Communication Interface: Open Flow

(
.The. Open Flow (0F) protocol is a standard in SDN architecture. This

g
southbound protocol defines the communication between an SDN controller

in
and the network device/agent such as switch.

er
.
The SDN controller takes the information from the applications and converts

e
them into flow entries, which are fed to the switch via OF. It can also be

in
used for monitoring switch and port statistics in network management.

ng
The term “switch" denotes any network device capable of using OF protocol.
fE
The controller can add, update, and delete flow entries in flow table.
O
SDN Controller
g e

OpenFlow
le

Protocol
ol

OpenFlow Group Table

C

Channel
u
ad

Pipeline
iln

Flow Table
Flow Table
m

OpenFlow Switch
Ta

Flow (OF) switch

Fig l1.4 Open to do
store flow entries or flows that tell the SDN switch what
Flow tables
comes to an incoming port.
With a packet when it
parameters like IP address, port number,
Ihe switch will match specific
etc and select the best matching
flow entry from
MAC address. VLAN ID,
execute the action associated with that entry.
he table and
forward it to a different port, flood the
Actions could be to drop the packet,

Packet, or send it to the

controller to further inspect it.
<br>

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Embedded Systems and loT Design

11.8|

(2) Network Function Virtualization (NFV)

a Definition:
to the use of virtual
The term "Network Functions Virtualization" (NF) refers
are act
machines in place ofphysical network appliances. The virtual machines
load
as a hypervisor to operate networking sofiware and procedures like

g
in
balancing and routing by virtual computers.

er
a Hypervisor:

e
A hypervisor is a software that you can use to run multiple virtual machines

in
on a single physical machine. Every virtual machine has its own operating

ng
system and applications.
fE
The hypervisor allocates the underlying physical computing resources such as
CPUand memory to individual virtual machines as required.
O
M Advantages of NFV: Need of NFV
g e

With the help of NFV, it becomes possible to separate communication

le

services from the specialized hardware like routers and firewalls. This
ol

eliminates the need for buying a new hardware and network operations can
C

offer new services on demand.

u

Virtual Network Functions

ad
iln
m
Ta

NFV Infrastructure NFV

Management
Virtual Virtual Virtual 8
Compute Network Storage Orchestration

Virtualization Layer

Compute Network Storage

Fig 11.5 NFV architecture

<br>

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jlachine-To-Machine (M2M)
11.9
With this, it is possible to
deploy network
components in a matter of hours
onnosed to months as with conventional
as networking. Furthermore, the
virtualized. services can run on less expensive
generic servers.
Fig 11.5 shows the NFV architecture and the key elements are as follows:

g
Virtualized NetworkFunction (VNF): Applications
)

in
VNF is a software implementation of a network function which is capable
of

er
running over the NFV Infrastructure (NFV).

e
Software delivers many forms of network functionality such as virtualized

in
network functions by substituting for the hardware elements for a

ng
conventional network design.
(ö) NEV
fE
Infrastructure (NFVI): Centralized Virtual Network Infrastructure
O
The foundation of an NFV infrastructure can be a hypervisor that abstracts
the resources for computation, storage, and networking that are virtualized.
g e

(ii) NFV Management and Orchestration:

le

Itmainly focuses on all virtualization specific management tasks and

ol

covers orchestration and life-cycle management of physical and /or

C

the
software resources that support the infrastructure virtualization, and
u

life-cycle management of VNFs.

ad

IOT SYSTEM MANAGEMENT WITH NETCONF-YANG

iln

2
m

11,2.1 Need
for IoT Systems Management
Ta

0 Automating configuration,

) Monitoring operational and statistical data,

) Improved reliability,

") System wide configurations,

() Multiple
system configurations, and
() Retrieving
and reusing
configurations.
<br>

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Embedded Systems and loT Design

11.10
(NETCONF)
11.2.2 Network Configuration Protocol
A Definition:
The Network Configuration Protocol (NETCON) is a network management
protocol allowing a Network Management System (NMS) to deliver, modif.

g
in
and delete configurations network devices.
of

Programming Interfaces (APIs) are available on.

er
Standard Application
netvork devices for the NMS to manage the devices using NETCONF.

e
in
NETCONF uses Extensible Markup Language (XML)-based data encoding for

ng
the configuration data and protocol messages, and uses a simple Remoe
Procedure Call (RPC) mechanism to implement the communication between a
fE
client and a server.
O
A client can be a script or an application running on an NMS. A server is
typically a network device.
g e

.
le

Disadvantages of CLI and SNMP

Conventional network management' methods are Command-Line Interface
ol

(CLI) and Simple Network Management Protocol (SNMP).

C

CLI-based configuration is complex and difers greatly according to vendors.

u

SNMP does not support the transaction mechanism, resulting in a low

ad

configuration efficiency. Therefore, it is typically used for monitoring

iln

purposs.
M
m

Advantages
Ta

To overcome the disadvantages of CLI and SNMP, XML-based NETCONF is

introduced, which has the following advantages:

(i) NETCONF uses a hierarchical protocol framework that makes it more

suitable for on- demand, automated, and big data requirements or
cloud-based networks.
(ii) NETCONF uses XML encoding to define messages and uses the RPC
mechanism to modify configuration data. This facilitates configuration data
management and interoperability between devices from different vendors.
<br>

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tachine-To-Machine (M2M)
11.11

NETCONF performs operations on devices

(ii) based on the YANG model,
reducing he network faults caused by manual configuration errors.

NETCONF provides security mechanisms such as authentication

(iv) and
authorization to ensures message transmission security.

g
Basic Network Architecture of NETCONF

in
)

er
A
NETCONF system contains atleast one NMS that manages nctwork-wide

e
devices. Fig l1.6 shows the basic nctwork architccture of
NETCONF.

in
NETCONF Server

ng
fE
O
NETCONF Client
e

IP Network
g
le

NMS
ol
C
u
ad

SSH
iln

architecture of NETCONF
Fig I1.6 Basic network
m

architecture consists of two roles: client and server. A client

O The NETCONF
Ta

provides the following functions:

using NTCONF.
Manages network devices
) one or
requests to a NETCONF server to query or nodify
(1) Sends RPC
more parameter values.
events
based on the alarms and
() Learms the status of a managed devicc
server of the managed device.
Sent by the NETCONF
managed devices and responds to the
A
server maintains information about
clicnt-initiated requests.
<br>

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11.12 Embedded Systems and loT Design

(i) When recciving a request from a NETCONF client, the NETCONE

server parses the request and sends a reply to the client.
(ii) If a fault or another type of event occurs on a managed device, the
NETCONF server reports an alarm or event to the client through the

g
notification mechanism. This allows the client to learn the status of the

in
managed device.

er
(2) Establishing a NETCONF Session

e
The NETCONF client and server uses the RPC mechanism to communicate

in
with each other. The communication is allowed only after a secure and

ng
connection-oriented session that is established between them.
fE
The client sends an RPC request to the server, and the server returns .a reply
to the client after processing that request.
O
NETCONF Client NETCONF Server
g e
le
ol

Establish an SSH connection

C

Send Hello messages to advertise supported capabilities

u

Send an RPC request

ad

Return an RPC reply

iln

Terminate the NETCONF session

m

Return a NETCONF session termination response

Ta

Terminate the SSH connection

Fig 11.7 Process of establishing a NETCONF session

The process of establishing and terminating a NETCONF session is detailed
as follows:
<br>

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Machine-1o-Machine (M2M)
11.13
A
client establishes a Secure Shell (SSH)
connection with a server,
and then establishes a NETCONF session
with the server once the
authentication and authorizations are
complete:

6) The client and server send Hello messages to negotiate

capabilities.

g
Gi) The client sends one or more RPC requests to the server.

in
The following lists some request examples:

er
Modify and commit the configuration.

e
in
Query the configuration data or status.

ng
Perform the maintenance operations on the device.
(iv) The client terminates the NETCONF session. fE
(v) Finally, the SSH connection is terminated.
O
e

11,2.3 Yet Another Next Generation (YANG)

g

to model configuration and state data

le

& YANG is a data modeling language used

YANG modules contain the definitions
ol

manipulated by the NETCONF protocol.

to maintain the
RPC calls that can be issued
C

of the configuration data, state data,

u

format of the notifications.

ad

YANG Module
iln

Header
revision)
(.,
m

includes
Ta

Import and

Type definitions

operational
Configurational and
declaration
data

notification
Action (RPC) and
declarations

YANG module
Fig 11.8
<br>

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Embedded Systems and loT Design

|11.14|
define the data exchanged between the NETCONF client and
YANG modules
structures in an XML tree
server. YANG is a modular language representing data
comes with a number of built-in data types
format. The data modeling language
can be derived from the built-in data
j Additionally application specific data types

g
can be represented as groupings.
types. More complex reusable data structures

in
YANG is gradually becoming a mainstream data description
specification in the

er
all define their
industry. Standards organizations, vendors, carriers, and OTTs

e
in
own YANG models.
The YANG model is integrated on the devices, which function as the servers.

ng
Network administrators can use NETCONF or RESTCONF to centrally manage,
fE
configure, and monitor various YANG-capable network devices, simplifying
network O&M (operations & maintenance) and reducing O&M costs.
O
g e
le

NMS IT O&M system

ol

YANG model YANG model

NETCONF
C

client
RS RESTCONF
client
u
ad
iln

Network
SSH
m

HTTPS
Ta

NETCONF YANG RESTCONF

server model
Server

Fig 11.9 Network management arclitecture

based on
NETCONF/RESTCONF and YANG
# This module comprises of a number of leaf 'nodes that are organized into a
hierarchical tree structure. The "leaf nodes are specified using
the 'leaf' or 'leat
list' constructs. Leaf nodes are organized using 'container' or
list' constructs.
<br>

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Machine-1o-Machine (M2M) 11.15

YANG module can import definitions from other modules. Constraints can be

defined on the data nodes, e.g. allowed values. YANG can model both the
configuration data and state data usingthe'config' statement.

Element Description

g
Module YANG constructs a data model as module. The module

in
name is the sáme as the YANG file name.

er
reference
A module can import data from other modules and

e
data from sub modules,

in
a unique URO.
Namespace of the module, which is globally

ng
Namespace
Namespaces are used during XML encoding of data.

Prefix
fE
Abbreviation of a namespace, which must be unique.
O
YANG belongs.
Organization Name of the organization to which
module developer.
Contact information of the YANG
e

Contact
g

Functions of the YANG module

le

Description
YANG module, providing the
Version information of the
ol

Revision
the module.
version editing history of
C

group related nodes into a subtree.

Container node, used to
u

Container
a sequence of list entries.
ad

used to define
List List node, or a
contains simple data such as an integer
Leaf node,which
iln

Leaf
character string.
m

of lhe YANG
model
Elements
Fig 11.10
Ta

NETCONF-YANG
Managements with
11.2.4 IoT Systems
device management with
approach of IoT
Fig 11.11 shows the generic' as follows:
contains various components
NETCONF-YANG which

W Management System:
NETCONF messages to
send
The managemen system to
Operator uses a
information and notifications from
receives state
configure the IoT device and
he device as NETCONF messages.
<br>

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Embedded Systems and loT Design

11.16|

g
Management System

in
e er
NETCONF

in
ng
NETCONF Server
fE
Transaction Rollback
Management
Manager Manager
O
API
e

Authentication,
g

Data Model Configuration Authorization &

Validator
le

Manager
|Auditing Modules
ol
C

Configuration Data Provider

Configuration
YANG API API
Database
u

Modules
ad
iln

loT Device

Applications
m

Maaged
Objects (Status, Statistics,Performance,
Alarms,Countors)
Ta

Fig 11.1I IoT device management with NETCONF-YANG: Generic approaclh

(ii) Management API:
It allows the managements applications to start NETCONF
sessions, read and
write configuration data, read state data, retrieveconfigurations,
and invoke
RPCs, programmatically.
<br>

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chine-To-iachine (M214)

11.17
Transaction Manager:

Transaction manager executes

all the NETCONF transactions
ACID (Atomicity, Consistency,
and ensures that
the Isolation, Durability)
properties for the
transactions.

Rollback<Manager:

g
Rollback manager
is responsible
for generating
all the transactions necessary to

in
a
ollback cúrrent contiguration to its original state.

er
Data Model Manager:

e
Itkeens track of all the YANG data models and

in
the corresponding managed

ng
objects and also keeps track of the aplications which provide data for cach pat

of a data model.
Configuration Validator:
fE
i)
O
a transaction would
It checks whether the resulting configuration after applying
be a valid
e

configuration.
g

vi) Configuration Database:

le

data.
This database contains both the configuration and operational
ol

MiljConfiguration API:
C

on the loT device can

read configuration data from
Using this the applications
u

store and write an operational data to the operational data

ad

the configuration data

store.
iln

lx) Data Provider APl:

events using
callbacks for various
m

can register for

Pplications on the IoT device provider API, the
applications can report
Ta

the data provider APL. Through the

data

statistics and an operational data.

METHODOLOGY
11,3 IOT PLATFORMS DESIGN
methodology.
system design
the oT
* Fig 11.12 shows the steps involved in
follows:
Each of these are explained as
stcps
Step Specification
1: Purpose & Requirements define the
purpose and
methodology is to
design
The first step in loT system
Tequirements of the system.
<br>

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Embedded Systems and loT Design

11.18|
as data
In this step, the system purpose, behavior and requirements such
collection requirements, data analysis requirements, system management
user interface
requirements, data privacy and security requirements and
requirements are defined.

g
Purpose & Requirements

in
Define Purpose & Requirements of loT system

e er
Process Model Specification

in
Define the use cases

ng
Domain Model Specification
fE
Define Physical Entities, Virtual Entities, Devices, Resources and Services in the loT system
O
Information model specification
Define the structure (e.g.relations, attributes)of all the information in the loT system
g e
le

Service Specifications
Map Process and Information Model to services and define service specifications
ol
C

loT level specification

Define the loT level for the system
u
ad

Functional View Specification

iln

Map loT level to functional groups

m

Operational View Specification

Ta

Define communication options,service hosting options,storage

options,device options

Device & Component Integration

Integrate devices, develop and integrate the components

Application Development
Develop Applications

Fig ll.12 Steps involved in loT system design metlhodology

<br>

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Achine-To-Machine (M2M)
11.19|

Process Specification
Step2:
The second step is to define the process specification.
In this step, the use
aases of the loT system are
formally based on and derived from the purpose
and requirement specifications.

Ddomain Model Specification

Step 3:

g
The domain model describes the main concepts, entities and objects in
the

in
domain of loT system to be designed.

er
Domain model defines the attributes of the objects and relationships between

e
the objects, provides an abstract representation of the concepts, independent of

in
any specific technology or platform.

ng
Step 4: Information Model Specification
fE
The information model defines the structure of all the information in
an

represented or stored.
O
IoT system. It does not describe how the information is

Service Specifications
e

Step 5:
system, service types,
g

Service specifications define the services in the IoT

le

endpoints, service schedules, service

service inputs/output, service
ol

preconditions and service effects.

C

Step 6: loT Level Specification

u

level for the system.

This sixth step defines the loT
ad

Step 7: Functional View Specification

the functions of
View (FV) which defines
iln

the Functional
This step describes Groups (FGs).
various Functional
m

grouped into
the loT systems for interacting with instances of
provides functionalities
Each FG either information related to these
Ta

domain model or provides

Concepts defined in the
concepts.
Step Specification
8: Operational View
system deployment and
options pertaining to the loT
In this step, the various storage options, device
as, service hosting options,
Operation are defined such
ctc.
options, application hosting options,
: Device & Component Integrationconnections of all the loT devices and
Step 9:
overall
This step defines the
Components in loT platforms.
<br>

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Embedded Systems and loT Design

11.20
Step 10: Application Development
Application development, or app development, is the process of planning.
designing, creating, testing, and deploying a software application to perfom
various business operations.
It can be done by massive organizations with large teams working on projects

g
in
or by a single freelance developer.

er
Code
Development

e
in
&
Design & Testing

ng
Prototyping Optimization

fE
The process of
O
Planning & APP
Research
Release &
Development Maintenance
g e

Fig l1.13 App development

le

loT integration means making the mix

of new loT devices, IoT data, IoT
ol

platforms and loT applications that are combined with

IT assets (business
C

applications, legacy data, mobile, and SaaS), works well

together in the context
u

of implementing end-to-end loT business solutions.

ad

11.4 IoT REFERENCE ARCHITECTURE AND REFERENCE MODEL

iln

11.4.1 Introduction
m

An Architecture and Reference Model

(ARM) consists
Ta

of twomain parts:
(i) Reference architecture, and
(ii) Reference model.
reference model is a model that describes
A

the main conceptual entities ana

how they are related to each other, while
the reference arclhitecture ains af
describing the main functional components a system as
of well as how the systen
works, how the system is deployed, what
information the system processes, ete.
<br>

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-To-Machine (M2M)

1.21
Architccture Reference
Model(ARM)

Understand loT Roference

ModelARIA)

g
guidos

in
Unifad steer
loT Reference

er
Requirements
Architecturo

e
extrapolate guidos wth

in
Best Practices
Business Scenarios,

ng
kppication
existing architecturcs& defino Compant
specific
Domain-Spccifc
stakcholders Requzements
Architectures
fE
O
Steps in order to crcate an ARIA Stops to uso ARM
g e

Fig l1.14 loT reference architecture and reference model dependency

le
ol

11.4.2 IoT Reference Architecture

C

& Definition:
u

dn loT reference architecture serves as aoundational blueprint that outlines the

ad

csential components and interacions wilhin an loT system. provides u solid I

iln

Sfartling point for designing and inplementing loï solutions.

m

& Benefits
Ta

a
A reference architecture serves as standardized blueprint that provides
a

implementing an loT' system.

clear structure and guidelines for designing and
tacilitates communication
II enables consistency, promotes best practices, and
andcollaboration among stakeholders.
ensure interoperability, and
The developers can reduce design complexity,
leading to more cicient and
accclerate the development process, ultimately
reliable loT solutions.
<br>

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11.22 Embedded Systems and loT Design

Application'

Management Service loT Process Virtual oTService Security

Organisation Management Entity
Process Modelling
Service Authorisation

g
Configuration
Composition
Process Execution

in
Key Exchange &
Fault Service VE & loT Management

er
Orchestration Service Monitoring
Reporting Trusrt &

e
Service VE Reputation
Member Choreography Resolution|VE Services

in
Identity
State loT Service Management

ng
loT Service
Resolution
Authentication

End to End
fE
Communication
Network Hop to Hop
|Communication Communication Communication
O
Device
g e

Fig I1.15 loT reference architecture

le

The loT reference architecture is described in the following

ol

three views:
(i) FunctionalView
C

Description of what the system does, and its main functions.

u
ad

(i) Information View

Description of the data and information that the system
handles.
iln

(ii) Deployment and Operational View

m

Description of the main real world components

of the system such as
Ta

devices, network routers, servers, etc

The IoT functional view for IoT reference
architecture is described as follows:.
(6) Device
and Application Functional Group (FG)
The physical devices or sensors that collect data from
the environment
or interact with the physical
world. These devices can incluae
temperatüre sensors, motion detectors, cameras, and other IoT-enabled
devices.
<br>

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achine-1o-Machine (M2M)
11.23|
The software applications ór
services that utilize
the processed loT data
to provide specific functionalities.

Communication Functional Group:

()
. It takes care' of node-to-node (hop-by-hop)
communication until they
reach a gateway node which forwards message

g
the (if needed) further to

in
the Internet.
. The

er
Network Functional Components (FC)
is responsible for message

e
routing & forwarding and the necessary translations
of various

in
identifiers and addresses.

ng
(i) loT Service Functional Group

i
fE
The IoT Service FC is a collection of service implementations, which
interface the related and associated resources.
O
(iv) Virtual Entity (VE) Functional Group
g e

It contains functions that support the interaction between users and

le

physical things through Virtual Entity services.

ol

(v) Process Management Functional Group

C

It is an integration of business processes with loT-related services

u

which consists of two FCs:

ad

modeling a
(a) The process modeling FC provides the right tools for
loT-related services.
iln

business process that utilizes

the execution environment of
(b) The Process execution FC contains
m

by the process modeling FC.

the process models created
Ta

(i) Service Organization Functional Group

the descriptions and execution
The service conposition FCmanages
simpler dependent
environment of complex services consisting of

services.
the requests coming from loT
The service orchestration FCresolves
concrete loT services that fulGl!
process execution FC or user into the

the requirements.
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Embedded Systems and loT Design

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Theservice choreography FCis a broker for facilitating the
pattem
communication among services using the publish/subscribe
Users who are interested in specific loT-related services
subscribe to tha
even if the
choreography FC, providing the desirable service attributes
desired services do not exist.

g
in
(vi) Security Functional Group

er
The Security FG contains the necessary functions for ensuring the
security and privacy of an loT system.

e
in
The identity. management FC manages the different identities of the

ng
involved Services or Users in an loT system.
fE
The authentication FC verifies the identity of a user and creates an

assertion upon successful verification.

O
The authorization FC manages and enforces access control policies. It
e

provides services to manage policies as well as taking decisions and

g

enforcing them regarding access rights of restricted resources.

le

The key exchange & management is used for setting up the necessary
ol

security keys between two communicating entities in an IoT system.

C

The trust & reputation FCmanages reputation scores of different

u

interacting entities in an loT system and calculates the service trust

ad

levels.
iln

(vii) Management Functional Group

m

The configuration FC maintains the configuration

of the FCs and the
Ta

devices in an IoT system. The component

collects the current
configuration of all
the FCs and devices, stores it in a historical
database, and compares current and historical configurations.
The fault FC detects, logs, isolates, if
and corrects system-wide faults
possible. This means
that individual component fault reporting triggers
fault diagnosis and fault recovery
procedures in the Fault FC.
The member FC manages relevant
membership information about the
entities in an IoT system.
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Machine-To-Machine (M2M)
11.25|

The state FCis similar to the

configuration FC, and collects and logs
state information from the current FCs. which can be'
used for fault
diagnosis, performance analysis and prediction, as well as billing
purposes.

g
The reporting FC is responsible for producing compressed reports
about

in
the system state based on input from FCs.

er
11.4.3 IoT Reference Model: Domain Model

e
in
loT loT Trust,

ng
Communicational Security and
Model Privacy Model

fE
O
loT Comm.FG} Sec.
Functional
FG
Model
g e

Informationan handled by
le

Functional Components
ol

Concepts as
C

loT Information
foundations of
Model
Functional Groups
u
ad

Concepts explicitly modelled

systems
& represented in loT
iln

loT Domain Model

m
Ta

reference model
Fig l1.16 loT
sub-models. The
describes the domain using a number of
A Teference model
main concepts and the
attributes of the
domain mnodel .captures the basic
domain model also serves as tool for
a
A

relationship between these concepts.

working in the domain in question and
human communication between people
betweenj whO work
across different domains.
people
The sub-mnodels of the IoT domain model are,

() loT information model,

<br>

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Embedded Systems and loT Design

|11.26|

(ii) IoT functional model,

(iii) IoT communication imodel, and
(iv) IoT trust, security and privacy model.
IOT domain modei contains the following entities:

g
User.

in
Physical entity.

er
Virtual entity.

e
Augmented entity.

in
Devices.

ng
Resource.
Service. fE
# In the IOT domain model, devices are technical artifacts that behave as interfaces
O
between the digital (Virtual Entity) and physical (Physical Entity) world.
Therefore, devices must have capabilities (like storage, computation &
e

communication) to operate in the digital as well as the physical world. Also

g

resources available in devices also play a very critical role in the overal
le

operation.
ol

(1) loT Information Model

C

Virtual Entity in the IoT domain model is the "Thing" in the Internet
of
u

Things.The loT information model captures the

details a virtual entity and
ad

of
it is presented using Unified Modeling Language
(UML) diagrams.
iln

Virtual Entity
m
Ta

is association with

Service

exposes

Resource hosts
Device

Fig l1.17 IoT information model

<br>

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Machine-Tb-Machine (M2M) 11.27

(2) loT Functional Model

The IoT functional model aims at describing mainly the Functional Groups
(FG) and their interaction with the ARM, while the functional view of a
reference architecture describes the functional components of an FG,

g
interfaces, and interactions between the components.

in
The functional view is typically derived from the functional model in

er
conjunction with high-level requirements.

e
Application

in
ng
Organisation
loT Business Process
Management fE
Management
O
Virtual Entity Security

Service
e

loT Service
g
le
ol

Communication
C

Device
u
ad

Fig l1.18 IoTfunctional model

iln

(3) Communication Model

process, which
o Communication models are systematic representations of the
m

can be done.Communication
helps in understanding how communication works
Ta

model communication.
models try to capture, explain, simplify, and then
(4) Trust, Security & Privacy Model
(i) Privacy
privacy model
User privacy is an utmost importance for LoT system. The IoT-A
depends on the following functional components:

Identity management,
Authentication,
<br>

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Embedded Systems and loT Design

11.28

Authorization, and
Trust & Reputation

(ii) Trust
entity makes
Generally, an entity is said to 'trust' a second entity when the first

g
as the first entitu
the assumption that the second entity will behave exactly

in
er
expects.

e
(ii) Security

in
focuses
The security model for loT consists of communication security that

ng
mostly on the confidentiality and integrity protection of interacting entities.

11.4.4 Communication Models in IoT

fE
O
4 Communication models used in loT allow people and things to be connected
any time, any space, with anything and anyone, using any network and any
g e

service. Some of the communication models are,

le

) Request & Response model

ol

(ii) Publisher-Subscriber model

C

(ii) Push-Pull Model, and

u
ad

(iv) Exclusive pair model.

iln

Note
m

For additional information Refer, Chapter-10, Page Nos: 10.12 - 10.14.

Ta

11.5 IOT PROTOCOLS

11.5.1 MQTT

a Definition:

MTT stands. for Message Queuing Telemetry is a lighnweight

Transport. I
footprint
messaging protocol, for use in cases where clients code
needasmall
<br>

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1ochine-To-Machine (M2M)
,
11.29|
and are connected to unreliable networks or networks with limited
resources. bandwidth

4
MQTT is primarily used for machine-to-machine
(M2M) communication or
Internet of Things types of connections.

g
Publish

in
Client
Message

er
Message
Publish

e
Suscriber
Publish Message

in
MQTT
Client
BROKER

ng
Message Publish
Message Suscribér
Publish
fE
O
Client
g e

Fig l1.19 MQTT architecture

le

defining the clients and

MQTT implements the publish/subscribe model by
ol

brokers as below:
C
u

0) MQTT client
ad

microcontroller that runs on

any device from a server to a
An MTT client is
iln

messages, it acts as a publisher, and

an MTT library. If the client is sendng
m

acts as a receiver.
if it is receiving messages, it can be
using MQTT over network
a
Ta

communicates
Basically, any device that
called an MTT client
device.

(i) MOTT broker

messages
system which coordinates
the backend
The MOTT broker is the broker include
receiving
clients. Responsibilities of
between the different clients subscribed to each
message, and
messages, identifying as:
and filtering responsible for other tasks such
messages. It is also
Sending them the
<br>

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11.30|
Embedded Systems and loT Design

Authorizing and authenticating MQTT clients.

Passing messages to other systems for further analysis.
Handling missed messages and client sessions.

g
(ü) MQTT connection

in
Clients and brokers begin communicating by using an MQTT connection.

er
Clients initiate the connection by sending a CONNECT message to the MQTT

e
broker. The broker confirms that a connection has been established by

in
responding with a CONNACK message. Clients never connect with each

ng
other, they connects only with the broker.
Advantages
fE
O
The advantages of MQTT are,
(6) Lightweight and efficient
g e

MQTT implementation on the loT device requires minimal resources, so that it.
le

can even be used on small microcontrollers. MQTT message headers are also
ol

small so that network bandwidth can be optimized.

C

(ii) Scalable
u

MQTT implementation requires a minimal amount of code that consumes very

ad

little power in operations.

iln

(ii) Secure
MQTT makes it easy for developers to encrypt messages and authenticate
m

devices and users using modern authentication protocols.

Ta

(iv) Well-supported
Several languages like Python have extensive support for MQTT Protocol
implementation. Hence, developers can quickly minimal
implement it with a
coding on any type of application.

11.5.2 XMPP
4 XMPP is a short jorm for Extensible Messaging Presence Protocol.
protocol Jor streaming XML elements over a network in order to exchange
<br>

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Mchine-To-Michine (M2M)
|11.31

messages and presence information in close to real time. This protocol

mosty usedl by instant messaging applications like WhatsApp.

Functions
% Requirements:
The following are the basic requirements of any Instant Messenger which are

g
fulfilled by XMPP:

in
A Send and receive messages with other users.

er
(Gi) Check and share presence status.

e
(i) Manage subscriptions to and from other users.

in
(v) Manage contact list

ng
() Block communications (receive message, sharing presence status, etc) to
specific users.

Decentralized:
fE
O
XMPP is based on client-server architecture, i.e. clients don't communicate
directly, they do it with the help of server as intermediary. It is decentralized
g e

means there is nó centralized XMPP server just like an email, anyone can run
le

their own XMPP server.

ol

A Addresses in XMPP
C

"Addresses in XMPP are similar to standard e-mail addresses with a couple of

u

notable differences. JIDs include an optional node, a domain, and an optional

ad

resource in the form:

" resourcel
iln

[node " @"]domain |"/

m

Direct Client -Client Communication

Ta

Client Client
stanza
stanza

Client Plug-ins Client

XMPP Server XMPP Server

Client Client
XMPP Component

Fig 11.20 XMPP architecture

<br>

Page 41l of 440

|11.32| Embedded Systems and loT Design

are
In XMPP architecture, a client communicates with another client when both
in same domain. The servers can also communicate for the purpose of routing
between domains.
Each client implements the client form of the protocol, where the server provides

g
routing capability. Gateways can cxist for purposes of translating between

in
foreign messaging domains and protocols.

e er
11.5.3 MODBUS

in
Modbus or MODBUS is a client/server, data communications protocol in the

ng
application layer of the OSI model. Itwas originally published by Modicon in
fE
1979 for use with its Programmable Logic Controllers (PLCs).

Modbus is a request-response protocol implemented using a master-slave

O
relationslip. In the communication always occurs in pairs, one device must
e

initiate a request and then wait for a response. The initiating device (the master)
g

is responsible for initiating every interaction.

le
ol

Modbus client Modbus client

C

Computer HMI
u
ad

Read /Write Read /Write

Response request Response request
iln

Ethernet Modbus TPC

m

Response Read /Write

Ta

request

PLC
PLC

Modbus server
Modbus server

Fig 11.2l Modbus protocol

The PDU consists of a
one-byte function code followed by up to 252 bytes of
function-specific data. The function code is the first item to
be validated. Ir uie
<br>

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ichine-To-Machine
(M2M)
11.33|

function code is not recognized by

the device receiving the request, it responds
with an exception.

Function
Code Function -Specific Data

1
0
253 maxX

g
Fig l1.22 Modbus PDU

in
The packet size is limited to.253 bytes, the

er
# most common
function codes can
ransfer between 240 and 250 bytes of actual data from the slave data model,

e
depending on the code.

in
ng
* Modbus uses the Transmission Control Protocol (TCP), which provides
connection-oriented communication, error detection, and flow control.
fE
Advantages
O
The advantages of Modbus are,
e

() Simple but efficient technical architecture.

g
le

() Very easy integration with installations.

ol

(üi) High reliability.

C

11.5.4 CANBUS with BACNet

u
ad

The Controller Area Network (CAN bus) is a message-based protocol designed

automobiles, as
to allow the Electronic Control Units (ECUs) found in today's
iln

a
well as to communicate with each other in reliable, priority
other devices,
m

driven fashion.
Ta

Building Automation Systems (BAS) t0

*BACnet is a network protocol used in
devices and components. BAChet
Control the data exchange between diferent

Siands forBuilding Automation and

Control Network.

gateway(PG-103-194) give a solution as a powerful and

Ihe CAN to BACNet
as a building &
flexible and productive
Dustanding processor that is completely
to
gateway, allowing integrators to easily connect devices
adustrial automation
and industrial facilities.
ielworks in a commercial buildings
<br>

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Embedded Systems and loT Design

|11.34|

A
T BACNet Network
CAN Network

W
A
Y

g
Node Node
Node

in
Node

er
Fig 11.23 CANbus with BacNet

e
and converts it to BACnet IP
The gateway reads the data from the CAN channel

in
message IDs, and the
format. The messages can be filtered by their CAN

ng
iñcoming bytes of data can be received.
a
fE
The BACnet IP can be set up as client, and data from the
CAN interface can be
O
written to the BACnet server.
BACnet client devices can read data from the gateway which- we received from
g e

CAN end if it's configured as a BACnet IP server.

le
ol

Features:
C

i) Up to 1000 points can be interconnected.

u

(i) Integrated Serial Port (one wire)

ad

(ii) Faster data transmission while decreasing the network traffic.

iln

11.6 TwO MARKS QUESTIONS AND ANSWERS

m

1. What is M2M connection?

Ta

A Machine-to-Machine (M2M) connection is a connection between two

machines without any human interaction that is, it allows two devices to
communicate autonomously.
M2M devioes can autonomously collect and transmit data, facilitating real-time
decision-making and improving operational efficiency across various industries.
2. Name the components of M2M system.
The architecture for M2M systems consists of,
(i) M2M Area Networks (or) Local Networks,
<br>

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Machine-To-Machine (M2M)
11.35
() Communication Networks, and
(i) Applications Domain.
3. List the applications of M2M

M2M has various application domains as

follows:
) Smart metering,

g
in
(ii) Home automation,

er
(iii) Industrial automation, and

e
(iv) Smart grids.

in
4. Give the comparisons between IoT and M2M.

ng
Sr.no IoT fE M2M
1 Internet-based connectivity. Direct machine-to-machine
O
communication.
. Wide range of devices and Specific applications and
2
e

industries. industries.
g

Uses the Internet and cellular Uses either an Internet or non

le

3
networks. internet connection.
ol

4 Cloud-based storage analytics. Local data processing.

C

5 Most scalable. Less scalable.

u
ad

6 Efficient resource utilization. Optimized resource utilization.

iln

It supports cloud-based It supports point-to-point

7
communication. communication
m
Ta

$. Define SDN.
Software-Defined Networking (SDN) is an approach to networking that uses
software-based controllers or Application Programming Interfaces (APIs) to
communicate with underlying hardware infrastructure and direct traffic on a
network.
O., Name the layer used inSDN.
The three layers used in SDN architecture are,

() Application layer,
<br>

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Embedded Systems and loT Design

11.36
(i) Control layer, and
(ii) Infrastructure/Data layer.
APIs.
7. functions of northbandánd southband
Write the
uses a northbound and southbound
To communicate between these layers, SDN

g
northbound API communicates
Application Program Interfaces (APIs) where the

in
between the application and the control
layers and the southbound API

er
communicates between the infrastructure and control layers.

e
of conventional network architectures.

in
8. Give the limitations

ng
The limitations of the conventional network architectures are,
(i) Complex network devices fE
More and more protocols being implemented to improve link speeds and
O
reliability.
(i) Management overhead
e

Dificult to manage multiple network devices and, interfaces from multiple

g
le

vendors.
ol

(ii) Limited scalability.

Computing environments require highly scalable and easy to manage
C

network architectures with minimal manual configurations. But in

u

conventional networks all are manual configurations.

ad

9. Define OFprotocol in SDN.

iln

The Open Flow (OF) protocol is a standard in SDN architecture. This

southbound protocol defines the communication between an SDN controller and
m

the network devicelagent such as switch.

Ta

10. What is meant by NFV?

The term "Network Functions Virtualization" (NFV) refers to
the use of virtual
machines in place of physical network appliances. The virtual mnachines are act
as a hypervisor to operate netwörking
software and procedures like load
balancing and'routing by virtual computers.
11. Why the loT systems management is needed?
Need for IoT Systems Management are,
) Automating configuration,
<br>

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Machine-To-Machine (M2M)
137
(G1) Monitoring operational and statistical data,

(i) Improved reliability,

(iv) System wide configurations,

() Multiple system configurations, and

g
(vi) Retrieving and reusing configurations.

in
er
12. Define NETCONE.

e
The Network Configuration Protocol (NETCONF) is network management
a

in
protocol allowing a Network Management System (NMS) to deliver, modify, and

ng
delete configurations of network devices.

I3. Write the advantäges of NETCONE.

fE
To overcome the disadvantages of CLI and SNMP, XML-based NETCONF is
O
introduced, which has the following advantages:
e

NETCONF uses a hierarchical protocol framework that makes it more

g

()
le

suitable for on- demand, automated, and big data requirements of

ol

cloud-based networks.
C

(ii) NETCONF uses XML encoding to define messages and uses the RPC
u

mechanism to modify configuration data. This facilitates configuration data

ad

management and interoperability between devices from diferent vendors.

iln

(ii) NETCONF performs operations on devices based on the YANG model,

reducing the network faults caused by manual configuration errors.
m
Ta

NETCONF provides security mechanisms such as authentication and

authorization to ensures message transmission security.
14. What is meant by YANG?
Yet Another Next Generation (YANG) is a data modeling language used to
model configuration and state data manipulated by the NETCONF protocol.
YANG modules contain the definitions of the configuration data, state data, RPC
calls that can be issued to maintain the format of the notifications.
<br>

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11.38 Embedded Systems and loT Design

15. Differentiate between IoTreference model and reference architecture.

A reference model is a model that describes the main conceptual entities and how
they are related to each other, while the reference architecture aims at describing
the main functional components of a system as well as how the system works.
how the system is deployed, what information the system processes, etc.

g
in
16. Define loT reference architecture.

er
An Io'T reference architecture serves as a foundational blueprint that outlines the

e
essential components and interactions within an loT system. It provides a solid

in
starting point for designing and implementing IoT solutions.

ng
17. What is domain model?
fE
A reference model describes the domain using a number of sub-models. The
domain model captures the basic attributes of the main concepts and the
O
relationship between these concepts. A domain model also serves as a tool for
e

human communication between people working in the domain in question and

g

between people who work across different domains.

le
ol

18. Name the different sub-nodels available in

loT domain model.
C

The sub-models of the IoT domain model are,

u

(i) IoT information model,

ad

(ii) loT functional model,

iln

(ii) IoT communication model, and

m

(iv) IoT trust, security and privacy model.

Ta

19. List the communication models used in

loT.
Some of the communication models
used in loT are,
i) Request & Response model
(ii) Publisher-Subscriber model

(ii) Push-Pull Model, and

(iv) Exclusive pair model.
<br>

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BWochìne-1o-Machine (M2M)

What is MQTT? 11.39)

0.
MQTT stands for Message
Queuing Telemetry
messaging protocol for use Transport.
in cases where It is a lightweight
are
connected to unreliable clients need a
small code footprint and
networks or networks
resources. with limited bandwidth

g
21. What do you mean by XMPP?

in
XMPP is a short
form for Extensible Messaging

er
protocol for streaming Presence Protocol.
XML elements over a It's

e
messages and presence network in order to exchange

in
information in close to real
mostly used by instant messaging time. This protocol is

ng
applications like WhatsApp.
22. What is Modbus?
Modbus or MODBUS is a client/server
fE
data communications protocol
in the
O
application layer of the OSI model.
Modbus is a request-response protocol
implemented using a master-slave relationship.
g e

23. Write the advantages of

Modbus.
le

The advarntages of Modbus are,

ol
C

-) Simple but efficient technical architecture.

Very easy integration with installations.
u

()
ad

(ii) High reliability.

iln

11,7 REVIEW QUESTIONS

m

systemn archtecture.
Mth a neat diagram, explin about M2M
Ta

Discuss about the function of M2M gatewaywitl a neat diagram.

M2M.
Give
the difference between loT and
Networking (SDN) architecture with a neat
Lplain about Software-Defined
diagram.
S. Write of SDN.
the advantages
neat diagram.
6. Discuss about Open Flow(OF) protocol in SDN, witlha
7. NFV architecture.
With neat
diagram, explain about the
management witlh NETCONF-YANG.
Discuss in detailabout the loTsystem
<br>

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Embedded Systems and loT Design

11.40|
of NETCONF.
9. Give the advantages NETCONF with neo,
architecture of
10. Explain in detail about the basic network
diagram.
11. Write a note on YANG.
loTplatforms design mnethodology' with neat diagrams.

g
12. Discuss about the

in
architecture.
13. With neat diagram, eyplain about IoT reference

er
reference model with neat diagram.
14. Explain in detail about the loT

e
15. Discuss about the various IoTprotocols.

in
16. Write a note on

ng
() MQTT.
(i) XMPP
fE
O
ge
le
ol
C
u
ad
iln
m
Ta
<br>

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UNIT -V
Chapter 12

g
in
loT PHYSICAL DEVICES

e er
in
12.1 BASIC BUILDING BLOCKS OF AN IOT DEVICE

ng
4 An loT system comprises of four basic building blocks as,
() Sensors/ Actuators. fE
(ii) Processors,
O
(ii) Gateways, and
e

(iv) Applications.
g
le

Applications
ol
C
u

Gafeways and
ad

Communication
iln
m

Processors
Ta

Sensors and
Actuators

an IoT device
Fig 12.1 Basic building blocks of
0) Sensors:
Sensing
Sensors are the front end of the loT devices. They really mean "things" in loT.
lIt can
be either on-board of the loT device or attached to the device.
<br>

Page 42l of 440

Embedded Systems and loT Design

12.2|
or
can various types of information from the on-board
IoT device collect
attached sensors such as
temperature, humidity, light intensity, etc. The sensed
to the processors or cloud-based
information can be communicated either
servers.

Actuators: Actuation

g
(ii)
of actuators attached to it„that allow

in
IoT devices can have various types
taking actions upon the physical entities in the
vicinity of the device.

er
an IoT device can turn an appliance
For example, a relay switch connected to

e
in
on/off based on the commands sent to the device.

ng
:
(ii) Processors Analysis & Processing
Processors are the brain of the loT system. The main job of the processor is to
fE
process raw data collected by the sensors and transforms them to some
O
meaningful information and knowledge.
Processórs are easily controlled by the applications and their one more
g e

important job is to securing data. They perform encryption and decryption of

le

data. Examples of processors are microcontrollers and microcomputers.

ol

(iv) Gateways: Communication

C

The main task of gateway is to route the processed data that is, to connect one
u

network to another. Gateways are responsible for bridging sensor nodes with
ad

the external Internet or World Wide Web.

Examples of gateways are LAN, WAN, PAN etc.
iln

(v) Applications:
m

Applications provide'a user interface and effective utilization

Ta

of the data
collected. Examples: Smart home apps, Security
system conrol apps and
Industrial control hub apps.

f An IoT device can consists of some modules based on

their functional attributes:
() Sensing/ actuation module,
(i) Analysis & processing module,
(ii) Communication module, and
(iv) Application module.
<br>

Page 422 of 440

oTPhisical Devices
12.3|
Sensing/Actuation Data Analysis
Processing Communication
Module
Any object you Obtained
npow

want to monitor physical signal into Contacting

collected date. Party Vendors
that can be local
or in cloud

g
in
Fig 12.2 IoT device modules

er
12.2 RASPBERRY Pi

e
Raspberry Pi is a series
af low-ost small Single-Board Computers (SBCs) with

in
the physical size
of a credit card developed in the United Kingdom by

ng
the Raspberry Pi Foundation in association
with the Broadcom.
Raspberry Piruns Linz operating system and can perform almost
fE
all tasks that
a normal desktop computer can do.
It also allows interfacing sensors and
O
actuators through the general purpose I/O pins.
e

Raspberry Pi supports Python which is a beginner-friendly programming

g
le

language that is used in schools, web development, scientific research, and in

many other industries.
ol
C

12.3 RASPBERRY PiBOARD

u
ad

40 Pin GPIO Ethernet

iln

port Port
display
m
Ta

External RAM ROM Processor

USB 3.0 12.0
Port Ports
Camera Jack

USB power HDMI Module

port ports AV

Fig 12.3 Raspberry Pi board

<br>

Page 423 of 440

412:4

Fig 12.3 shows the Raspberry Pi board with the

various components/peripherals
that are attached as follows,
on an ARM processor. The latest
(a) Processor & RAM: Raspberry Pi is based
power ARM117617-R
version of Raspberry Pi comes with 700 MHz low
processor and 512 MB SDRAM.

g
a
(b) USB ports: These USB ports are used to connect the peripherals like

in
keyboard or mouse. The two black ports are USB2.0 and the two blue ports

er
are USB3.0.

e
in
(e) Ethernet port: This port connects the Raspberry Pi to a wired network.

ng
Raspberry Pi also has Wi-Fi and Bluetoth built in for wireless connections.
fE
(d) HDMI ports: The HDMI port on Raspberry Pi provides both video and
audio output to the external monitors. The raspberry Pi 4 features two micro
O
HDMI ports, allowing it to drive two separate monitors at the same time.
g e

() Camera module port: This port is used to connect the official Raspberry Pi
le

camera module, which enables it to capture images.

ol

() AV jack: This AV jack allows you to connect speakers or headphones.

C

(g) GPIO pins: This General Purpose Input

/ Output pins are used to connect
u
ad

the electronic components.

(h) USB power port: This USB port powers the Raspberry
iln

Pi. The Raspberry

Pi4 has a USB Type-C port, while older versions
of the Pi have a micro
m

-USB port.
Ta

() ExternalDisplay port: This port is used to connect the official

seven-inch
Raspberry Pi touch display for touch-based
input.
() Micro SD card slot: This card slot is for the micro SD card
that contains the
operating system and files.
<br>

Page 424 of 440

T PhysicalDevices
|12.5
12.4 LINUX ON RASPBERRY Pi

12.4.1 Introduction
.Linux is a powerful, open-source operating system
oomputers, servers,
based on Unix that is used for
mainframes, móbile devices,
and embedded devices.
Raspberry Pi supports various

g
flavors of Linux including:

in
0) Raspbian: Raspbian
Linux is a Debian Wheezy port optimized
for Raspberry

er
Pi. This is the recommended
Linux for Raspberry Pi.

e
fi) Arch: Arch is an Arch Linux port for AMD devices.

in
(i) Pidora: Pidora Linux is a Fedora Linux port optimized

ng
for Raspberry Pi.
(iv) RaspBMC:
An XBMC media-center distribution for Raspberry Pi.
(v) OpenELEC: fE
A fast and user-friendly XBMC media-center distribution.
(vi) RISC OS: A very
fast and compact operating system.
O
e

12.4.2 Installation
g

# Following are the steps for headless installation (without connecting any
le

peripherals) of Raspberry Pi OS:

ol

() Download Raspberry Pi Imager software by clicking on download button

C

https://www.raspberrypi.org/software/
u
ad

(i) After installing Raspberry Pi Imager, open it. The interface of Raspberry Pi
-Imager as shown below:
iln
m
Ta

Raspberry Pi

CHOOSE. SD CARD
CHOOSE OS

SDIALS
<br>

Page 425 of 440

Embedded Systems and loT Design

12.6|
selection
(ii) Click on choose OS and select Raspberry Pi OS (32-bit) from the
box as shown below
Raspberty Pitagerl

Operating System

g
in
Raspberry Pi 0S (32-b)
Apert of Debian with the Rsepbery Pi Oetktop (Recommended)

er
RAS 2921-91-11

e
in
Raspbomy A OS (oche)
Other Raspberry PA OS based images

ng
Other generel purpose 0S
Gther general purpose Operatng Systerre

Madia plryer - Koda 0s

fE
Kodi based Meda parer opeating systers
O
Emulation tnd game 0S
g e
le

(iv) Attach your micro SD card to computer and then click on Choose SD card
ol

button as shown below and select the SD card.

C

erry PiImager y5
u
ad
iln
m

Raspberry Pi
Ta

RASPBERRY PI OS (32-BIT) CHOOSE SD CARD

<br>

Page 426 of 440

Devices
oT Physical 12.7|
Now,click on Write button. Raspberry Pi Imager will download the official
()
Raspberry Pi OS online and then write it on to your SD card.

(vi) After the process of writing Raspberry Pi OS is over, open the SD card in
explorer. Create a file named wpa_ supplicant.conf in the SD card root

g
folder and insert the following text which include the password into that file

in
and save it.

er
Command Function Example

e
cd Change directory cd/home/pi

in
Show file contents cat file.txt

ng
cat
Is List files and folders Is/home/pi
locate Search for a file
fE locate file.txt
O
Isusb List USB devices Isusb

pwd Print name od present working| pwd

e

directory
g
le

mkdir Make directory mkdir/home/pi/new

ol

my Move (rename) file mvsourceFile.txt

destinationFile.txt
C

Remove file Rm file.txt

Im
u

Table 12.1: Raspberry Pifrequently used comnands

ad

12.5 RASPBERRY PI INTERFACES

iln

transfer.
Raspberry Pi has serial, SPI and I2C interfaces for data
m

(i) Serial
Ta

Serial interface on Raspberry Pi has receive (Rx) and transmit (Tx) pins
for

communication with serial peripherals.

TX Rx

Rx Tx Device
RPI

GND GND

Fig 12.4 Sertal interface

<br>

Page 427 of 440

(ii) Serial Peripheral lnterface (SPI)

is a synchronous serial data protocol used for communicating with one or
SPI
one master device and
more peripheral devices. In an SPI connection, there is
one or more peripheral devices. There are five pins on Raspberry Pi for
SPI

interface:
(a) Master. In Slave Out (MISO): Master line for sending data to the peripherals.

g
a
(b) Master Out Slave In (MOSI): Slave line for sending data to master.

in
(c) Serial Clock (SCLK): Clock generated by master to synchronize data

er
transmission.

e
(d) Chip Enable 0(CEO): To enable or disable devices.

in
(e) Chip Enable 1(CE1): To enable ordisable devices.

ng
MOSI
fE
MISO
O
Master SCLK
CE 1
e

CE O
g
le
ol

SCLK
MISO MOSI CE SCLK MISO MOSI
C

Slave 1 Slave 2N
u
ad

Fig 12.5 SPI connection

iln

(iii) Inter-Integrated Circuit (12C)

The 12C interface pins on Raspberry Pi allow you to connect
m

hardware modules.
I2C interface allows synchronous data
transfer with just two pins: SDA (data
Ta

line) and SCL (clock line).

SDA
RP,.

SCL

Device 1 Device 2 Device 3

Fig 12.6 12I interface
<br>

Page 428 of 440

oT Physical Devices
12.9
12.6 PROGRAMMING RASPBERRY PI WITH PYTHON
12.6.1 Controlling LED with Raspberry Pi
.Bo 12.7shows the schematic diagram
of connecting an LED to Raspberry Pi. In
this example, the LED
is connected to GPIO pin 18, but you can connect
the
LED to any other GPIO pin as well.

g
in
er
18 J

e
P

in
W
E

ng
D

Raspberry Pi fE
O
Fig 12.7 Controlling LED with Raspberry Pi
e

on
g

Switching LED /off fromRaspberry Pi console

le

>
ol

Secho 18 /sys/class/gpio/export
C

$cd /sys/class/gpio/gpio18
u

#Set pin 18 direction to out

ad

>
echo out direction
iln

#Turn LED on
m

>
Secho 1 value
Ta

#Turn LED off.

$echo e >
value
every
program for blinking an LED connected to Raspberry Pi
Ihe Python
below. This program uses the RPi.GPIO module to control the
Second is given
program we set pin18 direction to output and then
oPIOon Raspberry Pi. In this
a delay of one second.
write True/False alternatively after
<br>

Page 429 of 440

Embedded Systems and loT Desigr

12.10
LED
program for blinking
Python

GPIO as GPIO
import RPi
Import time
(GPIO.BCM)
GPIO. setmode

g
GPIO.OUT)

in
GPIO. setup (18,

er
While True:
(18, True)

e
GPIO. output

in
time.sleep ( 1 )

ng
GPIO.output (18, False)
time.sleep ( 1) fE
O
12.7 CASE STUDIES
e

12.7.1 Home Automation

g

nos: 10.23-10.25.
Refer Unit-4, Chapter -10, Page
le

12.7.2 Smart Cities

ol

Refer Unit-4, Chapter -10, Page nos: 10.25-10.27.

C
u

12.7.3 Environment
ad

Refer Unit-4, Chapter -10, Page nos: 10.27-10.29.

iln

12.7.4 Agriculture
Refer Unit-4, Chapter -10, Page nos: 10.33
m
Ta

12.8 TWO MARKS QUESTIONS AND ANSWERS

1. Name the basic blocks of anIoT device.
An loT system comprises of four basic building blocks as,
(i) Sensors/ Actuators.
(ii) Processors,

(ii) Gateways, and

(iv) Applications.
<br>

Page 430 of 440

Physical
Devices
oT 12.11|
n modules
List the functional usedin loT device.
AnIoT device can consists off some modules based on their functional.attributes:
Sensing/ actuation ; module,

G) Analysis & processing module,

Communication module, and

g
(i)

in
(iv) Application module.

er
3. What is Raspberry Pi?

e
Raspberry Pi isa series of low-cost small Single-Board Computers (SBCs) with

in
the physical size of a credit card developed in the United Kingdom by

ng
the Raspberry PiFoundation in association with the Broadcom.
a
Raspberry Piruns Linux operating system and can perform almost all tasks that
fE
sensors and actuators
normal desktop computer can do. It also allows interfacing
O
through the general purpose I/O pins.
4.- Name the interfaces used inRaspberry Pi.
g e

The following interfaces are used for data transfer in Raspberry Pi:
le

) Serial interface.
ol

(i) Serial Peripheral Interface (SPI).

C

(12C) interface.
(i) Inter-Integrated Circuit
u

12,9 REVIEW QUESTIONS

ad

blocks of an IoT device.

„
Explain in detail about the basic building
iln

2. Write a note on Raspberry P.

board.
m

neat diagran, explain about Raspberry Pi

Püh
Ta

4 Discuss about Linux on Raspberry P.

neat
t diagrams.
Pi interfaces with
note on the Raspberry
S.
Write a

discuss about the programming of Raspberry Pi using

With an example,
Python.
ajpython, program for
7.
Write

(9 Switching LED ON/OFF.

(i) Blinking LED.

<br>

Page 43lof 440

Model Question Paper -

I
B.E/B.TECH Degree Examinations
B.E.
ELECTRONICS AND COMMUNICATION
ENGINEERING

g
ET3491 EMBEDDED SYSTEMSAND
IOT DESIGN

in
REGULATIONS 2021

er
Time : Three Hours
Maximum: 100

e
Marks

in
Answer ALL questions

ng
PART A - (10 x 2 = 20 marks)
1.
fE
State any fourinbuiltfeatures of 8051 microcontroller.
O
The features of 8051 microcontrollers are as follows:
4KB bytes on-chip program memory (ROM).
e

128 bytes on-chip data memory (RAM).

g
le

Four register banks.

ol

128 user defined software flags.

C

8-bit bdirectional data bus.

u

2. What is the function ofSWAP A?

ad

: SWAPA.
Mnemonic
Swap nibbles within the accumulator.
iln

Function
m

Flags : None
:(D3 –D0) >
(D7-D4)
Ta

Operation

DO
D7 04 03
Lower
Higher nibble
nibble
<br>

Page 432 of 440

Embedded Systems and loT Design

M.Q.2
nibble (D3 - D0) with the upper
This SWAP instruction interchanges the lower
A.

nibble (D7- D4) inside register

Example:
;A=S9H (0101 1001 in binary)
MOV A, #59H
0101 in binary)

g
SWAP.
A
;A=95H (1001

in
3. Define requirement in embedded design.

er
user wants and expects
Requirement is a plain language description of what the

e
tòget. It may be developed in several ways:

in
Talking directly to customers,

ng
Talking to marketing representatives, and
fE
Providing prototypes to the users for comment.
O
4. Defne ARM processor.
An Advanced RISC Machine (ARM) processor is one of family of Central
a
e

Processing Units (CPUs) based on the Reduced Instruction Set Computer (RISC)
g

architecture for computer processors.

le

ARM processors are used in music players, smatphones, wearables, tablets, and
ol

other consumer electronic devices. This needs a very few instruction sets and
C

transistors.
u

5. What is scheduling?
ad

The way that time is allocated between tasks is termed as "scheduling". The
iln

scheduler is the software that determines which task should un next. The logic
of the scheduler and the mechanism that determines when it should be run is the
m

scheduling algorithm.
Ta

6. Define Semaphore.
Semaphores are just riormal variables that are used to coordinate the activities
of multiple processes in a computer system. They are used to enforce mutual
exclusion, avoid race conditions, and implement synchronization between
processes.
7. What is the role of "things" and Internet in IoT?
The Internet of Things (IoT) describes the network of physical objects which a
oolther
considered as "things" that are embedded with sensors, software, and
<br>

Page 433 of 440

Anna University yuestion Papers M.Q3
*

technologies for the purpose of connecting and exchanging data with other
devices and systems over the Internet.

Give the comparisons between IoT and M2M.

Sr.no IoT M2M

Internet-based connectivity. Dircct machine-to-machine

communication.

g
in
Widerange of devices and Specific applications and
2

er
industries. industries.

e
Uses the Internet and ccllular Uses cither an Intemet or non

in
3
networks. internet conncction.

ng
4 Cloud-based storage analytics. Local data proccssing.

Most scalable.
fE
Less scalable.
O
6 Efficient resource utilization. Optimizcd resource utilization.
e

supports point-to-point
g

It
lt supports cloud bascd
7 communication
le

communication.
ol

9. Name the basic blocks anIoT device.

of
C

as,
An loT system comprises of four basic building blocks
u

() Sensors/ Actuators.
ad

(i) Processors,
iln

(ii) Gatevways, and

m

(iv) Applications.
Ta

10. Name the interfaces used in Raspberry Pi.

in Raspberry Pi:
The followving interfaces are used for data transfer

() Serial interface.
(ii) Serial Peripheral Interface (SPI).
(11) Inter-Integrated Circuit (12C)
interface.
<br>

Page 434 of 440

M.Q4 Embedded Systems and loT Design

PART B - (5 x 13= 65 marks)

witlh a neat diagram. (13)
11. (a) Erplain the architecture of 8051 microcontroller
page nos:1.10 -1.12.
Ans: Rcfer unit-1, chapter -1,
[OR]

g
(b)Explain the function of DJNZ instruction. (13)

in
Ans: Refer unit-1, chapter -2, page nos: 2.48 -2.49.

er
12. (a) Discuss in detail about the basic steps involved in embedded system design

e
(13)

in
process.
Ans: Refer unit-2, chapter -4, page nos:4.2 -4.18.

ng
[OR]

(b) Write note on VLIW processors.

fE (13)

Ans: Refer unit-2, chapter -5, page nos: 5.23 –5.26.

O

Explain how multiple processes are handled by preemptive real time

e

13. (a)
g

operating system. (13)

le

Ans: Refer unit-3, chapter -7, page nos: 7.18 - 7.21.

ol

[ORJ
C

(b) Explain in detail about Rate Monotonic Scheduling with an example. (13)

Ans: Refer unit-3, chapter -8, page nos: 8.2 - 8.6.

u
ad

14. (a) Explain about the physical design ofloT. (13)

iln

Ans: Refer unit-4, chapter -10, page nos: 10.4 -10.11.

m

[OR]
Ta

(6) With a neat diagram, explain about M2M system architecture.. (13)
Ans: Refer unit-4, chapter -11, page nos: 11.1– 1l1.3.

15. (a) Explain in detail about the basic building blocks of an IoT device. (13)
Ans: Refer unit-5, chapter -12, page nos: 12.1 – 12.3.

[ORJ
(b) With neat diagram, explain about Raspberry Pi board. (13)

Ans: Refer unit-5, chapter -12, page nos: 12.3 – 12.4.

<br>

Page 435 of 440

Vodel Anna University Question Papers

M.Q.5
PART C (1 x15 = 15 marks)
i6. (a) Explain in detail aboutprogramming input and output.
(15)
Ans: Refer unit-2, chapter -6, page nos: 6.1
-6.7.
[ORJ
(6) Explain with neat sketches about assembly, linking
and loading processes.

g
in
(15)

er
Ans: Refer unit-2, chapter -6, page nos: 6.15
-6.22.

e
in
ng
fE
O
g e
le
ol
C
u
ad
iln
m
Ta
<br>

Page 436 of 440

Embedded Systems and loT Design

M.Q.6
-
Model Question Paper II
B.E/B.TECH Degree Examinations
B. E. ELECTRONICS AND COMMUNICATION ENGINEERING
ET3491 EMBEDDED SYSTEMS AND IOT DESIGN

g
in
REGULATIONS 2021

er
Time :Three Hours Maximum: 100 Marks

e
in
Answer ALL questions
PART A - (10 x 2 =20 marks)

ng
1. Compare microcontrollers and microprocessors in system design.
Sr.NO Microprocessor
fE Microcontroller
The functional blocks of
O
1. The microcontroller includes the
microprocessor are the ALU, functional blocks of a
e

registers, timing and control unit. microprocessor and in addition has

g

a memory, VO interfacing circuit

le

and peripheral devices such as

ADC, DAC, timer etc.
ol

2. It has several instructions to move It has one or two instructions to

C

data between memory and CPU. move data between memory and
u

CPU.
are
ad

3. The microprocessors used for Microcontrollers are used for

designing general purpose digital designing application specific
iln

computing system (or computers). dedicated systems

4. It has one or two bit handling It has many bit handling
m

instructions. instructions.
Ta

5. Memory and I/O devices access Less access time

for built-in
time is more. memory and I/O devices.
2. What is the operation carried out when 8051 executes
the instruction?
MOVCA,@ A+DPTR?

Mnemonic Description Byte Cycle

MOVC A, @A + DPTR Move code byte relative to

DPTR to accumulator
1 2
<br>

Page 437 of 440

Universiy Question Papers

Bodel Anna M.Q.7
Function: Move code byte

Flags:
None
(DPTR))
Operation: (A) E (A) +
This instruction moves a byte of data
that is located in program (code)

g
ROM into register A. This allows us to put
strings of data, such as look

in
up table elements, in the code space
and read them into the CPU.

er
The addressof the desired byte in the code space (on-chip ROM) is

e
in
formed by adding the original value of the accumulator to
the 16-bit

ng
DPTR register.

Example: fE
Let (DPTR) = 1000H, (A) = 8H
O
A+ DPTR 8H + 1000H, the contents of memory location (1008H) = 22H.
e

After execution of this instruction (A) = 22H.

g
le

Why design methodology is important in embedded systemdesign process?

ol

A design methodology is important for the following three reasons:

C

() Optimizing performance,
u

(ii) Automated steps.

ad

(ii) Easy understanding.

iln

* Compare the features of

RISC and CISC architectures. [APRMAY-2023/
m

RISC (Reduced Instruction Set Computing) and CISC (Complex Instruction Set
Computing) are two different approaches to designing the instruction set of a
Ta

CPU(Central Processing Unit).

RISC proçessors are characterized by having a smal, highly optimized

instruction set. This means they have a smaller number of instructions that they
Can execute, but each of these instructions is designed to be very fast and
efficient.
set.
CISC processors are characterized by larger and more complex instruction
a

Ses many memory references process complex instructions. RISC has faster
processing, while CISC has slower processing.
<br>

Page 438 of 440

Embedded Systems and loT Design

M.Q.8|
real tine operating systems?
5. Wy preemptive scheduling is preferred in
scheduling is used in real-time systems where the tasks are usually
Preemptive
time- critical tasks are given higher
configured with different priorities and one at any
A higher priority task
can stop a lower priority time,grab
priorities.

g
and use the CPUuntil it releases it.

in
communication.
Name the two modes used in interprocess

er
6.
other
are two modes through which processes can communicate with each

e
There

in
i) Shared memory, and

ng
(ii) Message passing.
The shared memory region shares a shared
fE
memory between the processes. On

the other hand, the message passing lets

processes exchange information through
O
messages.
e

7. List the applications of loT

g

The applications of loT span a wide range of domains which includes homes,
le

cities, environment, energy systems, retail, logistics, industry, agriculture and

ol

health.
C

8. Define SDN.
u

Software-Defined Networking (SDN) is an approach to networking that uses

ad

software-based controllers or Application Programming Interfaces (APIs) to

iln

communicate with underlying hardware infrastructure and direct traffic on a

network.
m

9. What is Raspberry Pi?

Ta

with
Raspberry Pi is a
low-cost small Single-Board Computers (SBCs)
series of
the physical size of a credit card developed in the United Kingdom 0y
the Raspberry Pi Foundation in association with the Broadcom.
a
Raspberry Pi runs Linux operating system and can perform almost alltasks that
actuators
normal desktop computer can do. It also allows interfacing sensors and
through the general purpose VO pins.
10. List tihe functional modules used in loT device,
can of f some attributes:
An
loT device consists modules based on their functional
<br>

Page 439 of 440

Anna University Question Papers

Model M.Q.9
) Sensing/ actuation module.
(1) Analysis & processing module,

(ii) Communication module, and

(iv) Application
module.

Part-B
(13x 5 = 65 marks)

g
in
JL.() Explain the diferent addressing mode of 8051.
(13)

er
Ans: Refer unit-1, chapter -1, page nos: 1.15 -1.23.

e
[OR]

in
(D)
Explain the various bitmanipulation instructions in
805l with examples.

ng
fE (13)
Ans: Refer unit-1, chapter -2, page nos: 2.38 -2.40.
O
12. (a). Explain about design
of model train controller with neat sketches. (13)
e

Ans: Refer unit-2, chapter -4, page nos: 4.18 -4.30.

g
le

[OR]
(b) With neat sketches, explain in detailabout ARM processor.
ol

(13)
Ans: Refer unit-2, chapter -5, page nos: 5.1 -5.17.
C

13. (4) Discuss in detail about multitasking and multiprocessing.

u

(13)
ad

Ans: Refer unit-3, chapter -7, page nos: 7.9 -7.12.

iln

[OR]
(0) Explain in detail about the OSI model layers, with neat sketches (13)
m

Ans: Refer unit-3, chapter -8, page nos: 8.12 -8.14.

Ta

1. (4) Describe an example of loT service that uses WebsSocket-based

.(13)
communication
Ans: Refer unit-4, chapter -10, page nos: 10.17 -10.18.
[OR]
(6) Explain about Software-Defined Networking (SDN) architecture with a
neat diagram. (13)
-
Ans: Refer unit-4, chapter -11, page nos: 11.4 11.7
<br>

Page 440 of 440

1 Systems and
Embedded. loT Dexign
M.Q.10 nwith neat diagrams.
Raspberry Pi
interfaces (13)
15. (a) Write a note on the
-12. page nos:12.7- 12.8
Ans: Refer unit-5, chapter
[OR)
programming of Raspberry Pi
an example, discuss about the
using
With
(6)
(13)

g
Python.
nos: 12.9- 12.I1

in
chapter -12, page
Ans: Refer unit-S,

er
PART C
(1x 15 =15 marks)

e
in
16. (a) Write a note on

ng
() Supervisor mode.
page nos: 6.S - 6.9.
Ans: Refer unit-2, chapter -6. fE
(i) Exceptions.
O
--
Ans: Refer unit-2, chapter 6, page nos: 6.9 6. 10.
e

(ii) Traps.
g

Ans: Refer unit-2, chapter -6. page nos: 6.11.

le
ol

[OR]
(b) Discuss about program level performance analysis.
C

(45)

Ans: Refer unit-2, chapter -6, page nos: 6.29 - 6.33.

u
ad
iln
m
Ta