signal processing

Practical
‘antipodal’ phase shift modulation. The mathemati-
cal equation for this process is:

 π
Costas loop BPSKN (t ) = cos  2πfc t + DATAN (t )• 
 2
(1)

design where DATAN is restricted to ±1 and N is advanced

at a much lower rate than the frequency of the car-
rier (the cosine function). Shifting the phase of a
carrier (a sinusoid) by 180° is the same mathemati-
cal process as reversing the magnitude of a carrier
Designing a simple and for one symbol and not the other. With identical
inexpensive BPSK Costas loop results, the following amplitude modulation process
can be substituted, interchangeably:
carrier recovery circuit.
BPSKN (t ) = DATAN (t )• cos (2πfc t ) (2)
By Jeff Feigin
Modulation theory

B inary phase shift keying (BPSK), in terms of

noise immunity per unit bandwidth, is one of the
most efficient binary data modulation techniques.
The modulation techniques in Equation 1 and
Equation 2 are referred to as BPSK and double
side-band, suppressed carrier-amplitude modula-
Yet, communications systems designers often tion (DSBSC-AM), respectively, and when the
neglect this option because the design of a BPSK phase shift is restricted to 180° between opposing
demodulator is not as mathematically simple or symbols, there is no difference.
straightforward as frequency shift keying (FSK). As with the DSBSC-AM, the resultant BPSK RF
The prospect of having to apply thorough engineer- spectra are simply the baseband spectra mirrored by
the carrier frequency (see Figures 1, 2). The upper
sideband (the half of the BPSK spectra that exists
above the carrier) is identical to that of the modulat-
ing signal, except shifted up to where the carrier fre-
quency was the DC point in the spectra of the original
signal. The lower sideband (similarly, the part of the
modulated signal that exists below the carrier) con-
tains identical information to the upper sideband,
except its spectra is a mirror image of the carrier.
A mathematically simple demodulation scheme
multiplies the incoming RF signal by a coherent car-
rier (a carrier that is identical in frequency and
phase to the carrier that originally modulated the
BPSK signal). This is an application of the following
trigonometric identity:

1
cos (a)• cos (b) = cos (a + b)+ cos (a − b)
2
(3)

Figure 1. Amplitude spectra of a typical binary data signal. where the product of two cosine functions is the sum
and the difference of the inner term of each. When
ing rigor to the design of a BPSK demodulator can two cosine functions representing periodic time-
be daunting. However, it is unlikely that any such domain waveforms are multiplied together, the result
circuit will perform as well as it could if it were is two new cosines; the sum of the two frequencies
implemented without fully understanding and and the difference. Therefore, when the BPSK signal
parameterizing its behavior. is multiplied by a cosine function identical to the one
Designing and implementing a Costas-loop carrier that modulated it, the original modulating data, plus
recovery circuit and demodulator can be done simply the same BPSK signal at twice the carrier frequency,
and inexpensively using only basic components. are produced. This is mathematically represented by:

BPSK Background
Simple BPSK modulation is the process of shift- BPSKN (t )• cos (2πfc t ) = DATAN (t )•
ing a carrier’s phase by 180° for one data symbol (4)
cos (2πfc t )• cos (2πfc t )
while not shifting it for the other — known as

20 www.rfdesign.com January 2002

 same bandwidth, adds according to a
root mean squared (RMS) relationship
means that the demodulated data will
have an inherent signal-to-noise ratio
(SNR) advantage, or “processing gain”
of 3 dB above that of the BPSK signal.
The narrower the bandwidth of the
data filter, the less noise will appear at
its output. Too narrow of a filter will
limit demodulated data output levels.
For optimum performance, the ratio
between signal and noise should be
maximized. According to Nyquist’s first
criteria, so as not interfere with the
data signal at the center of each symbol
period (the instant where the symbol
value is decided), a square-shaped
“brick wall” filter should have a band-
width of no less than half the symbol
rate. Such a channel filter must have
unity response between DC and a fre-
quency equal to half the symbol rate.
This is the ideal channel filter, because
it removes the most noise possible
Figure 2. Amplitude spectra of a BPSK modulated carrier . without reducing the amplitude of the
desired signal at its sampling instants.
It will produce an output SNR that is
Applying the trigonometric identity 3dB greater than that of the BPSK sig-
from Equation 3, the result becomes: nal. Note that Nyquist specifies alter-
nate filters, vestigial spectrum filter
shapes such as the raised-cosine, which
1  DATAN (t )• cos (0)+ BPSKN (t )• will achieve the same goal.
  (5)
2 cos (2πfc t ) 
Practical BPSK demodulation
The previous mathematical descrip-
tion explains the principle behind
Now, considering that the cosine of coherent BPSK demodulation. Such a
zero is one, the result of this multiplica- Figure 3. Block diagram of an ideal coherent structure is straightforward and lends
tion is the modulating signal plus the demodulator . itself well to understanding the con-
BPSK signal shifted to twice its origi- cepts. However, it is difficult to imple-
nal frequency: Demodulation theory ment this circuit because its perfor-
On demodulation, the upper and mance is poor when non-ideal compo-
1 lower sidebands, which are mirror nents are used. With some modification
 DATAN (t )+ BPSKN (t )• cos (2πfc t ) (6) images, will “fold” onto one another. (see Figure 4), the demodulator circuit
2 The two sidebands of the modulating becomes much more practical. The
signal will coherently add while the requirements placed on the building
A “brick wall” filter (an ideal low- random channel noise (in which the blocks of the structure become far less
pass filter) then isolates the demodulat- upper and lower sidebands are com- demanding to achieve good perfor-
ed data or “low side” product from the pletely independent) will randomly mance.
extraneous high-frequency or “high- add. The fact that the two identical The more realizable BPSK demodula-
side” product: modulation sidebands coherently add tor is based on a practical mixer that is
while the noise, which occupies the allowed to be imperfect. Such a mixer
 1  DATAN (t )+ BPSKN (t )  can be built using common semiconduc-
LPF    tor devices with small current require-
 2 • cos (2πfc t )   (7) ments. Unlike an ideal multiplier, easi-
1 ly implementable mixers are subject to
= DATAN (t ) overloading and high-order non-lineari-
2 ties; undesired radio signals, which
need not exist at even similar frequen-
cies, can mix in a complicated manner
Equivalently, the block diagram for to produce undesired interference that
this mathematical operation is depicted Figure 4. Block diagram of a more easily realized superimposes the desired demodulation
in Figure 3. coherent receiver. product. The solution is to place a chan-

22 www.rfdesign.com January 2002

 bandwidth must be wide enough to
minimize ISI, while narrow enough to
minimize noise. For an alternating
(1,0,1,0,1…) data pattern, a –3 dB cut-
off frequency equal to half the symbol
rate will maximize SNR for the single-
pole RC low-pass. The total SNR degra-
dation, shown by simulation, is about
–1.2 dB for a worst-case alternating
data pattern, but found to be about
–0.6 dB in the case of a random data
pattern. This amount of degradation is
acceptable for simple designs, but bet-
ter filters are recommended if one
wishes to improve the SNR.
Figure 5 is a comparison of the resul-
tant demodulated BPSK data on ideal
and practical demodulation. Ideal
demodulation is that of Figure 3 where
the “perfect filter” is implemented as a
10,001-tap raised cosine finite-impulse
response (FIR) and the practical
demodulator, from Figure 4, uses an
infinite impulse response (IIR) three-
pole Butterworth as the channel filter
Figure 5. Resultant data waveform upon ideal vs. practical filtering in a demodulator. and a one-pole IIR structure as the
data filter. Although the ideal demodu-
nel filter before the mixer to preclude as ual roll-off characteristic than ideal — lator does not faithfully reproduce the
much off-channel energy from reaching about –20 dB per frequency decade. original signal, it does reproduce the
the mixer as possible. The most com- Therefore, it will not be possible to min- entire signal to reach its peak value at
mon inexpensive channel filters are sec- imize intersymbol interference with the data-sampling instant. This is the
only critical point, according to Nyquist
(this is an acausal implementation).
However, the result obtained using the
more practical structure requires more
than one bit time to reach its maximum
Figure 6. A square-then-divide carrier recovery level. This is the ISI degradation para-
circuit. meter. More noise than ideal would
have to be allowed through the demod-
ond- and third-order surface acoustic Figure 7. A costas loop carrier recovery circuit. ulator if one were to attempt to solve
wave (SAW) and ceramic type. this problem with non-ideal filters.
However, neither type exhibits ideal Finally, the carrier must be recov-
rectangular characteristics. allowing extra noise through; its –3 dB ered. Its frequency and phase needs to
cutoff point must be defined such that be exactly reproduced to optimally
Low-pass filter discussions it maximizes the SNR of the data sig- demodulate the BPSK signal. Unless
The low-pass filter, as with the ideal nal. An optimization means that its there exists some connection or infor-
demodulator, is the data filter. Because
the bandpass filter, ahead of the mixer,
removes a great deal of unwanted
noise, the low-pass filter requirements
can be relaxed. While the perfect
demodulator requires that the filter
exhibit no intersymbol interference (a
Nyquist filter), the practical design
may use filters that trade cost, com-
plexity, and size for some degree of
SNR degradation.
For the purpose of a simple imple-
mentation, a three-pole Butterworth is
used as the bandpass filter and a sin-
gle-pole RC is used as the low-pass
data filter for this analysis. The single-
pole low-pass filter has a far more grad- Figure 8. The second-order PLL.

24 www.rfdesign.com January 2002

 tice, controlling the phase offset will be
somewhat complicated and layout-
dependent; the recovered carrier takes
a different path from the demodulator
path, and this creates a time differen-
tial that will result in a phase error.
Also, several filters are required, mak-
ing it difficult to maintain proper phase
over the range operating frequencies.
While the first method is a feed-for-
ward technique, the Costas loop relies
on feedback concepts related to the
PLL. The Costas loop offers an inher-
ent ability to self-correct the phase (and
frequency) of the recovered carrier and,
in the end, its implementation is no
more complicated than the first tech-
nique. Its main disadvantage is
involvement of a loop settling time.

Analyzing the Costas Loop

The mechanism of the Costas loop
carrier recovery is to iterate its inter-
nally generated carrier – the VCO –
into the correct phase and frequency
Figure 9. The output-input phase detection characteristics of multiplier and Costas-type phase detection. based on the principle of coherency and
orthogonality. The low-frequency prod-
uct of a BPSK signal and its coherent
mation path between the carrier that the BPSK modulation causes ±180° carrier is the demodulated information,
was used in modulation and the phase transitions, its second harmonic while the low-frequency component is
demodulator, a carrier recovery circuit will be phase-modulated by an ambigu- completely canceled (there will be no
is required for coherent demodulation. ous ±360°. The second harmonic is an low-frequency component at all) in the
unmodulated carrier at twice the fre- case of a BPSK signal multiplied by its
Carrier recovery quency. Dividing this second harmonic orthogonal carrier (a carrier that is 90°
The two common methods for BPSK of the carrier by two will result in a out of phase with its coherent carrier).
carrier recovery are: 1) squaring the theoretically phase-coherent carrier. The coherent case has already been
BPSK signal then dividing by two and The advantage of the squaring-then- mathematically demonstrated in
2) the 180° Costas loop. The first tech- divide circuit is that it is mathematical- Equations 3 through 7. For the orthogo-
nique relies on the fact that, because ly simple to analyze. However, in prac- nal case, the following trigonometric
identity is presented:

cos (a)• sin (b)

1 (8)
= sin (a − b)+ sin (a + b)
2

representing the coherent BPSK carri-

er at a cosine function and its orthogo-
nal carrier is a sine (or negative sine)
function. The time-domain representa-
tion of this orthogonal multiplication is:

BPSKN (t )• sin (2πfc t ) = DATAN (t )•

(9)
cos (2πfc t )• sin (2πfc t )

Applying the trigonometric identity

from Equation 8, the result becomes:

1  DATAN (t )• sin (0) 

  (10)
2  + DATAN (t )• sin (2πfc t )

Figure 10. VCO tracking behaviors of a Costas loop and PLL with a BPSK reference input.

26 www.rfdesign.com January 2002

 Carriers of interest
The carrier that is to become coherent
when the loop settles is represented as a
cosine function with some phase error.
Therefore, the orthogonal carrier that
leads the coherent carrier by 90° must be
a negative sine function with the same
phase error. Considering the incoming
BPSK signal as a cosine with zero phase
offset relative to time zero, a radial fre-
quency of ωBPSK, (the radial frequency is
2π times the periodic frequency) and the
Costas loop VCO frequency to be ωvco
with a phase error relative to the BPSK
carrier of φphase_error, the resultant product
of the ‘I’ mixer is represented by:

I _represented
Mixer _ Output
by:
= cos (ωvcot + θphase _ error )
(13)
• BPSKN (t ) = cos (ωvcot + θphase _ error )
• DATAN (t )• cos (ωbpskt )

Figure 11. Costas loop simulation with a noise-free, band-limited BPSK input.
For analysis purposes, because the
modulating signal is binary data that
reverses its magnitude, DATAN(t) is
Now, considering that the sine of should be equal to avoid imbalances replaced by ±1 and the identity of
zero is zero, the product of this multi- that will prolong settling time), it com- Equation 3 is applied:
plication is only a “high side” compo- prises a pseudo-integrator (a low-pass
nent and the BPSK signal shifted by filter is related to an integrator). This
90° and to a frequency twice that of allows the circuit to behave in a some- 1 cos ((ωvco − ωbpsk )t + θphase _ error )+ 
±   (14)
what it was. what similar fashion as a second-order 2 cos ((ωvco + ωbpsk )t + ϑphase _ error ) 
 
PLL (see Figure 8).
1
DATAN (t )• sin (2πfc t ) (11)
2
Next, a low-pass filter removes the
high-frequency component, and nothing
remains:

1 
LPF  •  DATAN (t )• sin (2πfc t )  = 0
2 
(12)

The Costas loop is “locked” when it

has adjusted its VCO phase and fre-
quency (the initial conditions are ran-
dom) until the ‘I’ signal is a maximum
and the ‘Q’ signal is zero (in reality, the
locked-loop ‘Q’ signal is close to zero,
but not exactly zero). The third multi-
plier, the phase doubler, produces the
product of the ‘I’ and ‘Q’ signals that
sets the VCO input voltage. LPF3’s pur-
pose is only to remove spurious compo-
nents and LPF1/ LPF2 “high side” leak-
age — it is not meant to significantly
contribute to the loop response and is
often omitted in theoretical Costas
loops block diagrams. LPF1 not only
serves the purpose of a data filter, but
in combination with LPF2 (these two Figure 12. Costas loop simulation with a noisy, band-limited BPSK input.

28 www.rfdesign.com January 2002

LPF1 removes the “high side” compo- Further dissection phase-detector gain serve the purpose
nent and its output; the ‘I’ signal is rep- The phase detector result is then fil- of an example gain. The phase-detec-
resented as: tered by LPF3, which removes extrane- tion response is described by:
ous loop products before being applied
1 (ωvco − ωbpsk )t  to the VCO. Again, this filter is not Costas _ Phase _ Detector =
LPF 1 (t ) = ± cos  (15)
2 + θphase _ error  meant to significantly contribute to the
1 (22)
Costas loop locking response — its V
1
response should be far outside the − sin (2φphase _ difference ) ≈ Kp = 4
Similarly, the ‘Q’ mixer produces the closed-loop response. From the result of 8 r
following product: Equation 21, it can be determined that
the loop will correct itself, both in This result is similar to that of a con-
terms of frequency and phase. ventional multiplier-type phase detec-
Q _ Mixer _ Output And, by modifying Equation 21 to tor whose output, based on a unity
= sin (ωvcot + θphase _ error )• BPSKN (t ) (16) represent absolute phase difference amplitude input, is:
(rather than phases that are relative to
= − sin (ωvcot + θphase _ error )• DATAN (t ) time zero), the phase detection
response is found.
Applying Equation 8, and again substi- It is important to remember that all Conventional _ Phase _ Detector
tuting DATAN(t) with ±1, the resultant three multipliers compose the phase
1 (23)
‘Q’ product is shown as: detector response. The phase doubler V
multiplier is not, by itself, “the phase = cos (φphase _ difference ) ≈ Kp = 2
detector.” In the case where the input r
1 sin ((ωvco − ωbpsk )t + θphase _ error )+  signals have a peak value of unity, the
±   (17)
2 sin ((ωvco + ωbpsk )t + ϑphase _ error )  phase detection response is described by Comparing these two results (see
 
Equation 22. The phase detector gain vs. Figure 9), the Costas loop phase detec-
amplitude dependency is mentioned for tion response is a sine function while
LPF2 removes the “high side” compo- mathematical completeness, but such the multiplier-type phase-detection
nent and its output; the ‘Q’ signal is effects need not be thoroughly quanti- response is a cosine function of the
represented as: fied because realistic “multiplier” phase phase difference. The second-order PLL
detectors will be amplitude invariant. contains a low-pass filter that inte-
1  (ωvco − ωbpsk )t Picking unity for the input and VCO grates (or pseudo-integrates, depending
LPF 2 (t ) = ± sin  (18)
2  + θphase _ error  amplitudes as the parameters for on the type of filter) the error signal

Then, multiplying these two LPF

results together, the phase doubler pro-
duces:

Phase _ doubler (t ) = LPF 1 • LPF 2

 1 
=  ± cos ((ωvco − ωbpsk )t + θphase _ error )
 2  (19)
 1 
•  ± sin ((ωvco − ωbpsk )t + θphase _ error )
 2 

Next, applying Equation 8:

sin (0) 
1 
=−    (ωvco − ωbpsk )t   (20)
8  + sin  2  
   + θphase _ error   

Then simplifying the output of the

phase doubler, the phase detector
result becomes:

Phase _ det ector _ result =

1 (21)
− sin (2 ((ωvco − ωbpsk )t + θphase _ error ))
8 Figure 13. Ten Costas loop settling patterns under identical parameters, but randomized initial condi-
tions and BPSK modulation data.

30 www.rfdesign.com January 2002

from the phase detector. The PLL is Before the loop has settled, whether a period of the phase detection function,
locked when the phase detector result PLL or a Costas loop, the phase detec- where the loop tracking response is
is zero (near zero when the loop filter is tion response must be one that, based identical. Therefore, the Costas loop is
not a true integrator), hence producing on the phase relationship between the able to track a BPSK modulated carrier
a DC constant at the input of the VCO. VCO and the input signal, guides the (loops can also be derived that track
The cosine response of the multiplier VCO to a stable locking phase and fre- higher-order phase modulation
phase detector causes a lock when the quency. If one were to apply a signal schemes such as QPSK). The only catch
phase error is 90° (because the cosine of whose phase is reversing by 180° to an is that the loop-phase doubled response
90° is zero). ordinary PLL, the phase detector result means that it has a 50% chance of gen-
The Costas loop, considering LPF1 would constantly reverse polarity and erating an upside-down carrier. Figure
and LPF2, acts similarly to a second- the phase error magnitude is unlikely to 10 displays simulation results of how a
order loop (the combined effect of LPF1 converge on any stable value (i.e., the Costas loop vs. an ordinary PLL with
and LPF2 adds a second pole to the loop PLL will “track” in opposite directions similar loop parameters would behave
response. The filtered ‘Q’ signal moves for opposite phases — see Figure 9). with a BPSK signal as an input.
just slightly above or below zero and is One might refer to a conventional phase Because LPF3 is not part of the con-
multiplied by the filtered ‘I’ product). Its detector as 360° periodic. This means trol loop (and not the PLL loop filter), it
doubled-sine phase detection response that the phase of the incoming carrier must not have a frequency response
allows two stable locking points: 180° would have to be modulated with 360° that falls within the loop bandwidth.
phase error and zero degrees — both phase transitions (which is no phase Its purpose is only to remove the excess
produce a redundant output that drives transition at all because a sinusoidal noise products produced by the three
the VCO to the correct phase/frequency. carrier has a period of 360°) not to upset previous multipliers and two imperfect
Low-pass filters LPF1/LPF2 must pass the tracking so that the loop error may filters. This filter constitutes an unde-
the modulation (the direct result of fil- converge. sired S-plane pole that would cause the
ters that are too narrow is ISI) as: loop to oscillate, but if its response is
Costas vs. conventional far outside of the loop response, then it
2ωc ! ωLP 1, 2 ≥ 2πBM Conversely, the Costas loop phase- will not cause problems. A rule-of-
(24)
detection response is 180° periodic— thumb recommendation for a safe, out
there are two stable tracking points. of the loop, response would be to set the
where BM, the modulation bandwidth, BPSK modulation shifts the Costas pole of LPF 3 to a minimum of four
is half the data rate. loop input by 180°, which is the next times that of what the closed loop
response would be without this filter.
Exactly how the VCO will settle
depends on the initial phase and fre-
quency of the VCO as it relates to the
incoming BPSK signal, as well as to
the noise characteristics. Although
not apparent, the behavior of any
practical implementation of this cir-
cuit will also be affected by the actual
data that has been modulated. Real-
world communications are usually
band-limited, and the abrupt 180°
phase shifts of BPSK, which the
Costas loop is immune to, would
require an infinite bandwidth.
A more realistic-version BPSK signal
is one in which a bit transition will
cause the carrier amplitude to slowly
sweep from its current phase to the
opposite phase through the zero-ampli-
tude point. The phase-detector contri-
bution to loop gain (although realistic
phase detectors are not perfect multi-
pliers, they still have minimum input
level requirements) is diminished as
the input signal level shrinks.
Every BPSK phase transition will
cause a Costas loop “dropout” at and
near the zero-crossing instant during
the interval between the two discrete
phase levels. If the loop is still in the
Figure 14. Averaged results of simulation comparing Costas loop settle time to the bandwidth of LPF3 locking phase at this point (i.e., when
and VCO gain. the VCO phase does not match that of

32 www.rfdesign.com January 2002

 pole of this filter equals the closed-loop
bandwidth. Based on settling time to a
particular threshold, simulation shows
that setting the pole of lag-filter to half
the DC forward gain results in a quick-
er lock (this is a point where the loop is
slightly under-damped). Therefore,
these same parameters were used in
the Costas loop design as a starting
point for simulation.
The Costas loop phase detector gain,
under unity input conditions, is 1/4 V/r,
as stated in Equation 22, so the VCO
gain is the variable that needs to be
determined. Solving for this parameter,
the unity output VCO should have a
gain of eight times the filter’s pole fre-
quency, in terms of radians per second
for a unity BPSK input for this theoret-
ical circuit containing perfect multipli-
ers as the phase detector:

ω
VCO _ Gaincritically _ damped =
LPF 1 / LPF 2

1
KP (25)
2
Figure 15. Results (interpolated) of simulation of Costas loop vs. ideal BER performance as input SNR
= 8•ω LPF 1 / LPF 2 r / s/v
varies.
Simulation confirms this result for
the carrier), such a “glitch” could modulation data are randomized over the Costas loop (see Figure 14). The
allow a phase slippage and may tem- 10 trials. Realistic Costas loop behavior fastest achievable settle time is one in
porarily allow the loop to track in the is somewhat chaotic for the reasons which the VCO has a gain of eight
wrong direction. mentioned previously, depending on times that of the LPF1/LPF2 pole fre-
Other design issues include the effect when BPSK phase transitions occur quency with the above the phase-
of realistic (non-ideal) filters. Some during the lock phase. detector gain parameters and a ran-
“high side” product will always “leak” dom BPSK input. Using the Costas
through and affect the circuit’s perfor- Design considerations of Costas loops loop parameters presented here,
mance; their respective responses will Similar to PLL design, the Costas where the filter poles and loop gain
not be identical, and there will be ISI (a loop design considerations are noise are all in a fixed relationship to the
1-0-1-0 pattern will not quite produce performance, settling time and a reli- data rate, the regenerated carrier will
180° phase transitions). Further, it is able lock range. As a demodulator, settle in less than three bit times. Of
not realistic to assume that the quadra- noise performance is maximized when course, if the phase detector has some
ture components of the VCO will have a the least amount of noise is allowed in gain or gain-function other than that
perfect 90° offset or that the phase the loop. This is accomplished by set- of Equation 22, Equation 25 should be
detector is an ideal multiplier free from ting the LPF1/ LPF2 response to their appropriately modified.
DC offset. A second-order PLL analysis maximum SNR. This corresponds to a LPF3 must then be specified. This
(where the loop filter is the same as –3 dB cutoff equaling half the data rate filter should have its pole at a low-
LPF1/LPF2) of a carrier will approxi- for a single-pole RC. For loop settling enough frequency that the Costas loop
mate settling characteristics of a purposes, this cutoff is also the mini- will not be too noisy nor be subject to
Costas loop, but a computer simulation mum allowable for the loop filter. carrier phase reversals in the presence
is recommended if the designer needs Additionally, this is an attractive choice of noise (the Costas loop is equally sta-
accurate information. This is because because this filter also serves the pur- ble in both phases) while high enough
“mathematical” building blocks may pose of a data filter. that it doesn’t cause the loop to oscil-
need to be substituted with commonly The loop gain must now be set. late. Setting this pole to four times K
available and inexpensive components. Because LPF1, one of the two identical (or eight times the LPF1/LPF2 pole) is
Figures 11 and 12 show the simulated legs of the loop filter, serves the dual the point in which this filter will negli-
timing waveforms of a Costas loop purpose of also being the data filter and gibly affect on the loop; simulation
operating under noise-free and noisy is required to pass BPSK modulation, a shows this (see Figure 14). To be cau-
conditions, respectively. compromise has been made. According tious, particularly at lower data rates
Figure 13 is a plot of the VCO set- to [2], the critical damping point (the where such a filter can more easily
tling function where the loop parame- point where minimum settling time create problems, a factor of six times K
ters are identical for each run, but the occurs) for a PLL using the same lag- (12 times the LPF1/LPF2 pole) is a bet-
VCO starting phase/frequency and the type filter as LPF1/LPF2, is when the ter choice.

34 www.rfdesign.com January 2002

 The phase detector and VCO gain producing these two signals as well as when a Costas loop is presented with a
control the reliable lock range. With the maintaining their relative phase offset noisy BPSK signal, the ISI created by
above design parameters, this Costas over a range of frequencies. Fortunately, simple data filters produces the most
loop will always reliably lock so long as modern integrated circuits provide an degradation in a simple Costas loop
the VCO can produce the required car- easy-to-use and inexpensive implemen- implementation.
rier frequency. This value, the frequen- tation of an I/Q demodulator. Such ICs
cy range in which the loop may lock, is are also attractive solutions because
determined as follows: they provide additional mixers and References
amplifiers that facilitate the necessary [1] F. M. Gardner, “Phaselock
Range ≈ Gain • Gain building blocks required to build most of Technique,” Wiley, New York, 1979.
VCO phase _ detector VCO (26)
a receiver.
The remaining Costas loop building [2] B.P. Lathi, “Modern Digital and
A more practical limit on how far the blocks are three low-pass filters, the Analog Communications Systems 2nd
carrier recovery circuit may “stretch” “phase doubler” multiplier, and a sin- Edition,” Oxford University Press, New
from its center frequency, however, gle-phase VCO. As previously men- York, 1983.
depends on the width of the band-pass tioned, all filters in this design are sin-
filter shown in Figure 4. Whatever the gle-pole RC (this is for simplicity—the
track and hold ability of the Costas reader may wish to implement other
loop, the carrier recovery range will types of filters for better performance). About the author
never reach beyond that of the interme- One can implement the multiplier Jeffrey Feigin is an RF applica-
diate frequency (IF) filters. and VCO in a number of ways. The use tions engineer at Analog Devices,
Finally, noise performance must be of an integrated op amp-type multiplier where his responsibilities include RF
considered. While demodulated BPSK and a separate VCO are one possibility. IC applications support, systems-
(the data, itself) has an SNR that is A double-balanced switching-type level IC design and reference design.
3 dB greater than that of the modulat- mixer is also a suitable choice, although Previously, Feigin was a design engi-
ed BPSK (not considering ISI degrada- its pseudo-multiplier characteristics neer with Zo&Co., in Skopje,
tion due to non-ideal filtering), noise will somewhat alter the Costas loop Macedonia, where he designed micro-
will cause the Costas loop to introduce characteristics. However, conventional controller and RF circuitry for an
even more noise of its own. PLL logic gate phase detectors (such as urban wireless network. Prior to that,
The reason is that a carrier recovery the XOR) or devices that must be oper- he was employed at Lincom Corp. as
circuit produces a noisy carrier under ated under heavy saturation (which a contract engineer, where he devel-
noisy conditions. Figure 15 displays causes limiting) are unsuitable. Devices oped an OPNET model of a TCP/IP
the bit error rate (BER) performance that limit the Q-channel, but not the I- over Milstar. In addition, while a
of ideal BPSK demodulation (Figure 3) channel are perfectly acceptable. research assistant at the Center for
vs. practical demodulation with ideal Wireless Information Network
carrier recovery (Figure 4) vs. Costas Conclusions Studies, Feigin performed QoS analy-
loop demodulation, with a random The Costas loop, a cousin of the sis of wireless multimedia Internet
data pattern. It is observed that this PLL, is an effective close-loop coher- traffic and protocols. Feigin is a grad-
Costas loop demodulator performs well ent demodulator. Though the PLL and uate of Worcester Polytechnic
at regenerating the carrier until a low Costas loop exhibit similar setting Institute with a B.S.E.E. and
SNR input. At a BER of 10–4 (a value characteristics when configured under M.S.E.E. For further information,
often specified for minimum system identical parameters, the latter can contact Doug Grant
performance), non-ideal filtering con- lock onto a carrier that is reversing in [email protected]
tributes a 1.5 dB degradation while phase; A Costas loop regenerates the
Costas non-ideal carrier recovery caus- “phantom” BPSK carrier. Prediction
es only an additional 0.6 db demodula- of settling behavior may be estimated
tor loss. It is clear that, in the overall by appropriately substituting Costas
scheme, single-pole data filtering caus- loop parameters into a traditional
es more SNR degradation than a PLL analysis, but simulation is
Costas loop. required to accurately estimate its
chaotic behavior.
Implementation discussion Based on simulation, Costas loop
The most difficult structure to imple- settling time is minimized when the
ment in a Costas loop, within reason- closed-loop bandwidth is twice that of
able cost, complexity, and performance, its constituent RC filter, according to a
is a quadrature downconverter. Such a slightly under-damped condition. It
circuit requires that the incoming has also been found that a filter after
BPSK signal be split between two mix- the phase-doubler multiplier (the third
ers (to perform the down-conversion multiplier) is effective in reducing loop
multiplication) and independently mul- noise when its response is kept far
tiplied by two signals of identical fre- outside of the closed-loop bandwidth.
quency, but differ in phase by 90°. Finally, referring to Figure 15,
The greatest difficulty arises from although the recovered carrier is noisy

36 www.rfdesign.com January 2002