MCQ
Write down A,B,C or D in your answer for following MCQs
1. Which of the following is not a legal identifier in Verilog?
A. my_signal B. 2data C. _clk D. data$
2. What is the default value of a reg variable in Verilog?
A. 0 B. 1 C. x (unknown) D. z (high impedance)
3. What is the width of reg [7:0] data[0:3];?
A. 8 B. 4 C. 32 D. 16
4. Which of the following assignments is illegal in Verilog?
A. assign a = b & c; B. reg a = 1’b1;
C. wire a = 1’b0; D. initial a = 1’b1;
5. Which operator has the highest precedence in Verilog?
A. == B. & C. + D. ~
6. What is the result of 4'b1101 << 2?
A. 4'b1100 B. 4'b0100 C. 4'b0000 D. 4'b110100
7. Which Verilog construct supports multiple drivers on a net?
A. reg B. wire C. integer D. time
8. How does the following code execute?
always @(posedge clk)
q <= d;
A. q gets the value of d immediately.
B. q gets the value of d at the next positive clock edge.
C. q stays the same. D. Compile-time error.
9. What is the value of a after the following operation?
a = 4'd15 + 4'd2;
A. 4'b0001 B. 4'b0010 C. 4'b0000 D. 4'b1000
10. Which of the following generates a synthesis error?
A. initial clk = 0; B. assign out = a + b;
C. always @(posedge clk) q <= d; D. delay(5) clk = ~clk;
11. What happens if always block sensitivity list is empty?
A. It runs once. B. It runs continuously.
C. It does not run. D. Compiler error.
12. Which of the following operators is used for blocking assignments?
A. <= B. = C. := D. ==
13. What is the result of the following statement?
assign y = (a === b);
A. y will be true only if a and b are equal.
B. y will be true if a and b are equal, including unknowns.
C. y will always be false. D. y will cause a compile-time error.
14. Which of the following generates a synthesis warning?
A. assign out = a & b; B. reg [7:0] count = 8'd0;
C. always @(posedge clk) count = count + 1; D. #10 a = b;
15. What is the correct way to declare a 3-bit bus in Verilog?
A. reg [0:2] data; B. reg [2:0] data; C. wire data[3]; D. integer data;
Digital
1. What is the minimum number of flip-flops required to construct a MOD-45 counter?
A. 4 B. 5 C. 6 D. 7
2. How many select lines are required for a 128-to-1 multiplexer?
A. 6 B. 7 C. 8 D. 9
3. What is the output of an XOR gate when all inputs are HIGH?
A. HIGH B. LOW C. Undefined D. Depends on the number of inputs
4. Which digital circuit cannot be implemented using only NAND gates?
A. NOT B. AND C. OR D. XOR
5. In a 4-bit ripple counter, the output frequency of the most significant bit (MSB) is:
A. Same as the clock B. Half of the clock
C. One-sixteenth of the clock D. One-eighth of the clock
6. A 4-bit DAC has a reference voltage of 8V. What is the step size of the output voltage?
A. 0.25V B. 0.5V C. 1V D. 2V
7. In a JK flip-flop, if J = 1 and K = 0, what is the next state?
A. Toggle B. Reset C. No Change D. Set
8. Which code among the following is not a weighted code?
A. Binary Coded Decimal (BCD) B. 8421 C. Excess-3 D. Gray
9. How many unique states does a 4-bit Johnson counter have?
A. 8 B. 6 C. 7 D. 10
10. Which of the following is an asynchronous counter?
A. Ring Counter B. Ripple Counter
C. Johnson Counter D. Synchronous Binary Counter
11. Which logic family has the highest speed?
A. TTL B. CMOS C. ECL D. NMOS
12. What is the minimum number of two-input NAND gates required to implement a two-
input OR gate?
A. 1 B. 2 C. 3 D. 4
13. In a 3-bit binary up-counter, after 5 clock pulses, the counter value will be:
A. 101 B. 100 C. 010 D. 001
14. What is the Hamming distance between 101101 and 100100?
A. 1 B. 2 C. 3 D. 4
15. A 4-to-16 line decoder has:
A. 4 input lines and 16 output lines B. 16 input lines and 4 output lines
C. 8 input lines and 8 output lines D. 16 input lines and 4 output lines
1. Write down Verilog Code for below mentioned Block
For following question do write only main logic or reason, do not write long
theory
2. Explain Blocking (=) and non-blocking (,=) assignmements. When are they used ?
(write syntax also)
3. What happens if you declare the same signal as both wire and reg ?
4. How does verilog handle multiple driver on the same wire ?
5. Testbench is synthesizable ? ( Yes or No)
6. Can we define reg in a module without using an always block ?
7. Can we use assign inside an always block ? why or why not ?
8. What happens if a signal is declared but never assigned value in verilog ?
9. Why we write testbench ?
