Introduction

The Timerl module is a 16-bit timer/counterconsisting of two 8-bit registers (TMRIH and
TMRI L) which are readable and writable.The TMRI Register pair (TMRIH:TMRIL) increments
from 0000h to FFFFh and rolls over to 0000h. The Timerl Interrupt,if enabled, is generated on
overflowwhich is latched in the TMRI IF interruptflag bit.This interruptcan be enabled/disabled
by setting/clearingthe TMRI IE interruptenable bit.
TimerI can operate in one of three modes:
• As a synchronoustimer
• As a synchronouscounter
• As an asynchronouscounter
The operating mode is determined by clock select bit, TMRI CS (Tl CON<I >), and the synchro-
nization bit, TfSYNC (Figure 12-1).
In timer mode, Timerl increments every instruction cycle. In counter mode, it increments on
every rising edge of the external clock input on pin Tl CKI.
Timerl can be turned on and off using theTMRION control bit
TimerI also has an internal"reset input', which can be generated by a CCP module.
Timerl has the capabilityto operate off an external crystal. When the Timerl oscillator is enabled
(TI OSCEN is set), the TI OSI and TI OSO pins become inputs.That is, their correspondingTRIS
values are ignored.

Fi ure 12-1:Timerl Block Dia ram

Set TMRIIF flag bit CCP Special Trigger
on Overflow
TMRI S chronized
CLR clod( input
TMRIH TMRIL
TMRION
on/off 1
TIOSO/ TIOSC
1
TICKI Synchronize
Prescaler
Tl OSCEN Fosc/4 y det
Enable Internal
TIOSI Oscillator(l)
Clock SLEEP input
TICKPSI:TICKPSO
TMRICS
Note 1: When the Tl OSCEN bit is cleared, the inverterand feedback resistor are turned
off.This eliminates power drain.
Control Register
Register 12-1 shows the TimerI control register.

Register 12-1: Tl CON: Timerl Control Register

U-O U-O R/W-O R/W-O RIW-O R/W-O R/W-O R/W-O
Tl CKPSI TICKPSO TIOSCEN ffSYNC TMRICS TMRION
bit 7 bit O

bit 7.•6 Unimplemented:Read as 'O'

bit TICKPSI :TICKPSO: Timerl InputClock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 TIOSCEN: Timerl Oscillator Enable bit
1 = Oscillator is enabled
O = Oscillator is shut off.The oscillator inverter and feedback resistor are turned off to
eliminate power drain
bit 2 f¯SYNC: TimerI External Clock Input Synchronization Select bit
When TMRICS 1:
I = Do not synchronize external clock input
O = Synchronize external clock input
When TMRICS = O:
This bit is ignored.Timerl uses the internalclock when TMRICS = O
bit 1 TMRICS: Timerl Clock Source Select bit
I = External clock from pin TIOSO/TI CKI (on the rising edge)
O = Internal clock (FOSC/4)
bit O TMRION: Timerl On bit
1 = Enables Timerl
O= Stops Timerl

Legend
R = Readable bit W = Writablebit
U = Unimplemented bit, read as 'O' - n = Value at POR reset
Timerl Operation in Timer Mode
Timer mode is selected by clearing the TMRICS (Tl bit. In this mode, the input clock
to the timer is Fosc/4. The synchronize controlbit,ffSYNC (Tl has no effect since
the internalclock is always synchronized.
Timerl Operation in Synchronized Counter Mode
Counter mode is selected by setting the TMRI CS bit. In this mode the timer increments on every
rising edge of clock input on the Tl OSI pin when the oscillator enable bit (Tl OSCEN) is set, or
the Tl OSO/TICKI pin when the Tl OSCEN bit is cleared.
If the TfSYNC bit is cleared, then the external clock input is synchronized with internal phase
clocks. The synchronizationis done after the prescaler stage. The prescaler is an asynchronous
ripple-counter.
In this configuration,during SLEEP mode,Timerl will not incrementeven if the external clock is
present, since the synchronization circuit is shut off. The prescaler however will continue to
increment.

External Clock InputTiming for Synchronized Counter Mode

When an external clock input is used for Timerl in synchronized counter mode, it must meet cer-
tain requirements.The external clock requirementis due to internalphase clock (Tosc) synchro-
nization.Also, there is a delay in the actual incrementingof TMRI after synchronization.
When the prescaler is I , the external clock inputis the same as the prescaler output.The syn-
chronizationof TI CKI with the internal phase clocks is accomplished by sampling the prescaler
outputon alternatingTosc clocks of the internal phase clocks. Therefore, it is necessary for the
TICKI pin to be high for at least 2Tosc (and a small RC delay) and low for at least 2Tosc (and a
small RC delay). Refer to parameters45, 46, and 47 in the "Electrical Specifications" section.
When a prescaler otherthan 1:1 is used, the externalclock input is divided by the asynchronous
ripple-counterprescaler so that the prescaler output is symmetrical. In order for the external
clock to meet the sampling requirement,the ripple-countermust be taken into account. There-
fore, it is necessary for the TICKI pin to have a period of at least 4Tosc (and a small RC delay)
divided by the prescaler value. Another requirementon the TI CKI pin high and low time is that
they do not violate the minimumpulse width requirements).Refer to parameters40, 42, 45, 46,
and 47 in the "Electrical Specifications" section.
Timerl Operation in Asynchronous Counter Mode
If (Tl is set, the external clock input is not synchronized. The timer continues
to incrementasynchronously to the internal phase clocks. The timer will continue to run during
SLEEP and can generate an interrupton overflowwhich will wake-up the processor. However,
special precautions in software are needed to read/writethe timer (Subsection 12.5.2 "Reading
and Writing Timerl in Asynchronous Counter Mode"). Since the countercan operate in
sleep, Timerl can be used to implementa true real-time clock.
In asynchronous counter mode, Timerl cannot be used as a time-base for capture or compare
operations.

External Clock Input Timing with Unsynchronized Clock

If the TfSYNC control bit is set, the timer will increment completely asynchronously. The input
clock must meet certain minimumhigh time and low time requirements. Refer to the Device Data
Sheet Electrical Specifications Section, timing parameters 45, 46, and 47.
Reading and WritingTimerl in Asynchronous Counter Mode
Reading TMRIH or TMRIL whilethe timer is running from an external asynchronous clock, will
guarantee a valid read (taken care of in hardware). However, the user should keep in mind that
reading the 16-bit timer in two 8-bit values itself poses certain problems since the timer may
overflow between the reads.
For writes, it is recommended that the user simply stop the timer and write the desired values. A
write contention may occur by writing to the timer registers while the register is incrementing. This
may produce an unpredictablevalue in the timer register.
Reading the 16-bit value requires some care, since two separate reads are required to read the
entire 16-bits. Example 12-1 shows why this may not be a straight forward read of the 16-bit
register.

Example 12-1: Reading 16-bit Register Issues

Sequence 1 Sequence 2
TMRI
Action TMPH:TMPL Action TMPH:TMPL
04FFh READ TMRIL xxxxh READTMRIH xxxxh
0500h Store in TMPL xxFFh Store in TMPH 04xxh
0501h READ TMRIH xxFFh READTMRIL 04xxh
0502h Store in TMPH 05FFh Store in TMPL 0401h