Welcome to the Course

on
ANALOG IC DESIGN-DAY1
 Outline of the Course

• MOS Device Modeling and Simple Current Mirrors with LT Spice

Day-1 (Task-1)

• Design Of Mos transistor Electric VLSI EDA Tool (Task-2)

Day-2

• Design of Source Follower /Inverting Amplifier Design with Electric

Day-3 VLSI EDA Tool (Task-3)

• CMOS Inverter Design with Electric VLSI EDA Tool (Task-4)

Day-4

• Design of Oscillator with Electric VLSI EDA Tool

• B. Design of Differential Amplifier and OPAMP with LT Spice
Day-5
• (Task-5)

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 MOS Device Modeling and Simple
Current Mirrors with LT Spice

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CONTENTS

• Introduction to Analog IC Design

1

• Fundamentals of MOS Device and simple

2 Current Miiror

• Mos Transistor Modeling with LTSpice

3

• Analysis of Current Miiror with LTSpice

4

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 Introduction to Analog IC Design

Fore Noon - Session 1

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Course Objective

This course teaches analog integrated circuit design using CMOS technology.

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Course Objective

This course emphasizes understanding of analog integrated circuit design.

Although simulators are very powerful, the designer must understand the circuit before
using the computer to simulate a circuit.

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 VLSI Design
Integrated circuits are also categorized according to the number of transistors
or other active circuit devices they contain.

➢ An IC is said to use small-scale integration (SSI) if it contains

fewer than 10 transistors.

➢ An IC that contains from 10 to 100 transistors is said to use medium-

scale integration.

➢ A large-scale integration (LSI) IC contains from 100 to 1,000

transistors

➢ And one that uses Very-Large-Scale Integration (VLSI)

contains more than 1,000 transistors.
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 Advantages of CMOS Technology

➢ Low Static power consumption VDD

➢ High input impedance
➢ Rail to Rail Output
➢ Active Pull-up and Pull-down of Output
➢ Simple Design
Vin Vout
➢ High Packing Density
➢ High noise immunity CL
➢ Temperature Stability
➢ Scalability

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 Advantages of CMOS Technology

➢ Low Static power consumption VDD

➢ High input impedance
➢ Rail to Rail Output
➢ Active Pull-up and Pull-down of Output
➢ Simple Design
Vin Vout
➢ High Packing Density
➢ High noise immunity CL
➢ Temperature Stability
➢ Scalability

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 Pentium

1993 : Technology : 0.8 μm (16.7 mm by 17.6 mm)

60–66 MHz
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 Latest CPUs and GPUs
Latest Trends :- Intel : 14 nm AMD : 7nm

➢ Billions of Transistors/ Chip

➢ Frequency of Operation in GHz
➢ Complex Computational Capability

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 Moore’s Law
In 1965, Gordon E. Moore—co-founder of Intel (NASDAQ: INTC)—postulated that
the number of transistors that can be packed into a given unit of space will double
about every two years.

Million-transistor/chip barrier crossed in the late 1980s

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 Year 1999 2001 2004 2008 2011 2014
Tech.Node (nm) 180 130 90 60 40 30

Supply (V) 1.5- 1.2- 0.9- 0.6- 0.5- 0.3-

1.8 1.5 1.2 0.9 0.6 0.6

Wiring levels 6-7 7 8 9 9-10 10

Max. Frequenc y 1.2 2.1 3.5 7.1 11 14.9

(GHz)

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 Die Size Growth

100
Die size (mm)

P6
486 Pentium ® proc
10 386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years

1
1970 1980 1990 2000 2010
Year

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 Frequency

10000
Doubles every
1000 2 years

Frequency (Mhz)
100 P6
Pentium ® proc
486
10 8085 386
8086 286

1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year

Microprocessors frequency doubles every 2 years

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ITRS Prediction of Power Consumption

Semiconductor Industry Assoc., International Technology Roadmap for

Semiconductors, 2002 Update; http://public.itrs.net.
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 Limitations of Static CMOS
Intel’s Prediction of Power Consumption

Online Available: http://computerscience.chemeketa.edu/cs160Reader/Parallel Processing/

MooresLaw.html
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WHAT IS ANALOG DESIGN?

Analysis versus synthesis (design)

Analysis: Given a system, find its properties. The solution is unique.

Design: Given a set of properties, find a system possessing them. The solution is
rarely unique.

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 WHAT IS ANALOG DESIGN?
The Analog IC Design Process

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 What is Electrical Design?
Electrical design is the process of going from the specifications to a circuit solution.
The inputs and outputs of electrical design are:

The electrical design requires active and passive device

electrical models for
- Creating the design
- Verifying the design
- Determining the robustness of the design
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 Steps in Electrical Design
1) Selection of a solution
- Examine previous designs
- Select a solution that is simple
2) Investigate the solution
- Analyze the performance (without a computer)
- Determine the strengths and weaknesses of the solution
3) Modification of the solution
- Use the key principles, concepts and techniques to implement
- Evaluate the modifications through analysis (still no computers)
4) Verification of the solution
- Use a simulator with precise models and verify the
solution
- Large disagreements with the hand analysis and
computer verification should be carefully examined. 22
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 What is Physical Design?
Physical design is the process of representing the electrical design in a
layout consisting of many distinct geometrical rectangles at various
levels. The layout is then used to create the actual, three-dimensional
integrated circuit through a process called fabrication.

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What is the Layout Process?
1) Inputs are the W/L values and the schematic (generally from schematic entry used for
simulation).
2) A CAD tool is used to enter the various geometries. The designer must enter the
location, shape, and level of the particular geometry.
3) During the layout, the designer must obey a set of rules called design rules. These rules are
for the purpose of ensuring the robustness and reliability of the technology.
4) Once the layout is complete, then a process called layout versus schematic (LVS) is applied
to determine if the physical layout represents the electrical schematic.
5) The next step is now that the physical dimensions of the design are known, the
parasitics can be extracted. These parasitics primarily include:
a) Capacitance from a conductor to ground
b) Capacitance between conductors
c) Bulk resistance
6) The extracted parasitics are entered into the simulated database and the design is re-
simulated to insure that the parasitics will not cause the design to fail.

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 Packaging
Packaging of the integrated circuit is an important part of the physical design process. The
function of packaging is:
1)Protect the integrated circuit
2)Power the integrated circuit
3)Cool the integrated circuit
4)Provide the electrical and mechanical connection between the integrated circuit
U and the outside world.
Packaging steps:

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What is Test Design ?

Test design is the process of coordinating, planning and implementing the

measurement of the analog integrated circuit performance.

Objective: To compare the experimental performance with the specifications and/or

simulation results.

Types of tests:
• Functional – verification of the nominal specifications
• Parametric – verification of the characteristics to within a specified tolerance
• Static – verification of the static (AC and DC) characteristics of a circuit or system
• Dynamic – verification of the dynamic (transient) characteristics of a circuit or system

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Analog Integrated Circuit Design Skillset
Characteristics of Analog Integrated Circuit Design
• Done at the circuits level
• Complexity is high
• Continues to provide challenges as technology evolves
• Demands a strong understanding of the principles, concepts and techniques
• Good designers generally have a good physics background
• Must be able to make appropriate simplifications and assumptions
• Requires a good grasp of both modeling and technology
• Have a wide range of skills - breadth (analog only is rare)
• Be able to learn from failure
• Be able to use simulation correctly

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 Understanding Technology
Understanding technology helps the analog IC designer to know the limits of the
technology and the influence of the technology on the design.

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Understanding Modeling
Modeling:
Modeling is the process by which the electrical properties of an electronic circuit or system are
represented by means of mathematical equations, circuit representations, graphs or tables.
Models permit the predicting or verification of the performance of an electronic circuit or system.

Examples:
Ohm’s law, the large signal model of a MOSFET, the I-V curves of a diode, etc.
Goal:
Models that are simple and allow the designer to understand the circuit performance.
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 Complexity in Analog Design

Analog design is normally done in a non-hierarchical manner and makes

little use of repeated blocks. As a consequence, analog design can become
quite complex and challenging.

How do you handle the complexity?

1) Use as much hierarchy as possible.
2) Use appropriate organization
techniques.
3) Document the design in an efficient
manner.
4) Make use of assumptions and
simplifications.
5) Use simulators appropriately.

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Where Is Analog Ic Design Today?

Analog IC Design has Reached Maturity

There are established fields of application:
• Digital-analog and analog-digital conversion
• Disk drive controllers
• Modems - filters
• Bandgap reference
• Analog phase lock loops
• DC-DC conversion
• Buffers
• Codecs
• Etc.
Existing philosophy regarding analog circuits:
“If it can be done economically by digital, don’t use analog.”
Consequently:
Analog finds applications where speed, area, or power have advantages over a
digital approach.
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 Analog IC Design Challenges
Technology:
• Digital circuits have scaled well with technology
• Analog does not benefit as much from smaller features
- Speed increases
- Gain decreases
- Matching decreases
- Nonlinearity increases
- New issues appear such as gate current leakage
Analog Circuit Challenges:
• Trade offs are necessary between linearity, speed, precision and power

• As analog is combined with more digital, substrate interference will become worse

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 Digitally Assisted Analog Circuits

Use digital circuits which work better at scaled technologies to improve analog circuits
that do not necessarily improve with technology scaling.
Principles and Techniques:
• Open-loop vs. closed loop
Open loop is less accurate but smaller  Faster, less power
- Closed-loop is more accurate but larger  Slower, more power

- Increase of accuracy  Smaller devices, more speed

•Calibration
-Accuracy increases  Increased resolution with same area
•Dynamic Element Matching
-Enhancement of component precision
•Doubly correlated sampling
-Reduction of dc influences (noise, offset)  Smaller devices, more
speed Etc.

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A New Paradigm for IC Design?
• Today’s Paradigm
– $ invested up front
– No guarantee that product will be profitable
– Requires a lot of overhead, support, and time

• New Paradigm (shaped by the internet)

– No $ invested until the product is sold

– The need for an IC is generated by potential consumer
– Opens the design space to a wide range of “designers”
– Massive markets not needed to make a product and profit
– Minimizes the time and overhead required to develop a product
– Design equivalent of crowd funding ➞ “crowd designing”
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What is the future of Analog IC Design

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 SUMMARY

• Successful analog IC design proceeds with understanding the circuit before simulation.
• Analog IC design consists of three major steps:
1) Electrical design Topology, W/L values, component values and dc currents
2) Physical design (Layout)
3) Test design (Testing)

• Analog designers must be flexible and have a skill set that allows one to simplify and
understand a complex problem

• Analog IC design has reached maturity and is here to stay.

• The appropriate philosophy is “If it can be done economically by digital, don’t use analog”.
• As a result of the above, analog finds applications where speed, area, or power result in
advantages over a digital approach.
•Deep-submicron technologies will offer exciting challenges to the creativity of the
analog designer.
•Paradigm for IC design might be changing which would influence analog IC design.

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GETTING STARTED WITH LTspice XVII

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 SPICE

• Simulation Program with Integrated

Circuit Emphasis
• Developed in 1973 by Laurence Nagel at
UC Berkeley’s Electronics Research
Laboratory
• Dependent on user defined device
models

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 LTspice
• Developed in 1998 by Mike Engelhardt at Linear
Technology Corporation
• GUI, simulator, and schematic -> netlist for SPICE
• FREE and comes with tons of models

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How Do I Get LTspice and Documentation?

❖ Go to http://www.analog.com/LTspice
❖ Left-Click on Download LTspice for Windows 7, 8 and 10
❖ Follow the instructions to install
❖ LTspice is a standalone application that runs on your computer

❖ At this link, you will also find:

✓ LTspice Download Links
✓ LTspice Demo Circuits
✓ LTspice Documentation
✓ LTspice Technical Articles & Videos
✓ SPICE Models

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 Why Use LTspice?

 2500+ macromodels of Legacy Linear Technology

products
• Stable SPICE circuit simulation with:  1500+ power products
• Unlimited number of nodes  300+ Legacy ADI Products (power and amps)
• Schematic/symbol editor
• Waveform viewer
• Library of passive devices
• Steady state detection
• Turn on transient SPICE = Simulation Program with
• Step response Integrated Circuit Emphasis
• Efficiency / power computations
• Advanced analysis and simulation options

• Outperforms or as powerful as pay-for tools

• In other words LTspice is free!
• Automatically builds syntax for common tasks

LTspice is also a great schematic capture / BOM tool

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 Using the Schematic Editor in LTspice
Start With a New Schematic
• To open up a blank schematic screen select “File” Menu and “New Schematic”

Blank schematic
a.k.a.
MasterPiece in progress

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Toolbar and Keyboard Shortcuts

Place Circuit Element [F2]

Zoom In Place Diode [D]
Pan Place Inductor [L]
Zoom Out Place Capacitor [C]
Autoscale Place Resistor [R]
Label Node [F4]
Place Ground [G]
Draw Wire [F3]

Move [F7]
Drag [F8]
Undo [F9]
Delete [Del] Redo [Shift+F9]
Duplicate [Ctrl+C] Rotate [Ctrl+R]
Paste b/t Schematics [Ctrl+V] Mirror [Ctrl+E]
Find [Ctrl+F] Place Comment/text [T]
Place SPICE directive [S]

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How to Wire up a Simple RC Circuit
• Step 1: Open up a blank schematic screen
• Select “File” Menu and “New Schematic”

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 Le
6
.c1
Adding Components
t0
1
u
rSe
p
ri
4
n
g2
0
2
0 Devices besides basic resistors, capacitors, and
inductors are found from this button

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Editing Components

Just right click the

component

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Editing Components

But what
about this?
This is the basic voltage source menu.
Use this for DC sources such as power
supplies or bias voltages.

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Editing Components

Voltage sources can produce many test signals.

PWL can be used to construct any signal.

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 Le
6
.c1
t0
Selecting Device Model
1
u
rSe
p
ri
4
n
g2
0
2 There are no “ideal” BJT’s, MOSFET’s, etc. You can select a model
0 (provided by LTspice), download models, or create your own.

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How to Wire up a Simple RC Circuit

• Step 2: Add the passives and grounds

• Using the toolbar, select Resistor, Capacitor and Ground. Place these symbols on the schematic as shown below. Use Ctrl+R to rotate
before placement.

Select and place

res, cap & GND, or
use keyboard keys
R, C, and G
Tip: Ctrl+R to rotate
before placement

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How to Wire up a Simple RC Circuit

• Step 3: Add the voltage source

• Select “Edit” Menu and “Component”. From the component window, start typing “voltage” in the dialog box, and click
“OK”

2. Type
“Voltage”

3. Click “OK”

1. Edit menu, select

“Component”

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How to Wire up a Simple RC Circuit (cont.)

• Step 4: Wire up the circuit

• Using the toolbar, select Wire, or, press F3

1. Select
“Wire” button

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How to Wire up a Simple RC Circuit (cont.)

• Step 4: Wire up the circuit (cont.)

Left-Click ground “Pull” wire through the resistor “Pull” wire down through the capacitor
“Pull” wire up through the source Left-Click here to anchor Left-Click here to anchor & finish
Left-Click here to anchor

Hint: Press the ESC key at any time to clean up the schematic

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How to Wire up a Simple RC Circuit (cont.)

• Step 5: Add net labels

• Using the toolbar, select Label Net (or press F4). Label the input/output nodes as shown below

1. Select “Label
Net”
2. Enter net
name

3. Place on wire

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How to Wire up a Simple RC Circuit (cont.)

• Step 6a: Component values

• Right-Click on each component symbol to change its value as shown below

Right-click on
symbol

Or Right-click on
value

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Using Labels to Specify Units for Component Attributes

• M = m = milli = 10-3 • K = k = kilo = 103

• U = u = micro = 10-6 • MEG = meg = 106
• N = n = nano = 10-9 • G = g = giga = 109
• P = p = pico = 10-12 • T = t = tera = 1012
• F = f = femto = 10-15

Hints
 Use MEG (or meg) to specify 106, not M
 Enter 1 for 1 Farad, not 1F

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Editing Components

• Right-Click on the component to edit attributes

► You can also edit the visible attribute and label by pointing at the text with the mouse and then right-
clicking
► Mouse cursor will turn into a text caret

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Component Database

• Resistors, capacitors, inductors, diodes, Bipolar transistors, MOSFET transistors, JFET transistors,
Independent voltage and current sources
• You can access a database of known devices

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How to Wire up a Simple RC Circuit (cont.)

• Step 6b: Source parameters

• Right-Click on the voltage source and enter the parameters shown below under the “Advanced” tab.

Click
“Advanced”

Right-click source

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How to Wire up a Simple RC Circuit (cont.)

• Step 6b: Source parameters

• Select the PULSE button and enter the parameters shown below:

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Running the RC Circuit Simulation – Transient Analysis

• With the RC circuit in the active window, click on the RUN button on the toolbar
• The Edit Simulation Command window will appear. Set the Stop Time to 60m and click OK.
• Using the mouse, click on the IN node and OUT node to display the input and output voltage waveforms.

Run
Click here for
output
waveform

RCFilterTimeDomain.asc

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Running the RC Circuit Simulation – Transient Analysis

• To add a measurement cursor to the waveform window, left+click the mouse on the waveform name.

► To add a second Click to display

measurement cursor measurement
(paired cursors), just cursor. Click
and drag cursor
left+click on the waveform
position.
name again.

RCFilterTimeDomain.asc

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Running the RC Circuit Simulation – Transient Analysis

• To display the current in the resistor, just left+click on the resistor.

Click here for

resistor current
waveform

RCFilterTimeDomain.asc

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Running the RC Circuit Simulation – Transient Analysis

• Split the plot pane by selecting “Add Plot Pane” under the Plot Settings pull-down menu.
• Drag and drop the I(R1) waveform title into the new plot pane

RCFilterTimeDomain.asc
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Summary of the Waveform Viewer

• LTspice integrated waveform viewer:

• Plot the voltage on any wire by a simple point and click

Voltage probe cursor

• Plot the current through any component by clicking
on the body of the component

Current probe cursor

• When using the current probe, the convention of
positive current is from netlist pin #1 to pin #2.
• Add a waveform measurement cursor by left+clicking on the
waveform name. Add a second measurement cursor by
left+clicking on the waveform name again.

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AC Analysis Overview

• Performs small signal AC analysis linearized about the DC operating point

• Useful for analysis of filters, networks, stability analysis, and noise considerations

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Simulating AC Analysis – RC Filter

• Single pole filter using RC network

• Syntax: .ac <oct, dec, lin> <Nsteps> <StartFreq> <EndFreq>
• Example: RC network and .ac dec 100 .01 1MEG

-3dB point:
1/(2*pi*R*C) = 159Hz

AC amplitude of 1 sets
magnitude to 0dB

Right-click on .tran
command and select
“AC Analysis”

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Simulating AC Analysis – RC Filter

• Right-click on the .tran command

• Select AC Analysis tab
• Enter the following parameters:

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Simulating AC Analysis – RC Result

Click here for

Bode plot

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Simulating AC Analysis – Active Filter

• Single pole active filter using an opamp (AD8672)

Click here for

Bode plot

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 Defining a Component Value as a Variable (Using Parameters)

• The .param SPICE directive allows the creation of user-defined variables.

• To define a component value as a variable, replace the component value with a variable name enclosed in
curly braces. Example: {X}

Right+click to
change the
component
value to {X}

Add the
.param SPICE
directive (press
S on the keyboard)

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Defining a Component Value as a Variable (Using Parameters)

• The simulation results are the same as when the component value was defined as 10K.

Click here for

Bode plot

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 Defining a Component Value as a Variable (Stepping Parameters)

• The .STEP command can be used to vary a component variable over a range of values to plot a family of
curves.
• This is very powerful and can be used for sensitivity and Monte Carlo Analysis.

Right+click to
change SPICE
directive to the
.step command

RCFilterACAnalysis_Step Command.asc

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 Advantages of Labeling

• Replaces the default SPICE node names with node names and waveform titles that are easy to understand and
remember
• Allows LTspice circuit nodes to match those on your production schematic, i.e. “TP15”

Without With

LTC3412A_DC_Load.asc

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Labeling - Trick

• Highlight net from waveform viewer

• Alt-Left-Click on the label in the waveform viewer (i.e. V(n006)) and it will now highlight that particular net on the
schematic. You can also use the search function ( )

Alt-Left-
Click

Net
Highlighted

LTC3412A_DC_Load.asc

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 MOS Device Models for Analog Design

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INTRODUCTION

• Currently, most of the signal processing is computed with digital circuits.

• Since the 80s billions of transistors integrated on a single chip are able to perform
billions of operations per second.
• Advantages of digital signal processing:
• Why do we need then mixed-signal
• Design simplicity. circuits?
• Automatic design tools available. • Signal processing with sensors:
• Higher noise robustness.
• Compact circuits.
• Disadvantages of digital signal processing:
• Limited resolution.
• Discrete operation.

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 INTRODUCTION
• Why do we need then mixed-signal circuits?
• Digital control of actuators.

What is needed?

Digital signals from … and analog signals to

user… DAC control speed, acceleration,
temperature…

• Digital communications: DAC for transmitter and ADC for receiver.

• Radioreceivers:

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 INTRODUCTION
• Why do we use MOSFET design
nodes? 1928
• Patented by Liliendeld in the 30’s. Field effect control device
• They have been intensively used since the 60’s. proposed by J. Lilienfield
• CMOS-based digital design: only dynamic power consumption
• (logic transitions) and less area. Lower manufacturing costs and higher
scalability.
• CMOS-based analog design: high speed and less noisy than BJT nodes.
Lower intrinsic gain, but higher input impedance. High scalability has
enabled operating frequencies similar to BJT-based architectures.
• In the narrowest nodes the parasitic resistances and capacitors become
more limiting.

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Historcal Facts About MOSFET
• The surface controlled transistor has a very bad drift
• problem. We have been fooling with this problem for a
• long time and have no hope of an early solution. In fact,
• I am not sure I have a strong hope of an eventual solution.
• Gordon Moore
• Fairchild Progress Report, February 15, 1962

• Although the MOS devices are still at the research stage

• because of fabrication problems and incomplete physical
• understanding, their impact on microelectronics is
RCA Announcement of MOS
expected to be significant.
transistor (February 11, 1963)
• George Warfield, RCA
• Electron Device Meeting, October, 1962
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N-MOSFET Structure

• n-type MOS (NMOS) has n-doped source (S) and drain

(D) on p-type substrate (“bulk” or “body”).
• S/D junctions “side-diffuse” during fabrication so that
effective length Leff = Ldrawn − 2LD .
• Typical values are Leff ≈ 10 nm and tox ≈ 15 Å.
• The S terminal provides charge carriers and the D
terminal collects them.
• As voltages at the three terminals changes, the source
and drain may exchange roles.
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Structure of Depletion Mode MOSFET & Enhancement Mode MOSFET

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MOSFET Structure

• PMOS is obtained by inverting all of the doping

types (including the substrate).

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Complementary MOSFET Structure

• In complementary MOS (CMOS) technologies both NMOS (NFET) and

PMOS (PFET) are needed and fabricated on the same wafer.
• In today’s CMOS, the PMOS is fabricated in an n-well, where the n-well
is tied to the most positive supply voltage.

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MOS Symbols

• Substrate is denoted by “B” (bulk).

• PMOS source is positioned on top since it has a higher potential than the gate.
• Most circuits have NMOS and PMOS bulk tied to ground and VDD, respectively, so
we tend to omit the connections (b,c).
• Digital circuits tend to incorporate “switch” symbols (c).

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Threshold Voltage

• As VG increases from zero, holes in p-substrate

are repelled leaving negative ions behind to form
a depletion region.
• There are no charge carriers, so no current flow.

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Threshold Voltage

• Increasing VG further increases the width of the

depletion region and the potential at the oxide-
silicon interface.
• Structure resembles voltage divider consisting of
gate-oxide capacitor and depletion region
capacitor in series.

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Threshold Voltage

• When interface potential reaches sufficiently

positive value, electrons flow from the source to
the interface and eventually to the drain.
• This creates a channel of charge carriers
(inversion layer) beneath the gate oxide.
• The value of VG at which the inversion layer
occurs is the threshold voltage (VTH).

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Threshold Voltage

• Where
- ΦMS is the difference between the work functions of the
polysilicon gate and the silicon substrate.
- k is Boltzmann’s constant.
- q is the electron charge.
- Nsub is the doping density of the substrate.
- ni is the density of electrons in undoped silicon.
- Qdep is the charge in the depletion region.
- Cox is the gate oxide capacitance per unit area.
- єsi is the dielectric constant of silicon.
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Threshold Voltage

• In practice, threshold voltage is adjusted by

implanting dopants into the channel area during
device fabrication.
• For NMOS, adding a thin sheet of p+ increases
the gate voltage necessary to deplete the region.

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Threshold Voltage

• Turn-on phenomena in PMOS is similar to that of

NMOS but with all polarities reversed.
• If the gate-source voltage becomes sufficiently
negative, an inversion layer consisting of holes is
formed at the oxide-silicon interface, providing a
conduction path between source and drain.
• PMOS threshold voltage is negative.

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 The Threshold Voltage

1. The work function difference TGC between the gate

and the channel reflects the built-in potential of the MOS
system, which consists of the
p-type substrate, the thin silicon dioxide layer, and the
gate electrode. Depending on the gate material, the work
function difference is
∅𝐺𝐶 = ∅ 𝐹_𝑆𝑢𝑏𝑠𝑡𝑟𝑎𝑡𝑒 - ∅ 𝐹 𝑚𝑒𝑡𝑎𝑙 𝐹𝑜𝑟 𝑀𝑎𝑡𝑟𝑎𝑙 𝐺𝑎𝑡𝑒

∅𝐺𝐶 = ∅ 𝐹_𝑆𝑢𝑏𝑠𝑡𝑟𝑎𝑡𝑒 - ∅ 𝐹 𝑃𝑜𝑙𝑦𝑠𝑖𝑙𝑖𝑐𝑜𝑛 𝐹𝑜𝑟𝑃𝑜𝑙𝑦𝑠𝑖𝑙𝑖𝑐𝑜𝑛 𝐺𝑎𝑡𝑒

2. The externally applied gate voltage must be changed to
achieve surface inversion, i.e., to change the surface
potential by - 2 ∅ F. This will be the second component of
the threshold voltage.

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 The Threshold Voltage

3. Another component of the applied gate voltage is necessary

to offset the depletion region charge, which is due to the fixed
acceptor ions located in the depletion region near the surface.

4. There always exists a fixed positive charge density Qox at

the interface between the gate oxide and the silicon
substrate, due to impurities and/or lattice imperfections at
the interface. The gate voltage component that is necessary
to offset this positive charge at the interface is - QOX/Cox.

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 The Threshold Voltage

The body effect occurs in a MOSFET when the source is not tied to the substrate
(which is always connected to the most negative power supply in the integrated circuit
for n-channel devices and to the most positive for p-channel devices). The substrate
then acts as a “second gate” or a back-gate for the MOSFET

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MOSFET Current

Linear Region- Small VDS

𝑉𝑜𝑣 = 𝑉𝐺𝑆 - 𝑉𝑇

𝑄
𝐶𝑜𝑥 𝑊𝐿 =
𝑉𝑜𝑣
𝑄
𝐶ℎ𝑎𝑟𝑔𝑒 𝑝𝑒𝑟 𝑢𝑛𝑖𝑡 𝐿𝑒𝑛𝑔𝑡ℎ = =
𝐶𝑜𝑥𝑊𝑉 𝑜𝑣
𝐿
𝑉𝐷𝑆
𝐸𝑙𝑒𝑐𝑡𝑟𝑖𝑐 𝐹𝑖𝑒𝑙𝑑 𝑖𝑛 𝐶ℎ𝑎𝑛𝑛𝑒𝑙 =
𝐿
𝑉𝐷𝑆 µ𝑛
𝑉𝑒𝑙𝑜𝑐𝑖𝑡𝑦 𝑜𝑓 𝐶ℎ𝑎𝑟𝑔𝑒 𝑖𝑛 𝐶ℎ𝑎𝑛𝑛𝑒𝑙(𝑣) = µ 𝑛𝐸 =
𝐿
𝑄 𝑉 𝐷 𝑆 µ𝑛
𝐶𝑢𝑟𝑟𝑒𝑛𝑡 𝑖𝑛 𝐶ℎ𝑎𝑛𝑛𝑒𝑙 (𝐼𝐷 ) = 𝑣 ∗ = * 𝐶𝑜𝑥 𝑊𝑉𝑜𝑣
𝐿 𝐿

µ𝑛𝐶𝑜𝑥𝑊(𝑉𝐺𝑆 − 𝑉𝑇)𝑉𝐷𝑆
𝐼𝐷 =
𝐿

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 MOSFET Current

Linear Region- Small VDS

𝑉𝑜𝑣

µ𝑛𝐶𝑜𝑥𝑊(𝑉𝐺𝑆 − 𝑉𝑇)𝑉𝐷𝑆
𝐼𝐷 =
𝐿
µ𝑛𝐶𝑜𝑥𝑊𝑉 𝑜𝑣
𝑇𝑟𝑎𝑛𝑠𝑐𝑜𝑛𝑑𝑢𝑐𝑡𝑎𝑛𝑐𝑒 𝑜𝑓 𝐶ℎ𝑎𝑛𝑛𝑒𝑙 𝑔 𝐷𝑆 =
𝐿
𝑘𝑛′ 𝑊𝑉𝑜𝑣 𝑉𝐷𝑆
𝑃𝑟𝑜𝑐𝑒𝑠𝑠 𝑡𝑟𝑎𝑛𝑠𝑐𝑜𝑛𝑑𝑢𝑐𝑡𝑎𝑛𝑐𝑒 𝑝𝑎𝑟𝑎𝑚𝑒𝑡𝑒𝑟 𝑘 𝑛′ = µ 𝑛𝐶 𝑜𝑥 𝐼𝐷 =
𝐿

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MOSFET Current

Linear Region as VDS is Increased

Charge in the tapered channel is proportional to the

channel cross-sectional area

𝑘 ′ 𝑊(𝑉 − 𝑉𝐷𝑆 )𝑉
𝐼𝐷 =
𝑛 𝑜𝑣 2 𝐷𝑆
𝐿

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MOSFET Current

Saturation Region

𝑉𝐷𝑆 = 𝑉𝑜𝑣 = 𝑉𝐺𝑆 - 𝑉𝑇

𝑘 ′ 𝑊(𝑉 − 𝑉𝐷𝑆 )𝑉
𝐼𝐷 =
𝑛 𝑜𝑣 2 𝐷𝑆
𝐿
𝑘𝑛′ 𝑊(𝑉𝐺𝑆 − 𝑉𝑇 )2
𝐼𝐷 =
2𝐿

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MOSFET Current

𝑘𝑛′ 𝑊(𝑉𝐺𝑆 − 𝑉𝑇 )2
𝐼𝐷 =
2𝐿

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 Saturation

• For v DS  vGS – V t
VGS
0 1 2 3 4 5
20

IDS (µA)
W=1 micron
10
L=10 microns
Vt0= 1 volt
Kn=2e-5 (A/v 2)

id
G D

+ 2
• Large signal model in saturation K (v GS – V t )
_

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Saturation --- Channel Length Modulation

• VDS at the edge of the inversion layer remains fixed at VGS-Vt

• But the effective length of the channel decreases with increasing VDS
• Especially a factor when channel length is short

VG > Vt
VS = 0 VDS >> 0
+
L
L
n+ n+

VB = 0

KnW 2
iD = ------------------------(v GS – V t ) 
sat 2(L – L)

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Saturation --- Channel Length Modulation

• Sometimes expressed in terms of channel length modulation parameter

KnW 2
iD = ------------(v GS – V t ) (1 + v DS )
sat 2L

• SPICE can calculate the modulation for you...

0 1 2 3 4 VDS 5
100
VGS=3.0V

80
W=1 micron
IDS (µA)
L=1 microns
Vt0= 1 volt
60 Kn=2e-5 (A/v 2)
VGS=2.5V phi =0.6
NA=1e15
40

VGS=2.0V
20
VGS=1.5V
0 VGS=1.0V

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Saturation --- Channel Length Modulation

• Or we can specify lambda explicitly in the model

KnW 2
iD = ------------(v GS – V t ) (1 + v DS )
sat 2L

VDS
0 1 2 3 4 5
60
VGS=3.0V
50
W=1 micron
IDS (µA)

40 L=1 microns
Vt0= 1 volt
VGS =2.5V Kn=2e-5 (A/v 2)
30 lambda = 0.8

20
VGS=2.0V
10
VGS=1.5V
0 VGS=1.0V

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 Output Resistance

• We can add a resistor to model the channel length modulation effect for the
large-signal model in saturation

id
G D

+ 2
K (v GS – V t ) ro
_

• What is the value of ro?

–1
iDS  W 2 –1 1
ro =   = K n ------(V GS – V t )  ----------------
v DS 2L I Dsat

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Spice element description for the NMOS and PMOS MOSFETs. Also listed is the general form of the
associated MOSFET model statement. A partial listing of the parameter values applicable to either the
NMOS or PMOS MOSFET is given in Table
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Spice large-signal model for an n-channel MOSFET under static conditions.

The general form of the Spice large-signal model for an n-

channel MOSFET under static conditions.

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 Drain current versus gate-source voltage for an n-channel
MOS transistor. The colored dots show the border
between the active region (small vGS) and the triode
region (large vGS). For the largest value of vDS, i.e., vDS5,
the transistor is in the active region for the range of vGS
shown in the figure.

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Drain current versus drain-source voltage for an n-channel MOS
transistor. The dashed curve shows the border between the
triode region and the active region

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 Schematic Simulation with Self-Defined MOSFET Model
To run simulations of MOSFETs we need to at least set the values of parameters L (channel length), W (channel width), VT0
(zero-bias threshold voltage), KP (transconductance, μn/pCox), and LAMBDA (channel-length modulation coefficient, λ).

In LT Spice, these parameters can be specified by inserting the

model into the schematic.
Go to “Edit” on the menu bar and choose “Spice Directive”, or just
click .OP the button.
In the pop-up window, type-in
“.MODEL TestN NMOS (KP=90u VT0=0.7 LAMBDA=0.01)” in the
dialogue box to set KP, VT0, and LAMBDA of the NMOS transistor

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DC Operating Point Analysis
a) To perform DC operating point analysis, go to Edit and click on Spice Analysis. Select
“dc op pnt”and type .op (or Simply click on .op (right top corner) and type .op)
b) Next go to Simulateand click on Run
c) To see the DC operating points, go to Viewand click on SPICE Error Log
(Shortcut: Ctrl + L)

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Transient Analysis

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DC Operating Point Analysis:

a) To perform DC operating point analysis, go to Editand click on Spice Analysis. Select “dc op pnt”and type
.op (or Simply click on .op(right top corner) and type .op)
b) Next go to Simulateand click on Run
c) To see the DC operating points, go to Viewand click on SPICE Error Log (Shortcut: Ctrl + L)

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Input and output characteristic of NMOS:

To obtain input characteristics connect the circuit as shown in Fig

a) Go to Editand click on Spice analysis

b) Go to DC Sweepand enter values of VGS in 1st Source
c) To get id vs VGS plot for different values of VDS, enter
values of VDS in 2nd Source.
.dc VGS 0 5V 0.001V VDS 0 2V 0.2V
a) Then Run simulation

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input characteristics

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input characteristics

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Input and output characteristic of NMOS:

To obtain output characteristics connect the circuit as shown in Fig

a) Go to Editand click on Spice analysis

b) Go to DC Sweepand enter values of VDS in 1st Source
c) To get id vs Vgs plot for different values of VGS, enter
values of VGS in 2nd Source.
.dc VDS 0 5V 1mV VGS 0 5V 1V
a) Then Run simulation

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 How to get gm plot from ID vs Vgs plot?

➢ Got to Plot Settings and click on

Add trace (Shortcut: Ctrl + A)
➢ In expression field write d(Id(M1))
and click OK.
➢ d() indicates that differentiating a
parameter with respect to X-axis,
➢ since X-axis is

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Noise Analysis
Output Noise voltage of transistor can be plotted as follows
a) Go to Edit and click on Spice analysis
b) Go to Noiseand write V[Vout] in Output field. Here, at the drain
of transistor we would like to find noise voltage. Node voltage
should keep inside the V[]
c) Enter input voltage, since Vgs
d) Select type of sweep and enter frequency range (let 1Hz to 10G with 50
per decade)
e) The overall command will be as follows
.noise V[Vout] Vgs dec 50 1 10G
1.Run the Simulation and select Vout the

simply right click on Y-axis of the plot and change it to logarithmic

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Noise Analysis

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Device Characterization
Aim : To characterize the MOSFETs so that hand calculations can be done
in the future, simulations need to be done to measure KP, VT0, λ, and γ.

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Device Characterization
Aim : To characterize the MOSFETs so that hand calculations can be done
in the future, simulations need to be done to measure KP, VT0, λ, and γ.

λ Measurement
➢ To measure λ you need to do a DC sweep of VDS
and plot ID as shown in Figure .
➢ Each curve represents a different VGS value. Any
one of these curves can be used to calculate λ.
➢ Make sure that VBS is 0V for this simulation. T
➢ The formula for calculating λ given two points on
the saturation portion of a single curve is:

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Device Characterization
VT0 Measurement
➢ VT0 can also be obtained from Figure.
➢ Using the saturation portion of two curves with equal VDS, VT0 can be
calculated as

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Device Characterization
KP Measurement

➢ Knowing λ and VT0, KP can easily be found from the equation for
MOSFET drain current in the saturation region.
➢ A little algebra gives that KP is

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Device Characterization
γ Measurement
To obtain γ you must first give the transistor a non-zero VBS. Next
calculate the new VT using the same procedure that you used to obtain VT0. γ is
then given as

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 PMOS CHARECTERISTICS

DC Operating Point Analysis:

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 NMOS pullup

 Rather than using a big (and expensive) resistor, let’s look at a NMOS
transistor as an active pullup device

Note that when the transistor is connected this way, it is not an amplifier, it is a two terminal device. When the
gate is connected to the drain of this NMOS device, it will be in saturation, so we get the equation for
the drain current

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NMOS pullup

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 IV for NMOS pull-up

 The I-V characteristic of this pull-up device:

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Active Load

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 Current Mirrors

AN
Sensitivity: LNT INITIATIVE
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 DC Voltage Sources

Characteristics of DC Voltage Sources :

• A well controlled output voltage
Small Signal Equivalent Circuit Model:
MOSFET connected in “diode configuration”

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DC Voltage Sources

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 DC Voltage Sources

PMOS voltage source

Same operation and characteristics as NMOS voltage

source. PMOS needs to be larger to attain the same Rout .

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output stage to convert voltage to current

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 DC CURRENT MIRRORS

A current mirror replicates the input current of a current sink or current source as
an output current. The output current may be identical to the input current or can be
a scaled version of it.

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 DC Current Sources

Characteristics of Current Sources

▪ A well controlled output current
▪ Supplied current does not depend on output voltage
⇒ High Norton Resistance

Current Mirror Circuit

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Basic Current Mirror Amplifier

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 DC Current Sources

Small Signal Equivalent Circuit Model:

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 DC Current Sources

PMOS Current Source

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 Node 1: The voltage here is VGS1 = VT + VDS,sat1.
Node 2: For good matching between input
and output currents, we want VDS1 and
VDS2 to be equal. Thus, the voltage at
node 2 is also VT + VDS,sat1.
Node 3: The minimum compliance voltage
will be the minimum voltage to keep M3
and M4 in saturation. This will be VT +
VDS,sat1 + VDS,sat2.
Cascode current mirror

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 Standard Cascode Current Mirror

• All 4 MOSFETs have the same VTH if body effect is

• ignored.
• VX = VY =VTH + VOV
• VGS3 = VOV + VTH as M1 and M3 carry the same “I”
VG3 = VGS3 + VX = 2VTH + 2VOV ignoring body effect.
• VG4 = 2VTH + 2VOV
2(VT + VOV) • This should also be the case with body effect – only
2VTH will become VTH1 + VTH3.

VT + VOV

Note VOV of M1 and M2 will equal

VY = VT + VOV

Min Vout = VX + VOV = VTH + 2VOV

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Simulating Current Mirrors

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Cascode Current Mirror

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Wilson Current Mirror

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