Develop and implementing low power Braun Multiplier using ECRL

CHAPTER 1

INTRODUCTION

Multiplication is one of the elementary arithmetic operations. They are used in many
DSP applications, including filtering and FFT, and they frequently cause large delays
in processing times and occupy a sizable portion of silicon in DSP systems. Multipliers
are essential components in digital signal processing and FPGA- based applications,
perhaps because they consume more power and space than other devices. Multipliers,
which in turn depend on adders, are essential components of DSP and FPGA-based
systems because they provide power, speed, and area. Therefore, the latency can be
reduced by using adders. The need for efficient operations that involve multiplication is
growing due to the increasingly complex nature of today’s computer tasks. With its
creative design, the Braun Multiplier offers a workable answer by reducing the number
of required processes. This makes it a viable option for applications requiring accurate
and speedy multiplication, such as digital signal processing and encryption.
The Braun multiplier was developed to address the need for faster and more efficient
multiplication in digital systems, particularly in applications like digital signal processing
(DSP) and real-time computing. Traditional serial multipliers, while simple, were too
slow because they processed operations sequentially, one at a time. The Braun multiplier
solved this by using parallelism to generate all partial products simultaneously, significantly
speeding up multiplication. Its regular and straightforward hardware structure, consisting
of repetitive blocks of AND gates and adders, made it easier to design and implement,
especially in VLSI (Very Large scale Integration) systems. This simplicity and uniformity
also made the multiplier well-suited for pipelining, which allowed for even faster
computations by breaking down operations into smaller, parallel stages. The design’s
scalability and high throughput made it ideal for real-time applications where quick
processing of large data sets is essential, such as in audio or video processing. By eliminat-
ing the need for complex operations like bit-shifting, the Braun multiplier further simplified
the multiplication process, contributing to its efficiency in early digital systems. Its
introduction helped meet the growing demand for faster, scalable, and easily integrated
multipliers in early computing technologies.
In order to achieve the high speed and low power demand in DSP applications

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Braun’s multiplier are broadly used. The Braun’s multiplier is generally called as the
Carry Save Array Multiplier. The architecture of a Braun’s multiplier consists of
AND gates and full adders. The prolific growth in semiconductor device industry has
been indicates to the high-performance portable systems with enhanced reliability in data
transmission. In order to maintain the high-performance fidelity applications,
emphasis will be on incorporation of low power modules in future system design.
The design of such modules power consumption or dissipation in fundamental arithmetic
computation units such as adders and multipliers. This implies a need to design low
power multipliers towards the development of efficient power and high-performance
systems. The selection of the most efficient implemented multiplication has continually
challenge DSP system designers. Every system designer offers a wide range of tradeoffs
in terms of speed, complexity and power consumption. Input sequences to the
multiplier can be fed in parallel, serial or a hybrid (parallel serial) this proposal
approaches gives high processing speed. Usually Parallel multipliers are adopted at the
expense of high area complexity. Multiple parallel multiplications Algorithms
(architectures) have been pro- posed to reduce the chip area increase the speed of the
multipliers’ and reduce the power dissipation using various techniques. Several of these
techniques reduce the power dissipation by eliminating spurious transitions in the circuit.
The structure of Braun Multiplier consists of array of AND gates and adders arranged in
the iterative manner and no need of logic registers. This can be called as non – addictive
multipliers. Architecture: An n*n bit Braun multiplier is constructed with n (n-1) adders
and n2 AND gates. The internal structure of the full adder can be realized using FPGA.
Each product can be generated in parallel with the AND gates. Each partial product
can be added with the sum of partial product which has previously produced by using the
row of adders. The carry out will be shifted one bit to the left or right and then it will
be added to the sum which is generated by the first adder and the newly generated partial
product.
The Braun multiplier has several advantages:

1. Simple and Regular Structure:

The architecture of the Braun multiplier is very straightforward and consists of
repetitive blocks, making it easy to design, implement, and scale. It follows a grid-like
arrangement of adders and AND gates.
2. Low Latency:
Since the multiplier processes partial products in parallel, it offers fast computation
compared to sequential multipliers. The delay is determined by the addition process rather

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than by the generation of partial products, which reduces latency.

3. High Throughput:
The parallel processing structure allows the Braun multiplier to have a higher
throughput. It can handle multiple operations at once, making it suitable for real- time
applications, especially in DSP and image processing.

4. Suitability for VLSI Implementation:

Its regular layout makes it well-suited for VLSI (Very Large scale Integration) design.
The uniformity and repetitive structure simplify the layout and routing in chip design,
which reduces design complexity and errors.
5. Easy Pipelining:
The design can be easily pipelined by breaking down the addition stages. Pipelining
further increases throughput, making it ideal for high-speed applications.
6. Efficient Power Usage in Some Applications:
When used in pipelined systems with proper power management techniques, the Braun
multiplier can be power efficient in specific contexts. Its ability to per- form operations in
parallel can reduce the need for multiple clock cycles.
7. No Requirement for Bit Shifting:
The structure of the Braun multiplier doesn’t require additional bit-shifting operations.
All partial products are generated simultaneously and summed using adders, which
contributes to its simplicity and speed.

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CHAPTER 2

LITERATURE SURVEY

[1] “A Novel Approach to Braun Multiplier Design Utilizing High-Speed Parallel

Prefix Adder for Low Power Applications”, Kiran V, E M Savi Teja, 2023
Observation:
The paper focuses on the trade-offs between speed and power in Braun multi- plier
designs by incorporating high-speed arithmetic techniques. The study demonstrates that
applying optimization techniques like carry-save adders can minimize the critical path delay
while achieving better power efficiency. This is particularly important for systems requiring
low latency and low power, such as real-time digital signal.
Applicability of concepts:

• Power Efficiency Techniques

• Area Minimization.

[2] “Design of an Area Efficient Braun Multiplier using High Speed Parallel Pre- fix
Adder in Cadence,” B Neeraja, R. Sai Prasad Goud, 2019
Observation:
A conventional Braun multiplier and Braun multiplier with KSA is developed and
compared in terms of area, speed and power. Conventional Braun multiplier logic is
designed with Full adder comprising of 50 transistors and XOR logic hav- ing 22
transistors built in CMOS technology. It is observed that area, power and delay are
very high. This is reduced by designing Braun multiplier logic with Full adder logic
consisting of 28 transistors and XOR logic having of 14 transistor built with KSA. The
area is reduced by 246 transistors and delay is decreased by 4.9286 ns. Braun multiplier
with of 12T XOR has a total of 450 transistors, in which transistor count is reduced by
258 and delay is also decreased by 4.650ns compared to conventional Braun multiplier.
Power consumption also very less for final design.
Applicability of concepts:

• Low Power Consumption

• Area Optimization.

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[3] “Design and Implementation of low power and highspeed Braun Multiplier
using hybrid full adder”, I Omesh, B Supriya, Y Yamini, A Likitha, D Aditya, i-
manager’s Journal on Circuits and Systems, Vol. 9, No. 2, 2021.

Observation: This paper focused on reducing power consumed by the adder circuits.
The paper discussed a proposed design that use of combinations of XOR or XNOR in
the existing circuits. The study tried to reduce the number of transistors which definitely
reduced the usage of power and power dissipation. The introduction of Braun multiplier
considerably reduced the number of transistors in the adder circuit.
Applicability of concepts:

• Low power schemes

• Optimization of circuit.

[4] “A 2 GHz High-Performance Design of Braun Multiplier with Hybrid Full Adder
for ALU”, Sakthimohan M, Sundravadivelu K, Amuthaguka D, Tamil Selvan S,
Elizabeth Rani G, Dudekula Rahul, IEEE, 2024.
Observation:
This paper presents a sophisticated approach to designing a Braun multiplier that
achieves high performance by utilizing hybrid full adders. The hybrid full adder
combines the advantages of different adder architectures to optimize speed and power
consumption, allowing the multiplier to operate effectively at a clock speed of 2 GHz.
The authors demonstrate that integrating this design into an Arithmetic Logic Unit
(ALU) significantly enhances overall computational efficiency while maintaining low
power consumption, making it suitable for high-speed digital systems.
Applicability of concepts:

• High-Speed Design

• Power Efficiency.

[5] “Implementation of Braun and Baugh-Wooley Multipliers Using QCA”, P

Kishore, Rohan sirimalla, K Sai Sushma, R Sai Kiran Reddy, IEEE, 2023.
Observation:
This paper discusses the design and implementation of Braun and Baugh-Wooley

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multipliers utilizing Quantum Dot Cellular Automata (QCA) technology. The authors
explore how QCA can achieve high speed and low power consumption com- pared to
traditional CMOS technologies. The research highlights the advantages of QCA in
implementing both multiplier architectures, emphasizing significant improvements in
area and power efficiency while maintaining reliable operation at nanoscale
dimensions. The findings indicate that QCA’s unique properties can offer substantial
benefits in digital circuit design, particularly for arithmetic operations.

Applicability of concepts:

• Technology Integration

• Area Optimization.

[6] “Application-Specific Low-Power Multipliers”, P Sakellariou, V Paliouras, IEEE,

2016 Observation:
This paper explores the design of multipliers tailored for specific applications that
prioritize low power consumption without compromising performance. The authors discuss
various multiplier architectures, including their power efficiency and area optimization.
They emphasize that application-specific designs can significantly reduce power
requirements by leveraging specialized circuitry and operational characteristics suitable for
targeted use cases, such as digital signal process- ing (DSP) and embedded systems. The
findings highlight the importance of optimizing multiplier designs based on the specific
needs of applications to achieve both performance and energy efficiency.
Applicability of concepts:

• Application-Specific Design

• Area Optimization Strategies.

[7] “A Novel Approach to Design Braun Array Multiplier Using Parallel Prefix
Adders for Parallel Processing Architectures", KD Shinde, K Amit Kumar, DS
Rashmi, R Sadiya Rukhsar, HR Shilpa, CR Vidyashree, ICSCS, 2018.
Applicability of concepts:

• Enhanced Performance

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• Benchmarking against established techniques.

[8] "Performance Analysis of CMOS, PTL and GDI Based Braun Multiplier for
Signal Processing Applications," M Mahaboob Basha, Srinivasulu Gundala, G
Ganesh Kumar, IEEE 2021.
Observation:
This paper provides a comprehensive evaluation of different design techniques for
Braun multipliers, specifically focusing on CMOS (Complementary Metal-Oxide-
Semiconductor), PTL (Pass-Transistor Logic), and GDI (Gate Diffusion Input) tech-
nologies. The authors analyze the performance of these implementations in terms of
speed, power consumption, and area efficiency, particularly within the context of signal
processing applications. The findings highlight that while CMOS technology is widely
used, GDI and PTL offer significant advantages in power and area efficiency, making
them suitable alternatives for low-power applications.
Applicability of concepts:

• Technology Comparison:

• Low-Power Design Insights.

[9] “Deployment of Braun Multiplier Using Novel Adder Formulations,” Amit Kumar
Varshney, Arun Kumar P, Praveen Kumar M, Poovendan R, S Nava- neethan, IEEE,
2023.
Observation:
This paper discusses innovative adder formulations designed to enhance the
performance of Braun multipliers. The authors present a detailed analysis of how these
novel adder architectures can improve speed, power efficiency, and area optimization in
multiplier designs. The study demonstrates that integrating advanced adder techniques with
Braun multipliers leads to significant enhancements in computational speed and reduced
power consumption, making them suitable for high- performance computing applications.
Applicability of concepts:

• Performance Optimization

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• Application in High-Performance Computing.

[10] “Design and Analysis of Efficient Vedic Multiplier for Fast Computing
Applica- tions,” Aishitha Verma, Anum Khan, Subodh Wairya, IJCDS, 2023.
Observation:
This paper focuses on the implementation of a Vedic multiplier, based on anient Indian
mathematics, to achieve high-speed performance for fast computing applications. The
research highlights the advantages of the Vedic multiplication algorithm in reducing
computational complexity, thus improving both speed and area efficiency compared to
traditional multiplier designs. The authors demonstrate how the Vedic algorithm is
particularly effective in digital signal processing and other real-time applications that
demand quick data processing. Additionally, the study investigates the power
consumption and performance improvements when integrating the Vedic multiplier
into modern computing architectures.
Applicability of concepts:

• High-Speed Computation:

• Benchmarking and Comparative Analysis.

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CHAPTER 3
PROBLEM STATEMENT AND OBJECTIVES

3.1 Problem Statement:

Develop and implementing low power Braun multiplier using efficient charge recovery logic.

3.2 Objectives:
The objectives of the work are:

1. Developing low power adder using ECRL.

2. Developing of low power Braun Multiplier using adder.

3. Parameter analysis of the designed multiplier circuit.

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CHAPTER 4
WORKING PROCEDURE
Working procedure of a Braun Multiplier:
1. Partial Product Generation:
 Step 1: The first step in the Braun multiplier involves generating the partial products.
 The partial products are formed by performing bitwise AND operations between each
bit of A and each bit of B. These partial products represent the intermediate results of
the multiplication.
 These partial products are placed in a grid-like structure, with each row corresponding
to a product of a bit from A with all the bits of B.
2. Partial Product Summation Using Carry-Save Adders (CSAs):
 Step 2: The partial products are added using carry-save adders (CSAs).
 A CSA is a type of adder that generates two outputs for each bit addition: a sum and a
carry. This is in contrast to conventional adders, which propagate the carry immediately.
In CSAs, the carry is delayed, allowing multiple partial products to be added in parallel
without waiting for carry propagation, thus speeding up the process.
 The CSAs work in a tree-like structure, where the first level adds pairs of partial
products. The sum and carry from each pair are sent to the next level of CSAs.
 The structure of these CSAs forms a reduction tree, progressively reducing the number
of terms until only a few bits remain.
3. Reduction of Partial Products:
 Step 3: The CSAs progressively reduce the number of partial products through multiple
stages. At each stage, the number of terms is halved by combining partial sums and
carries. This reduces the complexity of the multiplication.
 In a tree-like structure, each level combines the sum and carry from the previous level,
continuing until only one sum and one carry remain. These final bits represent the
multiplication result.
4. Final Summation:
 Step 4: After all the partial products are reduced using CSAs, a final carry-propagate
adder is used to sum the remaining carry and sum bits from the final reduction stage.
 The result of this final addition is the final product of the multiplication operation.

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5. Result Output:
Step 5: The final product of the multiplication is obtained after the final addition
step. This result is then output as the multiplication result of A and B.

4.1 Procedure in Designing the Braun Multiplier

Working procedure for building up a system, starting from simpler components and
then progressing to more complex ones.

1. Half Adder: Half Adder is a fundamental combinational circuit that adds two
single-bit binary numbers is shown in Figure 4.1.1. It has two inputs, typically labeled
A and B, and two outputs S and C.

Figure 4.1.1 Circuit diagram of Half adder

2. Implementing ECRL: Implementing the efficient charge recovery logic to the
designed half adder.
3. Full Adder: Full Adder builds on the half adder by adding three inputs is shown in
Figure 4.1.2: two binary digits and a carry-in bit (Cin). It produces two outputs S and
Cout.

Figure 4.1.2 Circuit diagram of Full Adder

4. 1-bit Braun Multiplier: Braun Multiplier is a hardware-efficient multiplier

designed to minimize the area and latency required for

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multiplication. For a 1-bit Braun multiplier, we consider two 1-bit binary numbers and
compute their product. The process involves:
 Partial Products: We compute the individual bits of the product.

 Addition of Partial Products: Use adders (half or full) to sum the partial products

of the designed multiplier circuit

5. Higher-bit Braun Multiplier: To extend the Braun multiplier to multiple bits, we

perform multiple stages of multiplication. For example, for an n-bit multiplier, the steps
include:
1. Generate Partial Products for each pair of bits from the two numbers.

2. Summing the Partial Products using adders to compute the final product.

3. Carry Propagation between the stages of the partial product sums

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CHAPTER 5
SYSTEM DESIGN APPROACH
5.1 DESIGN

ECRL Logic Efficient Charge Recovery Logic (ECRL) proposed by Moon and Jeong. It
uses cross-coupled PMOS transistors as shown in figure 5.1.1. It has the structure similar to
Cascade Voltage Switch Logic (CVSL) with differential signaling, It consists of two cross-
coupled transistors M1 and M2 and two NMOS transistors in the N-functional blocks for the
ECRL adiabatic logic block .It uses least number of transistors as compared to other logic
familes. The two NMOS transistors are used for the purpose of logic functions. It does not
require precharging diode and can minimize the energy dissipation. During transition of the
constant power supply, ECRL always pumps charge on the output with a full swing. However,
as the voltage on the supply clock approaches to |Vtp|, the PMOS transistor gets turned off.
ECRL consist of pull up and pull down network. The pull up network is adiabatic latch and
half of energy is dissipated in this network. The pull down network consists of two NMOS
transistors and they can be worked as logic function. Both the networks are complement to
each other. It operated on ramp power supply instead of DC supply due to its better
performance in precharge and recovery phases. During tradition, the outputs out and out/ are
charged with the constant energy of power supply and it is independent of the input signal
level. When the signal level approaches to the peak value then the PMOSFETS is get turned
off automatically.

Figure 5.1.1: Circuit diagram of ECRL

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The basic gates are commonly used in digital circuits. Some of the commonly used gates are:
AND gate, OR gate, and XOR gate. These gates are implemented using adiabatic techniques
like ECRL by analyzing their truth table, forming Boolean equations, and then designing the
circuit according to these equations. The cases where the output is zero are taken, and the
Boolean equation is formed and simplified. Similarly, the equation for the cases where the
output is equal to 1 is made. For ECRL, the circuit for the Boolean equation with output 1 is
placed below /out, and for output 0, it is placed below out/.

AND GATE

o
a b u
t

0 0 0

0 1 0

1 0 0

1 1 1

TABLE1. TRUTH TABLE FOR AND GATE

Boolean equation for 0: Abar + Bbar

Boolean equation for 1: A.B

The OR gate is another fundamental digital logic gate commonly used in digital circuits. It
performs a logical addition of two or more input signals, producing a high output (1) if at
least one input is high (1), and a low output (0) only when all inputs are low (0).When
implementing the OR gate using adiabatic techniques like ECRL, the process is similar to
other gates. The truth table for the OR gate is analyzed, and Boolean equations are formed
to represent the logic of the gate. The equation for the cases where the output is 1 is formed
and simplified, and similarly, the equation for cases where the output is 0 is created.

In the case of ECRL:

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 The circuit for the Boolean equation with output 1 is placed below /out.
 The circuit for the Boolean equation with output 0 is placed below out/.

This ensures the correct energy recovery mechanism for both output states, leading to
reduced power dissipation while maintaining the OR gate's logical functionality.

Equation for zero: Abar.Bbar

Equation for one: A+B

Full Adder is a combinational circuit that adds three input bits, producing a sum and a carry
output. It has three inputs: A, B, and Carry-in (Cin), and two outputs: Sum (S) and Carry-out
(Cout).

 Boolean Equations:
1. Sum (S) = A ⊕ B ⊕ Cin
 The sum is the result of an XOR operation on all three inputs A, B, and Cin.
2. Carry-out (Cout) = (A ∧ B) + (Cin ∧ (A ⊕ B))
 The carry-out is generated when either A and B are both1, or when Cin and the result of
the XOR operation between A and B are both 1.

TABLE 2. TRUTH TABLE FOR FULL ADDER

Equation for sum zeors: Abar.Bbar.Cbar + Abar.B.C + A.Bbar.C + A.B.Cbar

Abar(B(XNOR)Cin) + A (B(XOR)C)

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Equation for sum one’s: Abar.Bbar.C + Abar.B.Cbar + A.Bbar.Cbar + A.B.C
Abar(B(XOR)Cin) + A (B(XNOR)C)
Equation for carry zeors: Abar.Bbar.Cbar + Abar.Bbar.C + Abar.B.Cbar + A.Bbar.Cbar
Abar.Bbar + Abar.B.Cbar + A.Bbar.Cbar
Abar(Bbar + B.Cbar) + A . Bbar . Cbar
Abar.Bbar + Abar . Cbar + A . Bbar . Cbar
Bbar(Abar + A.Cbar) + Abar . Cbar
Abar . Bbar + Bbar . Cbar + Abar . Cbar
Equation for carry one’s: A.B.C + A.Bbar.C + A.B.Cbar + Abar.B.C
A.B + A.Bbar.C + Abar.B.C
A.(B + Bbar.C) + Abar.B.C
A.(B + C) + Abar.B.C
A.B + A.C + Abar.B.C
B.(A + Abar.C) + A.C
A.B + B.C + A.C

Braun multiplier

Braun edward louis first proposed the braun multiplier in 1963. It is a simple parallel
multiplier that is commonly known as the carry array multiplier. It consists of an array
of and gates and adders arranged in an iterative structure that does not require logic
registers which is shown in the Figure 5.1.1. This is also known as the non-additive multi-
plier since it does not add an additional operand to the result of the multiplication. An
n*n-bit braun multiplier requires n(n-1) adders and n2 and gates. The internal structure
of the full adder used in the braun multiplier makes braun multipliers ideal for very
largescale integration (vlsi) and application specific integrated circuit (ASIC) realization.
Each of the Ai Bj product bits is generated in parallel with the and gates. Each partial
product can be added to the previous sum of partial products by using adders. The
carry out signals are shifted one bit to the left and are then added to the sums of the first
adder and the new partial product.

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Figure 5.1.2: Circuit diagram of Braun Multiplier

5.2 REQUIREMENT

Cadence

The Cadence tool is a software suite used for designing and testing of system on- chip (SoC)
and integrated circuits (ICs). It provides a user-friendly interface for implementing, simulating,
and testing complex analog, digital, and mixed-signal designs.
Cadence virtuoso

It is a very important EDA tool for electronics students learning about IC de- sign/analysis and
PCB design/analysis.
At undergraduate level, virtuoso is majorly used for custom design and analysis of circuits
based on MOS technologies, especially in the CMOS VLSI course.
The Virtuoso System Design Platform allows IC designers to easily include system- level
layout parasitics in the IC verification flow, enabling time saving by combining package/board
layout connectivity data with the IC layout parasitic electrical model.
It enables engineers to design concurrently across chip, package, and board, saving time and
minimizing errors. It is ideal for designs that integrate multiple heterogeneous ICs, including
RF, analog, and digital devices.

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CHAPTER 6
OBJECTIVES ACCOMPLISHED
1. Developing low power adder using ECRL
AND schematic is done implementing ECRL. Waveforms delay and power are
checked.
OR schematic is done implementing ECRL. Waveforms delay and power are
checked.
XOR schematic is done implementing ECRL. Waveforms delay and power are
checked.
2. Developing of low power Braun Multiplier using adder. ( Ongoing)
Schematic of Braun multiplier is half done.

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CHAPTER 7

REMAINING OBJECTIVES AND PLAN TO

COMPLETE

2. Developing of low power Braun Multiplier using adder. (Half)

3. Parameter analysis of the designed multiplier circuit.

These are the above objectives to be accomplished and we have planned to complete it by
the end of April

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CHAPTER 8

RESULTS AND DISCUSSION

8.1 Schematics and Waveforms

Figure 8.1.1 Schematic of AND gate

Figure 8.1.2 Waveform of AND gate

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CHAPTER 10

WORK COMPLETED

The work is carried till the design of the basic building blocks needed for the Braun
Multiplier, starting with the Half Adder that is shown in the Figure 10.1. The Half Adder takes
two single bits as inputs and produces a sum and a carry output using an XOR and an AND
gate, respectively.
Half adder is designed using Cadence Virtuoso tool, first schematic is designed and
then verified results by designing the testbench which is shown in the Figure 10.2. The
designed half adder is used for designing full adder and Braun multiplier. The output
waveform of Half adder is shown in the Figure 10.3.

Figure 10.1: Schematic of Half adder

Figure 10.2: Test bench of Half adder

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Figure 10.3: Output waveform of Half adder

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CHAPTER 11
BIBLIOGRAPHY

1. V Kiran, EMS Teja, “A Novel Approach to Braun Multiplier Design Utilizing High-
Speed Parallel Prefix Adder for Low Power Application” IEEE, 2023.

2. B Neeraja, R.Sai Prasad Goud “Design of an Area Efficient Braun Multiplier

using High Speed Parallel Prefix Adder in Cadence,” IEEE, 2013.

3. I Omesh, B Supriya, Y Yamini, A Likitha, D Aditya, “Design and Implementa-

tion of low power and highspeed Braun Multiplier using hybrid full adder”, i-
manager’s Journal on Circuits and Systems, Vol. 9, No. 2, 2021.

4. Sakthimohan M, Sundravadivelu K, Amuthaguka D, Tamil Selvan S, Eliza- beth

Rani G, Dudekula Rahul, “A 2 GHz High-Performance Design of Braun
Multiplier with Hybrid Full Adder for ALU,” IEEE, 2024.

5. P Kishore, Rohan sirimalla, K Sai Sushma, R Sai Kiran Reddy, “Implementa-

tion of Braun and Baugh-Wooley Multipliers Using QCA,” IEEE, 2023.

6. P Sakellariou, V Paliouras, “Application-Specific Low-Power Multipliers,”

IEEE, 2016.

7. KD Shinde, K Amit Kumar, DS Rashmi, R Sadiya Rukhsar, HR Shilpa, CR

Vidyashree, “A Novel Approach to Design Braun Array Multiplier Using Parallel
Prefix Adders for Parallel Processing Architectures," ICSCS, 2018.

8. M Mahaboob Basha, Srinivasulu Gundala, G Ganesh Kumar, "Performance

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9. Amit Kumar Varshney, Arun Kumar P, Praveen Kumar M, Poovendan R, S

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10. Aishitha Verma, Anum Khan, Subodh Wairya, “Design and Analysis of Effi-
cient Vedic Multiplier for Fast Computing Applications,” IJCDS, 2023.

Dept of ECE,PESCE,Mandya
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 Develop and implementing low power Braun Multiplier using ECRL

Dept of ECE,PESCE,Mandya
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