Project 105: UART Protocol

A Comprehensive Study of Advanced Digital Circuits

By: Gati Goyal ,Abhishek Sharma, Nikunj Agrawal, Ayush Jain

Documentation Specialist: Dhruv Patel & Nandini Maheshwari

1
Contents
1 Introduction 3

2 Background 3

3 Structure and Operation 3

3.1 Key Components..................................................................................................................................... 3

4 Implementation in System Verilog 4

5 Test Bench 9

6 Advantages and Disadvantages 13

6.1 Advantages............................................................................................................................................. 13
6.2 Disadvantages ........................................................................................................................................ 13

7 Simulation Results 13

8 Schematic 14

9 Synthesis Design 15

10 Conclusion 16

11 Frequently Asked Questions (FAQs) 16

11.1 What is UART? ..................................................................................................................................... 16
11.2 How does UART communication work? .......................................................................................... 16
11.3 What are the key components of UART? ........................................................................................... 17
11.4 What are the typical applications of UART? ..................................................................................... 17
11.5 What are the advantages of using UART? ......................................................................................... 17
11.6 What are the challenges associated with UART? .............................................................................. 17
11.7 How does UART differ from other communication protocols like SPI or I2C?............................ 17
11.8 Can UART support multiple devices? ............................................................................................. 18
11.9 How does UART handle error detection?........................................................................................ 18

2
1 Introduction
The Universal Asynchronous Receiver-Transmitter (UART) is a widely used communication protocol for
serial data transmission between devices. It enables asynchronous communication, meaning that data is
sent one bit at a time, with the timing determined by the baud rate rather than a shared clock. UART is
fundamental in many embedded systems and digital devices for transmitting and receiving data without
the need for complex synchronization.
In UART, data transmission typically involves a start bit, followed by a sequence of data bits, an
optional parity bit for error checking, and a stop bit to signify the end of the data frame. The protocol
allows devices to communicate over a single wire, using standard baud rates to control the speed of
transmission. Its simplicity, combined with low resource requirements, makes it ideal for embedded
applications such as sensor data communication, microcontroller interfacing, and debugging.
While UART generally handles unsigned binary data, its fundamental principle of serial data trans-
mission is central to many digital systems. The protocol’s simplicity and reliability make it an essential
tool in the development of systems where straightforward, low-overhead communication is needed.

2 Background
The Universal Asynchronous Receiver-Transmitter (UART) is a serial communication protocol widely
used for transmitting data between devices. UART operates asynchronously, meaning that data is
transmitted one bit at a time without the need for a shared clock signal. This simplifies communication
in embedded systems, as devices do not need to be synchronized with each other beyond the agreement
on a common baud rate.
The UART protocol involves a simple frame structure, typically consisting of a start bit, data bits,
an optional parity bit for error checking, and stop bits to indicate the end of the transmission. The data
bits can range from 5 to 9 bits, with the start bit signaling the beginning of the data transfer and the
stop bit marking the end of the transmission.
In UART communication, the timing for sending and receiving bits is determined by the baud rate,
which must be the same on both transmitting and receiving devices to ensure proper data reception.
The simplicity and reliability of UART make it particularly well-suited for low-speed, short-distance
communication, such as interfacing microcontrollers with sensors, external devices, and other embedded
systems.
While UART is primarily used for unsigned binary data, it is commonly used for communication
in various applications, including debugging, serial data transfer, and control systems. The protocol’s
straightforward design and widespread support in embedded systems make it a versatile choice for many
communication needs.

3 Structure and Operation

The Universal Asynchronous Receiver-Transmitter (UART) is designed for serial communication, trans-
mitting and receiving data one bit at a time. Its structure involves several key components that work
together to enable reliable data transmission and reception between devices.

3.1 Key Components

• Transmitter: The component responsible for converting parallel data (from a microcontroller or
system) into a serial stream, which is then sent bit-by-bit over a single communication line.

• Receiver: The counterpart of the transmitter, it receives the serial data, converts it back into
parallel form, and passes it to the receiving system.
• Shift Register: Used in both the transmitter and receiver, this component shifts the data bits
one by one into or out of the system at the correct baud rate.

• Baud Rate Generator: Controls the timing for data transmission and reception, ensuring that
both devices communicate at the same speed (baud rate).
 • Start, Data, and Stop Bits: The start bit indicates the beginning of the transmission, the data
bits represent the transmitted data, and the stop bit(s) signal the end of the transmission.
• Parity Bit (optional): Used for error detection, the parity bit can be even or odd, and it ensures
that the number of ones in the transmitted data follows the specified parity scheme.

The operation of the UART protocol can be summarized as follows:

1. Data Transmission Initialization: In the transmitter, parallel data (often from a microcon-
troller register) is prepared for serial transmission. The start bit is added, followed by the data
bits, optional parity bit, and stop bits.
2. Serial Bit Transmission: The transmitter shifts each bit from the data register one at a time,
starting with the start bit, followed by the data bits, parity bit (if used), and ending with the stop
bit. The data is transmitted at the specified baud rate.

3. Data Reception: On the receiving end, the receiver listens for a start bit, which indicates the
beginning of incoming data. The receiver shifts each bit one by one, storing them in a shift register.
4. Data Conversion: After receiving all the data bits (and the optional parity bit), the receiver
converts the serial data back into parallel format, making it accessible to the receiving device.
5. Error Detection (optional): If a parity bit is used, the receiver checks it against the received
data to detect any errors in transmission. If errors are found, the data may be discarded or flagged
for retransmission.

6. Output Data: After the data is shifted and error checking is completed (if applicable), the receiver
outputs the parallel data for use by the receiving device.

The UART protocol is simple, yet effective, for reliable, low-speed serial communication. It is used
in a variety of applications, such as microcontroller communication, sensor data acquisition, and serial
debugging. The protocol’s flexibility with respect to baud rate, data bits, parity, and stop bits makes it
adaptable to a wide range of devices and systems.

4 Implementation in System Verilog

The following RTL code implements the Uart Protocol for the Transmitter Module in System Verilog:

Listing 1: Uart Protocol for Transmitter Module

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22 tx_serial <= 1; // Idle state is high
23 tx_done <= 0; // Reset tx_done
24 bit_index <= 0; // Reset bit index
25 end else begin
26 current_s tate <= next_state ; // Update current state on
clock edge
27 end
28 end
29

30 // State machine logic

31 always_comb begin
32 // Default ass ign ments to avoid latches
33 next_state = current_st ate ;
34

35 case ( current _st at e )

36 IDLE : begin
37 if ( send ) begin
38 next_state = START ; // Trans ition to START on send
39 end
40 end
41

42 START : begin
43 next_state = DATA ; // Trans ition to DATA after start
bit
44 end
45

46 DATA : begin
47 if ( baud_tick ) begin
48 if ( bit_index == 7) begin
49 next_state = STOP ; // Move to STOP after the
last data bit
50 end
51 end
52 end
53

54 STOP : begin
55 if ( baud_tick ) begin
56 next_state = IDLE ; // Return to IDLE after stop bit
57 end
58 end
59

60 default: next_state = IDLE ;

61 endcase
62 end
63

64 // Output and data handling

65 always_ff @( posedge clk) begin
66 case ( current _st at e )
67 IDLE : begin
68 tx_done <= 0;
69 if ( send ) begin
70 shift_reg <= data_in ; // Load data
71 bit_index <= 0;
72 tx_serial <= 1; // Idle state for serial line
73 end
74 end
75

76 START : begin
77

78 end
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84 end
85 end
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91 end
92 end
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94 end
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96

The following RTL code implements the Uart protocol for the baud generator for 50Mhz Clock
Frequency with 9600 Baud Rate in System Verilog:
Listing 2: baud generator for 50Mhz Clock Frequency with 9600 Baud Rate
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2 CLOCK_FREQ
50000000
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17 <=
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22 end
23 end
24

25 endmodule
The following RTL code implements the Uart protocol for the Receiver Module in System Verilog:
Listing 3: Receiver Module for Uart Protocol
1 module uart_rx1 (
2 input wire clk ,
3 input wire rst ,
4 input wire rx_s erial ,
 5 input wire baud_tick ,
6 output reg [7:0] data_out ,
7 output reg rx_done
8 );
9

10 typedef enum logic [2:0] { IDLE , START , DATA , STOP } state_t;

11 state_t current_state , next_state ;
12

13 reg [3:0] bit_index ; // To track the current bit being received

14 reg [7:0] shift_reg ; // Shift register for received data
15

16 // State transition logic

17 always_ff @( posedge clk or posedge rst) begin
18 if ( rst) begin
19 current_s tate <= IDLE ; // Initializ e to IDLE on reset
20 rx_done <= 0; // Reset rx_done
21 shift_reg <= 0; // Reset shift register
22 bit_index <= 0; // Reset bit index
23 $display (" Time : %0 t | Reset: Moving to IDLE state ", $time );
24 end else begin
25 current_s tate <= next_state ; // Update current state on
clock edge
26 end
27 end
28

29 // State machine logic

30 always_ff @( posedge clk) begin
31 case ( current _st at e )
32 IDLE : begin
33 rx_done <= 0; // Reset rx_done in IDLE
34 if (~ rx _s eria l) begin // Start bit is low
35 next_state <= START ;
36 $display (" Time : %0 t | Start bit detected , moving
to START state ", $time );
37 end else begin
38 next_state <= IDLE ;
39 end
40 end
41

42 START : begin
43 if ( baud_tick ) begin
44 next_state <= DATA ; // Move to data state after
start bit
45 bit_index <= 0; // Reset bit index
46 $display (" Time : %0 t | Start bit received ", $time );
47 end else begin
48 next_state <= START ; // Wait for baud tick
49 end
50 end
51

52 DATA : begin
53 if ( baud_tick ) begin
54 shift_reg <= { rx_serial , shift_reg [7:1]}; // Shift
in the received bit
55 $display (" Time : %0 t | Received Data Bit % b: % b",
$time , bit_index , rx_s erial);
56 if ( bit_index == 7) begin
57 next_state <= STOP ; // Move to STOP state
58

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62 end
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65 end
66 end
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%
74 end
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76 end
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80 end
81 end
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86 endmodule
The following RTL code implements the Uart protocol in System Verilog:

Listing 4: Uart Protocol

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21

22 . BAUD_RATE ( BAUD_RATE ),
23 . CLOCK_FREQ ( CLOCK_FREQ )
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5 Test Bench
The following test bench verifies the functionality of the Receiver Module Testbench :

Listing 5: Receiver Module Testbench

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21 . rst( rst),
22 . rx_s erial( rx_serial),
23 . baud_tick ( baud_tick ),
24 . data_out( data_out),
25 . rx_done ( rx_done )
26 );
27

28 // Instantiate the baud generator

29 baud_generator #(
30 . BAUD_RATE ( BAUD_RATE ),
31 . CLOCK_FREQ ( CLOCK_FREQ )
32 ) baud_gen (
33 . clk( clk),
34 . rst( rst),
35 . baud_tick ( baud_tick )
36 );
37

38 // Clock generation
39 always #10 clk = ~clk; // 50 MHz clock
40

41 // Serial transmission task

42 task send_serial_data ( input [7:0] data );
43 integer i;
44 begin
45 // Send start bit (0)
46 rx_serial = 0;
47 @( posedge baud_tick );
48

49 // Send 8 data bits ( LSB first)

50 for ( i = 0; i < 8; i = i + 1) begin
51 rx_serial = data [ i];
52 @( posedge baud_tick );
53 end
54

55 // Send stop bit (1)

56 rx_serial = 1;
57 @( posedge baud_tick );
58 end
59 endtask
60

61 // Testbench procedure
62 initial begin
63 // Initializ e signals
64 clk = 0;
65 rst = 1;
66 rx_serial = 1; // Idle state for serial line
67 #50 rst = 0; // Release reset
68

69 // Wait for some time

70 #100;
71

72 // Transmit first byte : 0 xAA

73 $display (" Time : %0 t | Sending byte : 0 xAA ", $time );
74 send_serial_data (8 ’ hAA );
75 wait( rx_done );
76 $display (" Time : %0 t | Receiv ed byte : 0 x% h | rx_done : % b",
$time , data_out , rx_done );
77
78 // Transmit second byte : 0 xCC
79 #100; // Wait before sending next byte
80 $display (" Time : %0 t | Sending byte : 0 xCC ", $time );
81 send_serial_data (8 ’ hCC );
82 wait( rx_done );
83 $display (" Time : %0 t | Receiv ed byte : 0 x% h | rx_done : % b",
$time , data_out , rx_done );
84

85 // End simulation
86 #100;
87 $finish ;
88 end
89 endmodule
The following test bench verifies the functionality of the Uart Protocol Testbench

Listing 6: Uart Protocol Testbench

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24 end
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28 . BAUD_RATE ( BAUD_RATE ),
29 . CLOCK_FREQ ( CLOCK_FREQ )
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43 task apply _reset ();
44 begin
45 rst = 1;
46 #100; // Hold reset for 100 ns
47 rst = 0;
48 end
49 endtask
50

51 // Task to send and verify UART data

52 task send_data ( input [7:0] data_to_s end );
53 begin
54 tx_data = data _to_send ;
55 tx_start = 1;
56 #20 tx_start = 0; // Clear start signal
57

58 wait( tx_done ); // Wait until transmission is done

59 $display (" Time : %0 t | Sent Data : 0 x%02 h", $time ,
dat a_t o_s end );
60

61 wait( rx_done ); // Wait until reception is done

62 if ( rx_data == dat a_to_s end ) begin
63 $display (" Time : %0 t | Received Data: 0 x%02 h | Test
Passed ", $time , rx_data );
64 end else begin
65 $fatal (" Time : %0 t | Received Data : 0 x%02 h | Test
Failed ", $time , rx_data );
66 end
67 end
68 endtask
69

70 // Loopback : Drive RX serial input with TX serial output

71 always @( posedge clk) begin
72 rx_serial <= tx_serial;
73 end
74

75 // Testbench logic
76 initial begin
77 $display (" Starting UART Protocol Testbench ...");
78

79 // Apply reset
80 apply_res et ();
81

82 // Test case 1: Send 0 xAA

83 send_data (8 ’ hAA );
84

85 // Test case 2: Send 0 x3C

86 send_data (8 ’ h3C );
87

88 // Si mulation complete
89 $display (" Simulation Complete : All tests passed .");
90 #100 $finish ;
91 end
92 endmodule
6 Advantages and Disadvantages
6.1 Advantages
• Simplicity: UART communication is straightforward to implement, requiring only a minimal
number of control signals (start, data, stop bits) and a shared baud rate for communication.
• Low Cost: UART uses a simple design with fewer components compared to more complex com-
munication protocols, making it cost-effective for many embedded systems.
• No Need for Synchronization: Since UART is asynchronous, devices don’t need to share a
clock signal, simplifying the hardware and making it easier to implement across different systems.

• Wide Compatibility: UART is widely supported by most microcontrollers, computers, and

peripheral devices, making it a versatile communication protocol in embedded systems.
• Error Detection (optional): UART supports optional parity bits for error detection, allowing
for simple error checking and ensuring data integrity during transmission.

6.2 Disadvantages
• Limited Speed: UART is typically slower compared to other communication protocols like SPI
or I2C, making it less suitable for high-speed data transmission.

• Short Range: The distance over which UART can reliably transmit data is limited due to the
absence of a clock signal, especially at higher baud rates.
• Limited Scalability: UART is designed for point-to-point communication, which means it is
not ideal for connecting multiple devices in a network without additional multiplexing or bus
management techniques.

• No Built-In Synchronization: Since it operates asynchronously, the baud rate must be carefully
matched between transmitting and receiving devices. Mismatched baud rates can result in data
loss or corruption.

• Requires Manual Error Handling: Although the optional parity bit allows for error detection,
UART does not have built-in mechanisms for error correction, meaning retransmission or other
corrective actions must be implemented manually.

7 Simulation Results

Figure 1: Simulation results ofUART Result TCL Console-1

 Figure 2: Simulation results ofUART Result TCL Console-2

Figure 3: Simulation results of Output for Uart Protocol

8 Schematic Design

Figure 4: Schematic of Uart Protocol

9 Synthesis Design

Figure 5: Synthesis of Uart Protocol

10 Conclusion
The UART protocol is a widely used and simple communication standard that enables reliable serial data
transmission between devices. It operates asynchronously, transmitting data bit-by-bit, which allows devices
to communicate without needing a shared clock signal. Its simplicity, ease of implementation, and low
resource requirements make UART a popular choice in many embedded systems and applications that
require low-speed, point-to-point communication.
While UART offers significant advantages such as low cost, wide compatibility, and simplicity, it also
has certain limitations, including slower data transmission speeds, limited range, and scalability concerns
in multi-device communication. Despite these drawbacks, UART remains an essential protocol for many
applications, including microcontroller interfacing, sensor data acquisition, debugging, and more. Its
optional error detection feature, using parity bits, further enhances its reliability in data transmission.
In conclusion, UART continues to be a versatile and widely adopted communication protocol in
embedded systems, offering a straightforward solution for serial communication with minimal overhead,
making it indispensable in numerous digital systems.

11 Frequently Asked Questions (FAQs)

11.1 What is UART?
The Universal Asynchronous Receiver-Transmitter (UART) is a communication protocol that en-ables
asynchronous serial data transmission between devices, sending data one bit at a time without requiring
a shared clock signal.

11.2 How does UART communication work?

In UART communication, data is transmitted starting with a start bit, followed by data bits, an optional
parity bit for error detection, and stop bits. The receiver then reconstructs the data based on the
predefined baud rate.

11.3 What are the advantages of using UART?

Advantages include its simplicity, low cost, reliable data transmission, no need for synchro-
nization, wide compatibility, and optional error detection using parity bits.

11.4 What are the challenges associated with UART?

Challenges include limited transmission speed, short communication range, limited scalability
(point-to-point communication), and the need for careful matching of baud rates between devices to
ensure reliable data transmission.

11.5 How does UART differ from other communication proto-

cols like SPI or I2C?
UART operates asynchronously with a single data line for transmission, whereas SPI and I2C are syn-
chronous protocols that require additional lines and can support communication with multiple devices.
UART is simpler but slower compared to these protocols.
11.6 Can UART support multiple devices?
UART is designed for point-to-point communication, meaning it is typically used to connect only
two devices. However, it can support multiple devices with additional multiplexing or bus management
schemes.

11.7 How does UART handle error detection?

UART can use an optional parity bit to detect errors during transmission. It supports even or odd
parity, and the receiver can check if the number of ones in the data matches the expected parity.