Al-Madina Higher Institute for Engineering and Technology

Digital Circuits Design

COMM 471

Dr. Saeed Mohsen

Course Aim
By the end of the course, students will acquire knowledge of:

Digital Integrated Circuits (ICs)

Resistor Transistor Logic

Emitter Coupled Logic

Diode Transistor Logic

Transistor Transistor Logic

CMOS Logic
Course Grading
Midterm exam (25 Marks)

Quizzes (10 Marks)

Sheets, Assignments (10 Marks)

Attendance (Lectures + Sections) (5 Marks)

Activity in lectures (5 Marks)

Scientific Reports (5 Marks)

Final exam (40 Marks)

Project (Software + Scientific report + Short Video + Presentation)

Each team will be 5 members (No Excuses for Deadlines)
Contents

• Introduction to Digital ICs

• Resistor Transistor Logic Gates

• Emitter Coupled Logic Gates

• Diode Transistor Logic Gates

• Transistor Transistor Logic Gates

• CMOS Logic Gates

 Introduction to Digital ICs (Lec 1)

An integrated circuit Design (abbreviated as IC)

What Is Integrated Circuit ?

It is a small silicon semiconductor, called a chip, which contains
transistors, diodes, resistors, and capacitors.
1

The digital IC operate with a binary signal. 0

binary signal
 Introduction to Digital ICs
Advantages of Digital Integrated Circuit (IC)

1- small package, size is reduced in a system

2- IC is low cost

3- low power consumption

4- Operating speed is high

5- Reducing external wires which can be connect

 Introduction to Digital ICs
Digital IC classification

Complexity Circuit Technology

Fabrication method Logic operation
(logic family)
Thick Film RTL
Glass is used in IC NOR
NAND ECL
Thin Film
Non conducting material AND DTL
to make passive elements
NOT
TTL
Hybrid NMOS
PMOS
Monolithic
Components are integrated on
a single piece of silicon crystal
CMOS
 Introduction to Digital ICs
Digital IC classification
Complexity of digital IC
IC Classification Equivalent Basic Logic Number of
Gates Components
i.e. Transistors
Small-scale integration (SSI) Less than 12 Up to 99

Medium-scale integration (MSI) 12 - 99 100 - 999

Large-scale integration (LSI) 100 - 999 1,000 - 9,999

Very Large-scale integration (VLSI) Above 1,000 Above 10,000

 Introduction to Digital ICs

Saturated IC
It means that the transistors are driven into saturation region, such as RTL,
DTL, and TTL.

Non saturated IC
It means that the transistors are driven into cutoff or active regions, such as
ECL.
 Introduction to Digital ICs
Logic Levels
The input and output voltages of a gate represented as LOW and HIGH.

Digital systems assume two values or two status or two levels.

Positive logic Negative logic

+5V HIGH 1 0V LOW 0

0V LOW 0 +5 V HIGH 1
 Introduction to Digital ICs

Logic Levels for TTL

Practically, the voltage level varies slightly, due to internal resistances and loading effects.
 Introduction to Digital ICs
Logic Levels for CMOS
 Introduction to Digital ICs

Characteristics of Digital ICS (Characteristics of Logic Gates)

1- Fan-out
It is the maximum number of similar logic gates connected to the output of a driving gate.

driving gate

driving Gate
 Introduction to Digital ICs

Characteristics of Digital ICS

2- Fan-in
It is the maximum number of inputs that can be applied to a logic gate.
 Introduction to Digital ICs NAND truth table
0 0 1
Characteristics of Digital ICS 0 1 1
1 0 1
3- Current and Voltage Parameters
1 1 0
 Introduction to Digital ICs
The noise voltage will be generated due to electric and magnetic fields of connecting
wires between logic circuits.

Noise Immunity
The logic circuit's ability to tolerate a noise signal without causing a false change in
its output.
 Introduction to Digital ICs
Characteristics of Digital ICS
4- Noise Margin
A mathematical measure of noise immunity of a logic circuit.
It is maximum undesired noise voltage that can be added to a logic gate input which will not affect the output.
The higher noise margin, it is a better logic circuit.
 Introduction to Digital ICs
Characteristics of Digital ICS
Noise Margin
There are two values of noise margin for a logic gate (VNH and VNL).
VNH: the difference between the minimum voltage HIGH output and the minimum voltage required for a HIGH input

VNL: the difference between the maximum voltage LOW output and the maximum voltage required for a LOW input

High level
noise margin
Low level
noise margin
Characteristics of Digital ICS Introduction to Digital ICs
Output Switching Time
The minimum amount of time needed for a logic gate to switch from
a logic 0 to a logic 1 level and back again.

5- Propagation Delay Time (tP) or Gate Delay

The time interval which it takes the output digital circuit to respond to the input level change of a pulse

Represented by the average switching time.

Shorter propagation delay, higher the speed of the circuit.

Input and output waveforms of a logic gate
 Introduction to Digital ICs
Characteristics of Digital ICS
Every IC needs a certain electrical power to operate, connected to power pins of the IC.

6- Power Dissipation (PD) of IC

The product of the dc supply voltage (VCC) by the amount current drawn from the supply ICCL or ICCH
The current drawn from the dc supply changes due to the output of logic circuit changes.

The average supply current (ICCavg)

The ICCL & ICCH determined by datasheet

Thus, Lowest power dissipation is better

 Introduction to Digital ICs
Characteristics of Digital ICS
7- Speed Power Product (SPP) or Figure of Merit
The propagation delay time of an integrated circuit multiplied by the average power dissipation.

SPP = Propagation delay × Average power dissipation Unit W.s =J

SPP used to evaluate the performance of an IC

For any digital IC, 1- Shorter propagation delay (higher speed)

2- Lower power dissipation
 Introduction to Digital ICs
Characteristics of Digital ICS
8- Current Sinking and Current Sourcing
current source logic
A driving gate is able to supply a current to a load gate when in output is logic 1 state.

Example: RTL is current source logic

current sink logic

A driving gate is able to sink a current from a load gate when the output is logic 0 state.

Example: TTL is current sink logic

.
 Introduction to Digital ICs

Ideal voltage levels representation for each logic family

Practically, it is difficult to get these voltages

 Introduction to Digital ICs

NOT Gate (Inverter)

OR Gate

Truth Table
 Resistor Transistor Logic (RTL) Gates (Lec 2)
BJT Transistor can operate in four modes “regions”

1- Saturation
2- Cut-off
3- Linear (active)
4- Inverse active

In RTL, the transistors are driven “biased” in cut-off region or in saturation region.
 Resistor Transistor Logic (RTL) Gates
RTL is the first family of logic circuits in 1960

Advantage of RTL
is simple design Resistor& Transistor Symbol of NOR gate
Disadvantage of RTL
is low switching speed and Low noise immunity

The function of the RTL circuit

operates as a NOR gate.

Basic RTL circuit

 Resistor Transistor Logic (RTL) Gates

Truth table of NOR gate

A B VO
LOW ( 0.2 V) or 0 0 1 Vo = VCEsat = x V based N load gates
iC
0 1 0
1 0 0
1 1 0 Vo = VCEsat = 0.2 V

iC = VCCR− VO
C

NOR gate drives similar N load gates.

NOR gate N load gates
RTL circuit driving N load gates
 Resistor Transistor Logic (RTL) Gates
Circuit Operation of the RTL Gate
1- If two inputs are low “ A= B = 0.2 V DC”, Transistors T1 and
T2 will be cutoff “OFF” and outputs Vo will be HIGH. Vo = VCC.
iC

2- If one input is high or both inputs are high “A or B =

VCC”, the corresponding transistor/s will be operate in
saturation (ON). Therefore, the output VO will be LOW
“0.2V”. Where other input in cut off due to is LOW.

NOR gate N load gates

RTL circuit driving N load gates
 Resistor Transistor Logic (RTL) Gates

IB = IB1 + IB2 +….. IBN

Loads are the same. So, the base currents are equal.

IB = N IBN = IC

Where N is number of fan-out , N is an integer number.

 Resistor Transistor Logic (RTL) Gates
Example (1)
Given in the Fig 1, RC = 640 Ω, VCC= 3.6 V, load is 450/N Ω series with voltage source 0.8 V
If N = 5, determine the minimum hfe required.

IB is the base current for each load transistor

ICsat is the collector current for the load transistor in saturation

ICsat = (VCC - VCEsat ) / RC

Value of N must satisfy this condition hfe IB ≥ ICsat , which confirm that
transistor driven in saturation region. where hfe is β of transistor
Fig 1
IB will be 0.767 mA , hfe = 6.92 ~7
Is the hfe is suitable for this circuit ?
 Emitter Coupled Logic (ECL) Gates (Lec 3)

In ECL, the transistors are driven “biased” in cut-off region or in active region

The function of the ECL circuit

operates as OR or NOR gate.
Symbol of ECL logic gate

Advantages of ECL
1- It has shortest propagation delay time among bipolar digital circuits.
2- So, it has highest switching speed of all logic families.
Disadvantages of ECL
It is complex circuit and costly.
Low noise immunity
 Emitter Coupled Logic (ECL) Gates

Voltage Transfer Characteristics of ECL

 Emitter Coupled Logic (ECL) Gates
High level (Logic 1) in the ECL = – 0.9 V

Low level (logic 0) in the ECL = – 1.7 V

Power Supply of the ECL is from – 4.5 V to – 5.2 V

Basic ECL circuit

 VE < VB
Emitter Coupled Logic (ECL) Gates VB < VC

Circuit Operation of the ECL Gate

Let VR less=-1.3V
1- circuit compare, If vX and vY are LOW “vx=-1.7 (if vX ,vY < VR)

Q1,Q2 are cut-off “Off” and QR is biased in active region “ON”,where ICXY
= 0 “since VCC = 0”, vo1 = VC1 = 0 – ICXY RC1 = 0 V, vo2 = negative, therefore,
vo1 > vo2 and vNOR = vo1 – VBEonQ4 = 0 – 0.7 V = – 0.7 V. “due to – 0.7 V is
largest possible voltage”.So, vNOR is HIGH “-0.9V”,and vOR is LOW “-1.7
V” .
It is designed to operate with VCC = 0 V , and VEE- = - 5.2 V
QR is supplied by constant voltage VR from an external power supply.

vE = vR – VBEonQR

vE – V −
iCR = iE =
RE
 Emitter Coupled Logic (ECL) Gates
Circuit Operation of the ECL Gate

2- If vX or vY is or both High, “- 0.9 V”. So, the corresponding transistor

conduct “ON” in active region, and QR is cutoff. mean (vX ,or vY > vR),
vo2 = vC2 = 0 – RC2 iC2 = – RC2 iCR

QR, goes to cut-off, where ICR= 0 , vo2 = 0 V, Q3 is in active region,

Therefore, vo2 > vo1, and vOR = vo2 – VBEonQ3 = 0 – 0.7V = – 0.7 V. So, vOR is
HIGH, “mean - 0.7 V consider High level” vNOR is LOW.

vE – V −
iCXY = iE = R
E

Emitter Follower Circuit is used to shift the output and input voltage
levels of an ECL circuit. So that V (0) and V (1) are the same for inputs
and outputs. In addition, amplify the current.
 Emitter Coupled Logic (ECL) Gates
Ground
connected to V- Emitter follower
ECL circuit
Calculation of Power Dissipation for an ECL

PD = (ICQXY + ICR QR + ICQ3+ ICQ4 ) ( 0 – v-)

 Emitter Coupled Logic (ECL) Gates
Reference Circuit is designed to provide a desired reference voltage (VR) without the need
for an external power supply.

It consists of R1 , R2 , R5 , D1 , D2 , Q5

The voltage at base of transistor Q5 is

vB5 = VCC – i1R1
Therefore,
VR = vB5 – VBEonQ5
VR – VEE −
iE5 = i5 ~
R5
VNOR – VEE −
i4 = R4
PD at logic(1) = (iCXYQ + iCR QR + i5 + i1+ i3 + i4) ( 0 – v-)
 Diode Transistor Logic (DTL) Gates (Lec 4)
In DTL, the transistors are driven “biased” in cut-off region or in saturation region.

The function of the DTL circuit

operate as a NAND gate. Symbol of DTL logic gate

When Q0 in saturation, vo = VCEsat = 0.1 V “ defined as logic 0”.

Basic DTL circuit

Circuit Operation of the DTL Gate
1- If two inputs vX and vY are High, “Logic 1” or equal VCC = 5 V, Dx and Dy are reverse biased “ open circuit”.

D1 and D2 are forward biased “ON” and Q0 will be ON “ driven in saturation”, vo = VCEsat = 0.1 V “defined as logic 0”.
VB > V E
v1 = VɤD1+ VɤD2 + VBEsat

VCC − v1 VCC − VCEsat VBEsat − 0

i1 = i2 = iRC = iR = where VBEsat = vB
R1 RC RB

KCL iB = i2 – iR

iDX

iDX = iDY = 0
iDY

2- If vX or vY is High, the corresponding diode conduct, Q0 still be cut off , vo = VCC = 5 V

Circuit Operation of the DTL Gate
3- If vX and vY are LOW, “Logic 0” or equal “0.1 V”, Dx and Dy are forward biased.

If v1 = VɤDx+ vx = 0.7 + 0.1 = 0.8 V , 0.8 < 1.4

Therefore, D1 and D2 will be OFF and Q0 is in cut-off “OFF”. VE > VB

No current pass in D1 and D2 and Q0.

So, i2 = iR = iB= iC = 0 , vB = 0 V

Q0 will be cut off , vo = VCC = 5 V “ defined as logic 1”.

VCC – v1
i1 =
R1 ,
i
iDX = iDY = 1
2

The pull down resistor “RB”

It is used to decrease the switching time of the output transistor as it goes from saturation to cutoff.
Calculation of Power Dissipation for an DTL

If vX = vY = logic 1

PD = (i1 + iRC ) (VCC – 0)

If vX = vY = logic 0

PD = (i1 ) (VCC – 0)

PD(0) + PD(1)
PDaverage = 2
Fan-out of the DTL Gate
For vX and vY is High

IL’= N IL N is an integer

KCL iRC + N IL = iC , where iC = β iB

iRC + N IL = β iB

VCC – v1
IL =
R1
v1 = VɤDx+ vx = 0.7 + 0.1

VCC − VCEsat
iRC = iC =
RC
 Transistor Transistor Logic (TTL) Gates (Lec 5)
In TTL, the transistors are driven “biased” in cutoff region or in saturation region.

The function of the TTL circuit

operate as a NAND gate. Symbol of TTL logic gate

Power supply of TTL is 5 V

The input stage of a TTL gate uses multi-emitter transistor Q1.

Advantage of TTL
It increases switching speed of the output transistor Q0 from saturation to cut off.
It is faster than CMOS
 Transistor Transistor Logic (TTL) Gates
Circuit Operation of TTL
1- if two inputs vX = vY are high “logic 1 or 5 V”, the base–emitter junctions of Q1 is forward biased (Q1 operate in
inverse active mode). So, i1 passes to the base of Q2 and Q0. and transistors Q2 and Qo are driven into saturation “ON”.
VE > VB
vO = VCEsat = 0.1 V

vB1 = VBEon Q1 + VBEsat Q2 + VBEsat Q0 = 0.7+ 0.8 + 0.8 = 2.3 V

vC2 = VCEsat Q2 + VBEsat Q0 = 0.1 + 0.8 = 0.9 V

VCC – VB1 VCC – VC2 VCC – VCEsat VBEsat – 0

i1 = iB1 = i2 = i3 = i4 =
R1 R2 R3 RB
iEX
iEY
iEX = iEY = βReverse iB1 iB2 = i1 + iEX + iEY = (1 + 2 βR) i1 iE2 = i2 + iB2
iB0 = iE2 - i4
i2
To ensure transistor Q2 in saturation, βFQ2 ≥
iB2
i
To ensure transistor Q0 in saturation, βFQ0 ≥ 3
iB0 Basic TTL NAND circuit
 Transistor Transistor Logic (TTL) Gates
Circuit Operation of TTL
2- If both inputs vX = vY are low “logic 0 = 0.1 V”, the Q1 is biased in saturation “ON”.

vB2 = VCEsat Q1 + Vx = 0.1 + 0.1 = 0.2 V. Therefore, Q2 and Q0. are biased in cutoff “OFF”.

vB1 = VBEsat + Vx = 0.8 + 0.1 = 0.9 V

VCC – VB1
i1 = i2 = i3 = i4 = 0 A , vBo = 0 V. vo = VCC = 5 V “defined as logic 1”.
R1

iEX = iEY = iB1

iEX
iEY

Basic TTL NAND circuit

 Transistor Transistor Logic (TTL) Gates
Calculation of Power dissipation for an TTL
if vX = vY = logic 1

PD = (i1 + i2 + i3 ) ( VCC – 0)

if vX = vY = logic 0

PD = (i1) (VCC – 0)

PD(0) + PD(1)
PDaverage = 2

Basic TTL NAND circuit

 Complementary Metal Oxide Semiconductor (CMOS) Gates (Lec 6)

Combinational Logic
Combinational logic circuit: we can combine different logic gates in the circuit, this circuit
hasn’t any memory.

For example, NMOS and PMOS transistors can be used together. So, it is called CMOS.

CMOS, NMOS, and PMOS operate into saturation region.

Power supply of CMOS from 3 to 15 V.

Advantages of CMOS
The highest speed and least power consumption, then NMOS, then PMOS.

We will design a combinational logic circuit using NMOS and PMOS transistors. How ?
 CMOS Logic Gates
MOS transistors can be used as ON/OFF switches. They are two types n-channel (NMOS) and p-channel (PMOS).

When the gate of an nMOS transistor is “1”, the transistor is ON.

When the gate of an nMOS transistor is “0”, the transistor is OFF.

When the gate of an pMOS transistor is “1”, the transistor is OFF.

When the gate of an pMOS transistor is “0”, the transistor is ON.
 CMOS Logic Gates
CMOS Inverter Circuit “NOT”

Logic symbol of NOT

Truth table
A Y
0 1
1 0 CMOS Inverter circuit

Operation of the CMOS Inverter

1- When the input “A” is 0, the nMOS transistor is OFF and pMOS transistor is ON.
The output Y will be “1” due to it connected to VDD.

2- When the input “A” is 1, the pMOS transistor is OFF and nMOS transistor is ON.
The output Y will be “0”..
 CMOS Logic Gates
CMOS AND Circuit

Series Connection

Logic symbol of AND gate

Truth table CMOS AND circuit

CMOS OR Circuit

Parallel Connection

Logic symbol of OR gate

 CMOS Logic Gates
CMOS NAND Gate
The CMOS transistor circuit design must be satisfy all output states of a logic gate.

Logic symbol of NAND

 CMOS Logic Gates
CMOS NOR Gate

Logic symbol of NOR

 CMOS Logic Gates
Example (2)
Write Boolean logic function expression for the logic diagram of AND-OR-Invert gate in the Fig. 1.

Fig. 1

Solution

Y = A . B + C. D
 CMOS Logic Gates

Transmission Gate: a parallel combination of nMOS and pMOS transistors.

Function of Transmission Gate: it is used as bi-directional switch that controlled by control signals.

Structure of CMOS Transmission Gate

Transmission Gate
 CMOS Logic Gates

Advantages and Disadvantages of CMOS Family

Advantages

1- It consumes less power

2- Fan-out is more
3- Better noise margin

Disadvantages

1- Low switching speed

2- Greater propagation delay
 CMOS Logic Gates (Lec 7)
The switching speed of a CMOS gate depends on “Transition time and Propagation delay time”.

Transition Time: The amount of time that the output of a logic circuit takes to change from one state to another

Rise Time (tr): is the time taken by the output to change from LOW to HIGH.

Fall Time (tf): is the time taken by the output to change from HIGH to LOW.
 CMOS Logic Gates
Dynamic Electrical Behavior of CMOS
The switching speed and power consumption of CMOS gates are depend on the dynamic characteristics and a load.

1- AC “dynamic” characteristics of the CMOS, which are the output changes between states.

2- Its load which consists of DC load (RL and VL) and AC load (CL).

The rise time and fall time of a CMOS output depend on load capacitance (CL), if CL increases, transition time will be increase

Load

Equivalent circuit for transition time of a CMOS output

 CMOS Logic Gates
Analysis of Rise Time VOUT

If VIN = 0 to 1.5 V, pMOS (ON), nMOS (OFF)

(Logic 0)

where RP CL is time constant

 CMOS Logic Gates
Analysis of Fall Time VOUT

If VIN = 3.5 to 5 V, pMOS (OFF), nMOS (ON)

(Logic 1)

Rn CL is time constant
 CMOS Logic Gates
Dynamic Power of a CMOS Circuit
Due to charging and discharging the CL

The power consumption during transition

𝑃𝑇 = 𝐶𝑃𝐷 × 𝑓 × (𝑉𝐷𝐷)2

Power dissipation due to CL , CPD = from 20 pF to 24 pF for CMOS gate

𝑃𝐿 = 𝐶𝐿 × 𝑓 × (𝑉𝐶𝐶)2 , f = 100 kHz or 1 MHz

Total dynamic power of CMOS circuit

𝑃𝐷 = 𝑃𝑇 + 𝑃𝐿
 BiCMOS Logic Gates
BiCMOS Inverter
It combine between advantages of BJT and CMOS transistors.

It is prefer in high speed applications.

Operation of BiCMOS Inverter

1- If Vin = 0 V “logic 0”,
T3 will be off which keeps T1 off. T4 is on and supplies base current to T2 which
conducts and acts as current source to charge the load CL toward 5 V “VDD”.

The output Vout = 5 V – VBE T2.

2- If Vin = 5 V “logic 1”
T4 will be off. so, T2 will be off. T3 is on and supplies base current to T1 which
conducts and acts as current source to charge the load CL which discharges
through it to 0 V “GND”.

The output Vout = 0 V + VCEsat T1.

BiCMOS Inverter circuit
 Memory Using CMOS
Memory Cell: is a circuit or a single device that can store a bit of information.

Random Access Memory (RAM): a read–write memory in which each individual cell can be
addressed at any particular time.

Read-Only Memory (ROM): The set of data in this memory is considered to be fixed.

The basic CMOS SRAM (static RAM) cell

 Comparison between RTL, ECL, DTL, TTL, and CMOS families
Parameter RTL ECL DTL TTL CMOS

Propagation delay 12 ns 0.75 ns 30 ns 10 ns 70 ns

Noise margin ---- 150 mV 0.7 V 0.4 V 0.45 VDD

Power dissipation 12 mW 5 mW 60 mW 10 mW 0.01 mW

Fan-out 5 25 8 10 50
Speed power product 144 pJ 0.5 pJ 1800 pJ 100 pJ 0.7 pJ
Power supply voltage Fixed 5 V - 4.5 to - 5.2 V Fixed 5 V Fixed 5 V 3 to 15 V
 References

[1] R. P. Jain, "Modern Digital Electronics", 3rd ed., McGraw Hill Publication, India, 2003.

[2] Donald. A. Neamen "Microelectronics Circuit Analysis and Design", 4th ed., 2018.

[3] A. Anand Kumar, "Fundamental of Digital Circuits", 1ist ed., USA, 2016.