+

College of Information Technology

Computer Architecture and Organization
(CS 251 )
Lecture (4)
Dr. Shahira Mohamed
+

William Stallings
Computer Organization
and Architecture
10th Edition
© 2016 Pearson Education, Inc., Hoboken,
NJ. All rights reserved.
+ Chapter 3
A Top-Level View of Computer
Function and Interconnection
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+

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Hardware programming

 This means connecting the basic logic

components, e.g. AND, OR, Flip-Flop gates, in a
specific configuration to implement the required
function.

 The result of this process is called a hardwired

program.

 Examples: a counter, decoder, adder, etc.

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+ Software programming
 This means writing a sequence of instructions that
perform the required function. These instructions are
called a software program.

 The program is executed on an architecture similar to

the IAS computer which is based on three key concepts:

1) Data and instructions are stored in a single read-

write memory.

2) The contents of this memory are addressable by

location, without regard to the type of data
contained there.

3) Execution occurs in a sequential fashion from one

instruction to the next.
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+ Data
Sequence of
arithmetic
and logic
Results
functions

Hardware (a) Programming in hardware

and Software
Approaches Instruction
codes
Instruction
interpreter

Control
signals

General-purpose
Data arithmetic Results
and logic
functions

(b) Programming in software

Figure 3.1 Hardware and Software Approaches

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+
Components of a general-purpose computer.

 CPU
• Instruction interpreter
• Module of general-purpose arithmetic and logic functions
 Main memory :
Used to store the instructions and data
 I/O Components
 Input module
• Accepting data and instructions from external devices
 Output module
• Used to send results to external devices
 CPU Main Memory
0
System 1
2
PC MAR Bus
Instruction
Instruction
Instruction
IR MBR

I/O AR
Data
Execution
unit Data
I/O BR Data
Data

I/O Module n–2

n–1

PC = Program counter
Buffers IR = Instruction register
MAR = Memory address register
MBR = Memory buffer register
I/O AR = Input/output address register
I/O BR = Input/output buffer register

Figure 3.2 Computer Components: Top-Level View

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 MEMORY
Memory Memory buffer
address register (MBR)
register (MAR) • Contains the data
• Specifies the to be written into
address in memory memory or
for the next read or receives the data
write read from memory
MAR

I/O address I/O buffer

register (I/OAR) register (I/OBR)
+ • Specifies a • Used for the
particular I/O exchange of data
device between an I/O
module and the
CPU
MBR

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 Fetch Cycle Execute Cycle

Fetch Next Execute

START HALT
Instruction Instruction

Figure 3.3 Basic Instruction Cycle

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+
Fetch Cycle

 At the beginning of each instruction cycle the processor

fetches an instruction from memory

 The program counter (PC) holds the address of the

instruction to be fetched next

 The processor increments the PC after each instruction

fetch so that it will fetch the next instruction in sequence

 The fetched instruction is loaded into the instruction

register (IR)

 The processor interprets the instruction and performs the

required action

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 Action Categories
• Data transferred • Data transferred to
from processor to or from a peripheral
memory or from device by
memory to transferring
processor between the
processor and an
I/O module

Processor- Processor-
memory I/O

Data
Control
processing

• An instruction may • The processor

specify that the may perform
sequence of some arithmetic or
execution be logic operation on
altered data

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+
Example
 Consider a simple example using a hypothetical machine that
includes the characteristics listed in Figure 3.4.

 The processor contains a single data register, called an accumulator

(AC).

 Both instructions and data are 16 bits long. Thus, it is convenient to

organize memory using 16-bit words.

 The instruction format provides 4 bits for the opcode, so that there
can be as many as 24 = 16 different opcodes, and up to 212 = 4096
(4K) words of memory can be directly addressed.

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 0 3 4 15
Opcode Address

(a) Instruction format

0 1 15
S Magnitude

(b) Integer format

Program Counter (PC) = Address of instruction

Instruction Register (IR) = Instruction being executed
Accumulator (AC) = Temporary storage

(c) Internal CPU registers

0001 = Load AC from Memory

0010 = Store AC to Memory
0101 = Add to AC from Memory

(d) Partial list of opcodes

Figure 3.4 Characteristics of a Hypothetical Machine

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+
Example

 Figure 3.5 illustrates a partial program execution, showing

the relevant portions of memory and processor registers.

 The program fragment shown adds the contents of the

memory word at address 940 to the contents of the memory
word at address 941 and stores the result in the latter
location.

 Three instructions, which can be described as three fetch

and three execute cycles, are required:

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Example
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 0 PC 300 1 9 4 0 3 0 1 PC
301 5 9 4 1 AC 301 5 9 4 1 0 0 0 3 AC
302 2 9 4 1 1 9 4 0 IR 302 2 9 4 1 1 9 4 0 IR
• •
• •
940 0 0 0 3 940 0 0 0 3
941 0 0 0 2 941 0 0 0 2
Step 1 Step 2
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 1 PC 300 1 9 4 0 3 0 2 PC
301 5 9 4 1 0 0 0 3 AC 301 5 9 4 1 0 0 0 5 AC
302 2 9 4 1 5 9 4 1 IR 302 2 9 4 1 5 9 4 1 IR
• •
• •
940 0 0 0 3 940 0 0 0 3 3+2=5
941 0 0 0 2 941 0 0 0 2
Step 3 Step 4
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 2 PC 300 1 9 4 0 3 0 3 PC
301 5 9 4 1 0 0 0 5 AC 301 5 9 4 1 0 0 0 5 AC
302 2 9 4 1 2 9 4 1 IR 302 2 9 4 1 2 9 4 1 IR
• •
• •
940 0 0 0 3 940 0 0 0 3
941 0 0 0 2 941 0 0 0 5
Step 5 Step 6

Figure 3.5 Example of Program Execution

(contents of memory and registers in hexadecimal)
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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+
Example
1. The PC contains 300, the address of the first instruction. This
instruction (the value 1940 in hexadecimal) is loaded into the
instruction register IR, and PC is incremented.

2. The first 4 bits (first hexadecimal digit) in the IR indicate that the
AC is to be loaded. The remaining 12 bits (three hexadecimal digits)
specify the address (940) from which data are to be loaded.

3. The next instruction (5941) is fetched from location 301, and the
PC is incremented.

4. The old contents of the AC and the contents of location 941 are
added, and the result is stored in the AC.

5. The next instruction (2941) is fetched from location 302, and the
PC is incremented.

6. The contents of the AC are stored in location 941.

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 Instruction Operand Operand
fetch fetch store

Multiple Multiple
operands results

Instruction Instruction Operand Operand

Data
address operation address address
Operation
calculation decoding calculation calculation

Return for string

Instruction complete, or vector data
fetch next instruction

Figure 3.6 Instruction Cycle State Diagram

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+
I/O Function
 I/O module can exchange data directly with the processor

 Processor can read data from or write data to an I/O module

 Processor identifies a specific device that is controlled by a
particular I/O module
 I/O instructions rather than memory referencing instructions

 In some cases it is desirable to allow I/O exchanges to occur

directly with memory
 The processor grants to an I/O module the authority to read from
or write to memory so that the I/O memory transfer can occur
without tying up the processor
 The I/O module issues read or write commands to memory
relieving the processor of responsibility for the exchange
 This operation is known as direct memory access (DMA)

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+

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 Read Memory
Write
N Words
Address 0 Data

Data N–1

Read I/O Module Internal

Write Data

External
Address M Ports Data

Internal
Data Interrupt
Signals
External
Data

Instructions Address

Control
Data CPU Signals

Interrupt Data
Signals

Figure 3.15 Computer Modules

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 The interconnection structure must support the
following types of transfers:

Memory Processor I/O to or

I/O to Processor
to to from
processor to I/O
processor memory memory

An I/O
module is
allowed to
exchange
data
Processor Processor
directly
reads an Processor reads data Processor
with
instruction writes a from an I/O sends data
memory
or a unit of unit of data device via to the I/O
without
data from to memory an I/O device
going
memory module
through the
processor
using direct
memory
access

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 A communication pathway Signals transmitted by any
connecting two or more one device are available for
devices reception by all other
• Key characteristic is that it is a
shared transmission medium
devices attached to the bus
• If two devices transmit during the I
same time period their signals will
overlap and become garbled n
n
e
Typically consists of multiple t
communication lines Computer systems contain a
number of different buses B c
e
• Each line is capable of that provide pathways
transmitting signals representing
binary 1 and binary 0 between components at
various levels of the
computer system hierarchy u t
r
s i
c
System bus
• A bus that connects major The most common computer o
computer components (processor,
memory, I/O) interconnection structures o
n
are based on the use of one
or more system buses

n
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+
Bus Interconnection

 A bus is a communication pathway connecting two or more

devices.

 A key characteristic of a bus is that it is a shared transmission

medium. Multiple devices connect to the bus, and a signal
transmitted by any one device is available for reception by
all other devices attached to the bus.

 If two devices transmit during the same time period, their

signals will overlap. Thus, only one device at a time can
successfully transmit.

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+
Bus Interconnection
 A Typically, a bus consists of multiple communication lines;
each line is capable of transmitting signals representing
binary 1 and binary 0.

 Over time, a sequence of binary digits can be transmitted

across a single line.

 several lines of a bus can be used to transmit binary digits

simultaneously (in parallel). For example, an 8- bit unit of
data can be transmitted over eight bus lines.

 A system bus : connects major computer components

(processor, memory, I/O). Three type of system bus are
available: Data bus, Address bus, and Control bus.

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 Data Bus
 Data lines that provide a path for moving data among system
modules

 May consist of 32, 64, 128, or more separate lines

 The number of lines is referred to as the width of the data bus

 The number of lines determines how many bits can be

transferred at a time

 The width of the data bus

is a key factor in
determining overall
system performance

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+ Address Bus Control Bus

 Used to label the source or

destination of the data on the  Used to control the access and the
data bus use of the data and address lines
 If the processor wishes to
read a word of data from  Because the data and address lines
memory it puts the address of are shared by all components there
the desired word on the must be a means of controlling their
use
address lines
 Control signals transmit both
 Width determines the maximum command and timing information
possible memory capacity of the among system modules
system
 Timing signals indicate the validity
 Also used to address I/O ports of data and address information
 The higher order bits are
used to select a particular  Command signals specify operations
module on the bus and the to be performed
lower order bits select a
memory location or I/O port
within the module
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 CPU Memory Memory I/O I/O

Control lines

Address lines Bus

Data lines

Figure 3.16 Bus Interconnection Scheme

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+
Peripheral Component
Interconnect (PCI)
 A popular high bandwidth, processor independent bus that
can function as peripheral bus

 Provides better system performance for high speed I/O

subsystems

 PCI Express (PCIe)

 Point-to-point interconnect scheme intended to replace bus-based
schemes such as PCI
 Key requirement is high capacity to support the needs of higher
data rate I/O devices, such as Gigabit Ethernet
 Another requirement deals with the need to support time
dependent data streams

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+ Summary
A Top-Level View of
Chapter 3 Computer Function
and Interconnection
 Computer components
 Computer function
 Instruction fetch and
execute
 Interrupts
 I/O function
 Interconnection structures
 Bus interconnection

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