Ch.

6 Study 8 Bit Microcontroller Applications

PIC

• PIC is an abbreviation used for Peripheral Interface Controller.

• PIC microcontroller is the smallest microcontroller in the world and are programmed to execute
large number of operations.

• PIC microcontrollers hold the ability of faster execution of programs than microcontrollers.

• It was invented in 1989 by microchip technology corporation and was an 8-bit microcontroller.

• Microchip Inc. has developed the PIC18 series of microcontrollers for use in high-pin count, high-
density, and complex applications.

• The PIC18F microcontrollers offer costefficient solutions for general purpose applications written in
C that use a real-time

• operating system (RTOS) and require a complex communication protocol stack such as TCP/IP,
CAN, USB, or ZigBee

Basic features of PIC18F-Series Microcontrollers

• 77 instructions

• PIC16 source code compatible

• Program memory addressing up to 2Mbytes

• Data memory addressing up to 4Kbytes

• DC to 40MHz operation

• 8 x 8 hardware multiplier

• Interrupt priority levels

• 16-bit-wide instructions, 8-bit-wide data path

• Up to two 8-bit timers/counters

• Up to three 16-bit timers/counters

Architecture of PIC18XX Family

1.CPU (Central Processing Unit):

• PIC microcontroller’s CPU consists of

A. Arithmetic logic unit (ALU)

B. Memory unit (MU)

C. Control unit (CU)

D. Accumulator

• ALU is used for arithmetic operations and for logical decisions.

• Memory is used for storing the instructions after processing.

• Control unit is used to control the internal and external peripherals which are connected to the
CPU

• Accumulator is used for storing the results

A. Arithmetic logic unit (ALU)

• The ALU gets one of the input operand from W register (WREG) or the IR (in case of immediate
addressing mode).

• The other operand may be given either from a register or a memory location, and hence the other
input side of ALU is connected to the internal data bus.
• For transfer of data, ALU is not required.

• The task of ALU is to perform arithmetic and logical operations.

• The task of data transfer is carried out by the control unit by issuing various control signals

2. CPU Registers : Total 7 registers

• Working Register (WREG)

• Status Register

• File Selection Register (FSR)

• Indirect Through FSR (INDF)

• Program Counter Latch Higher (PCLATH)

• Program Counter Low Byte (PCL)

• Program Counter Latch Upper (PCLATU)

• Program Counter Stack

A. Working Register (WREG)

• The WREG (Working Register) Register is one of the most widely used registers of the PIC.

• 8-bit register any data larger than 8 bits must be broken into 8-bits chunks before it is processed.

• There is only one.

• To Moves 8-bit data into WREG (00H ≤ k ≤ FFH) & Move literal value k into
WREG (WREG = k)
Example:

• MOVLW 25H  WREG = 25H

• MOVLW 5AH  WREG = 5AH

A. Working Register (WREG)

• Values can be loaded directly into the WREG.

• If values 0 to F are moved into an 8-bit register such as WREG, the rest of the bits are assumed to
be all zeros.
• Moving a value larger than 255 (FF in hex) into the WREG register will truncate the upper byte and
cause a warning in the .err file.

Ex. MOVLW 7F2H; Illegal , becomes F2H

• Add literal value k to WREG (WREG = WREG + k)

Ex.

MOVLW 12H  WREG = 12H

ADDLW 16H  WREG = 28H

B. Status Register

• To indicate arithmetic conditions

• It is a 8-bit register

• Five bits are used

D0: C Carry Flag

D1: DC Digital Carry Flag

D2: Z Zero Flag

D3: OV Overflow Flag

D4: N Negative Flag

D5, D6 & D7 are not implemented & reserved for future used

C. Stack

• PIC18CXX8 has a 21-bit stack with 31 levels, or in other words, a group of 31 memory locations, 21
bits wide, with special purpose.

• Its basic role is to keep the value of program counter after a jump from the main program to an
address of a subprogram.
• In order for a program to know how to go back to the point where it started from, it has to return
the value of a program counter from a stack.

• When moving from a program to a subprogram, program counter is being pushed onto a stack

• When executing instructions such as RETURN, RETLW or RETFIE which were executed at the end of
a subprogram, program counter will be taken from a stack so that program will continue where was
stopped before it was interrupted.

• These operations of placing on and taking off from a program counter stack are called PUSH and
POP, and are named according to similar instructions on some bigger microcontrollers.

3. Data Memory

• The data memory address bus is 12 bits with the capability to address up to 4Mbytes.

• The memory in general consists of sixteen banks, each of 256 bytes, where only 6 banks are used.

• The PIC18F452 has 1536 bytes of data memory (6 banks 256 bytes each) occupying the lower end
of the data memory.

• Bank switching happens automatically when a high-level language compiler is used, and thus the
user need not worry about selecting memory banks during programming.

4. Program Memory

• Program memory addresses consist of 21 bits, capable of accessing 2Mbytes of program memory
locations.

• The PIC18F452 has only 32Kbytes of program memory, which requires only 15 bits.

• The remaining 6 address bits are redundant and not used.

• A table pointer provides access to tables and to the data stored in program memory.

• The program memory contains a 31-level stack which is normally used to store the interrupt and
subroutine return addresses.

5. PWM Mode

• The pulse width modulation (PWM) mode produces a PWM output at 10-bit resolution.

• A PWM output is basically a square waveform with a specified period and duty cycle.

• The module is controlled by Timer 2. The PWM period is given by:

Where

PR2 is the value loaded into Timer 2 register

TMR2PS is the Timer 2 prescaler value

TOSC is the clock oscillator period (seconds)

The PWM frequency is defined as 1/(PWM period).

• The resolution of the PWM duty cycle is 10 bits.

• The PWM duty cycle is selected by writing the eight most significant bits into the CCPR1L register
and the two least

Steps for Programming CCP Module for PWM Generation

• Set the PWM period by writing to the PR2 register

• Set PWM duty cycle by writing to the CCPR1L register and CCP1CON <5:4> bits

• Make the CCP1 pin an output by clearing the TRISC<2> bit

• Set the TMR2 prescale value and enable Timer 2 by writing to T2CON

• Configure the CCP1 module for PWM operation

Speed Control of DC Motor using PWM Mode of CCP Module

• A DC motor works by converting electric power into mechanical work.

• This is accomplished by forcing current through a coil and producing a magnetic field that spins the
motor.

• The speed of the motor is dependent on the voltage given to it.

• Hence by varying the voltage to DC motor we can control the speed of DC motor.

• This is mainly implemented by PWM (Pulse Width Modulation)

• In PWM, a variation in the duty cycle generates variation in the average DC voltage.

• Pulse Width Modulation (PWM) is one of the methods to provide Digital to Analog Conversion, by
controlling the duty cycle of the square wave provided at the output the average voltage varies and
hence a DC voltage at the output of the filter available is dependent on the pulse width (counter
digital value).

• A RC circuit provides filtering and gives the average DC voltage proportional to the count as shown
fig (a)
• The Fig (b) shows how it can be used to turn on a LED and then to control its intensity by varying
the voltage (inversely proportional) across it.

• The Fig (c) shows how it can be used to turn on a DC motor and then to control its speed by varying
the voltage across it.

Features of Atmega 328P

1. High performance, low power AVR® 8-bit microcontroller

2. Advanced RISC architecture

• 131 powerful instructions - most single clock cycle execution

• 32 × 8 general purpose working registers

• Up to 16MIPS throughput at 16MHz

• On-chip 2-cycle multiplier

3. High endurance non-volatile memory segments

• 32K bytes of in-system self-programmable flash program memory

• 1Kbytes EEPROM

• 2Kbytes Internal SRAM

4. Peripheral features

• Two 8-bit Timer/Counters with separate prescaler and compare mode

• One 16-bit Timer/Counter with separate prescaler, compare mode, and capture mode

• Real time counter with separate oscillator

• Six PWM channels

• 8-channel 10-bit ADC in TQFP and QFN/MLF package

5. I/O and packages

• 23 programmable I/O lines

• 32-lead TQFP, and 32-pad QFN/ML

6. Operating voltage:

• 2.7V to 5.5V for ATmega328

7. Temperature range:

• Automotive temperature range: -40°C to +125°C

8. Speed grade:
• 0 to 8MHz at 2.7 to 5.5V (automotive temperature range: -40°C to +125°C)

• 0 to 16MHz at 4.5 to 5.5V (automotive temperature range: -40°C to +125°C)

9. Low power consumption

• Active mode: 1.5mA at 3V-4MHz

• Power-down mode: 1μA at 3V

Architecture of Atmega 328P : AVR Core

• In order to maximize performance and parallelism, the AVR uses a Harvard architecture with
separate memories and buses for program and data.

• Instructions in the program memory are executed with single-level pipelining.

• While one instruction is being executed, the next instruction is pre-fetched from the program
memory.

• This concept enables instructions to be executed in every clock cycle.

• The program memory is In-System Reprogrammable Flash memory.

Architecture of Atmega 328P : ALU

• The ALU supports arithmetic and logic operations between registers or between a constant and a
register.

• Single clock cycle access time allows single-cycle ALU operations.

• In a typical ALU operation, two operands are output from the Register file, the operation is
executed and the result is stored back in the Register file in one clock cycle.

• Single register operations can also be executed in the ALU.

• After an arithmetic operation, the Status register is updated to reflect information about the result
of the operation.

• Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space.

• Most AVR instructions have a single 16-bit word format.

• Every program memory address contains a 16- or 32-bit instruction.

AVR General Purpose Register

• The AVR® register file structure is optimized for the AVR Enhanced Reduced Instruction Set
Computer (RISC) instruction set.
• In order to achieve the required performance and flexibility, the following I/O schemes are
supported by the register file:

1. One 8-bit output operand and one 8-bit result input.

2. Two 8-bit output operands and one 8-bit result input.

3. Two 8-bit output operands and one 16-bit result input.

4. One 16-bit output operand and one 16-bit result input.

• Most of the instructions operating on the register file have direct access to all registers and most of
them are single cycle instructions.

• Each register is also assigned a data memory address, mapping them directly into the first 32
locations of the user data space

AVR Registers X,Y & Z

• Registers R26 through R31 have some added functions to their general purpose usage.

• These registers are 16-bit address pointers for indirect addressing of the data space.

• The three indirect address registers (X, Y, and Z) are defined as described in the figure.

AVR Status Register

• The status register is an 8-bit register in the microcontroller's I/O memory space.

• It contains 8 flags that are updated based on the results of the previous instruction.

• C : Carry Flag: It indicates a carry in an arithmetic or logic operation.

• Z : Zero Flag: It indicates a zero result in an arithmetic or logic operation.

• N : Negative Flag: The Negative Flag, N, indicates a negative result in an arithmetic or logic
operation.

• V : Two's Compliment Overflow Flag: The Two’s Complement Overflow Flag, V, supports two’s
complement arithmetic.

• S : Sign Flag : The S-bit is always an exclusive or between the Negative Flag and the Two’s
Complement Overflow Flag.
• H : Half Carry Flag: It indicates a half carry in some arithmetic operations. It is useful in Binary Code
Decimal (BCD) arithmetic.

• T : Copy Storage: The Bit Copy instructions Bit Load (BLD) and Bit Store (BST) use the T-bit as a
source or destination for the operated bit

• I : Global Interrupt Enable: This bit must be set for the interrupts to be enabled. The individual
interrupt enable control is then performed in separate control registers.

AVR Stack Pointer

• The stack is mainly used for storing temporary data, local variables, and return addresses after
interrupts and subroutine calls.

• It is implemented as growing from higher to lower memory locations.

• The Stack Pointer register always points to the top of the stack;

• It points to the data SRAM stack area where the subroutine and interrupt stacks are located.

• The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits
actually used depends on the implementation.

• Stack Instruction Set

• A stack PUSH command will decrease the Stack Pointer.

• The stack in the data SRAM must be defined by the program before any subroutine calls are
executed or interrupts are enabled.

• The initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer
must be set to point above the start of the SRAM.

AVR Memory Access & Instruction Execution Timing

• The AVR Central Processing Unit (CPU) is driven by the CPU clock clkCPU, directly generated from
the selected clock source for the chip.

• No internal clock division is used.

• Parallel instruction fetches and instruction executions are enabled by the Harvard architecture and
the fast-access register file concept.

• This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique
results for functions per cost, functions per clocks, and functions per power-unit.

• The Parallel Instruction Fetches and Instruction Executions

• In a single clock cycle, an Arithmetic Logic Unit (ALU) operation using two register operands is
executed and the result is stored back to the destination register.

• Single Cycle ALU Operation

Atmega 328P Pin Configuration

ATmega328P Memory Organization

Flash Program Memory

• The ATmega328P contains 32Kbytes On-chip In-

System Reprogrammable Flash memory for

program storage.

• Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 16K x 16.

• For software security, the Flash Program memory space is divided into two sections, Boot Loader
Section and Application Program section.

• The Flash memory has an endurance of at least 10,000 writes/erase cycles.

• The ATmega328P Program Counter (PC) is 14 bitswide and addresses the 16K program memory
locations.

• The Range of memory address for ATmega328P Flash Memory is 0x0000 – 0x3FFF.

SRAM Data Memory

• Data can be accessed through the standard data bus (Load/Store Instructions).

• There is a secondary In/Out Bus for rapid direct access to select locations.

• The ATmega328P is a complex microcontroller with more peripheral units than can be supported
within the 64 locations reserved in the Opcode for the IN and OUT instructions.

• For the Extended I/O space from 0x60 – 0xFF in SRAM, only the ST/STS/STD (Store) and
LD/LDS/LDD (Load) instructions can be used.

• The IN/OUT data bus has direct access to the 64- byte I/O Memory section (not Extended) using a

0x00 to 0x1F address.

• This memory can also be accessed by the standard data bus using a 0x20 address offset in the
acces command.
• There are five different data bus addressing modes for the data memory:

1. Direct – The direct addressing reaches the entire data space.

2. Indirect – In the Register File, registers R26 to R31 feature the indirect addressing pointer
registers.

3. Indirect with Displacement – The Indirect with Displacement mode reaches 63 address locations
from the base address given by the Y or Z register.

4. Indirect with Pre-decrement – The address registers X, Y, & Z are decremented

5. Indirect with Post-increment – The address registers X, Y, & Z are incremented

EEPROM Data Memory

• The ATmega328P contains 1Kbytes of data EEPROM memory.

• It is organized as a separate data space, in which single bytes can be read and written.

• The EEPROM has an endurance of at least 100,000 writes/erase cycles.

• The access between the EEPROM and the CPU is performed using the EEPROM Address Registers,
the EEPROM Data Register, and the EEPROM Control Register.

• The EEPROM Access Registers are accessible in the I/O space.

LCD Interfacing AVR (ATmega328P)

• LCDs (Liquid Crystal Displays) are used for displaying status or parameters in embedded systems.

• LCD 16x2 is a 16-pin device that has 8 data pins (D0-D7) and 3 control pins (RS, RW, EN).

• The remaining 5 pins are for the supply and backlight for the LCD.

• The control pins help us configure the LCD in command mode or data mode.

• They also help configure read mode or write mode & also when to read or write.

• LCD 16x2 can be used in 4-bit mode or 8-bit mode depending on the requirement of the
application.

• In order to use it we need to send certain commands to the LCD in command mode and once the
LCD is configured according to our need, we can send the required data in data mode.

ATmega328P based remote temperature monitoring with LCD Display

• This circuit is developed using “LM35”, a linear voltage sensor.

• Temperature is usually measured in “Centigrade” or “Faraheite”.

• “LM35” sensor provides output based on scale of centigrade.

• LM35 is three pin transistor like device.

• It has VCC, GND and OUTPUT.

• This sensor provides variable voltage at output based on temperature.

• For every +1 centigrade raise in temperature there will be +10mV higher output.

• So if the temperature is 0◦centigrade the output of sensor will be 0V, if the temperature is 10◦
centigrade the output of sensor will be +100mV, if the temperature is 25◦ centigrade the output of
sensor will be +250mV.

• So for now with LM35 we get temperature in the form of variable voltage.

• This temperature dependent voltage is given as input to ADC (Analog to Digital

Converter) of ATMEGA32A.

89v51 based Clock Using I2C RTC

• I2C : Inner Integrated Circuit RTC : Real Time Clock Features of I2C RTC DS12887

• Binary or BCD representation of time, calendar, and alarm

• 12– or 24–hour clock with AM and PM in 12–hour mode

• Daylight Savings Time option

• Selectable between Motorola and Intel bus timing

• Multiplex bus for pin efficiency

• Interfaced with software as 128 RAM locations

14 bytes of clock and control registers

114 bytes of general purpose RAM

Features of I2C RTC DS12887

• Programmable square wave output signal

• Bus–compatible interrupt signals (IRQ)

• Three interrupts are separately software–maskable and testable

 Time–of–day alarm once/second to once/day

 Periodic rates from 122 μs to 500 ms

 End of clock update cycle