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Instruction Formats and Addressing Modes

The document presents various instruction formats including three-address, two-address, one-address, and zero-address formats, along with examples. It also details different addressing modes such as implied, immediate, register, and several others. The content is prepared by Dr. Zubair Ahmad Shah from the Department of Computer Science and Engineering at the Islamic University of Science and Technology.

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14 views9 pages

Instruction Formats and Addressing Modes

The document presents various instruction formats including three-address, two-address, one-address, and zero-address formats, along with examples. It also details different addressing modes such as implied, immediate, register, and several others. The content is prepared by Dr. Zubair Ahmad Shah from the Department of Computer Science and Engineering at the Islamic University of Science and Technology.

Uploaded by

wbmsheikh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Instruction Formats

and
Addressing Modes

Slides prepared by:


Dr. Zubair Ahmad Shah
Department of Computer Science and Engineering
Islamic University of Science and Technology, Awantipora
Instruction Formats
• Three-Address Instruction Format
• Two-Address Instruction Format
• One-Address Instruction Format
• Zero-Address Instruction Format

Slides by Dr. Zubair Ahmad Shah, Dept. of CSE, IUST


Example: (A + B) * (C + D)

• Three-Address Instructions:

• Two-Address Instructions:

Slides by Dr. Zubair Ahmad Shah, Dept. of CSE, IUST


Example: (A + B) * (C + D)

• One-Address Instructions:

• Zero-Address Instructions:

TOS: Top of Stack


Slides by Dr. Zubair Ahmad Shah, Dept. of CSE, IUST
Example: (A + B) * (C + D)

• RISC Instructions:

Slides by Dr. Zubair Ahmad Shah, Dept. of CSE, IUST


Addressing Modes
1. Implied Mode: The operands are specified implicitly in the definition of
instruction (Example: Zero Address Instructions).

2. Immediate Mode: The operand is specified in the instruction itself.

3. Register Mode: The instruction specifies a register in the CPU that is holding the
operand.

4. Register Indirect Mode: The instruction specifies a register in the CPU whose
contents give the address of the operand in the memory.

5. Autoincrement mode: This is similar to register indirect mode except that the
register is incremented after its value is used to access memory.

6. Autodecrement mode: This is similar to register indirect mode except that the
register is decremented before its value is used to access memory.

Slides by Dr. Zubair Ahmad Shah, Dept. of CSE, IUST


Addressing Modes Cont.

7. Direct Address Mode: The effective address is equal to the address part of the
instruction.

8. Indirect Address Mode: The address field of the instruction gives the address
where the effective address is stored in memory.

9. Relative Address Mode: The content of the program counter is added to the
address part of the instruction in order to obtain the effective address.

10. Indexed Addressing Mode: The content of an index register is added to the
address part of the instruction in order to obtain the effective address.

11. Base Register Addressing Mode: The content of a base register is added to the
address part of the instruction in order to obtain the effective address.

Slides by Dr. Zubair Ahmad Shah, Dept. of CSE, IUST


Numerical Example

Slides by Dr. Zubair Ahmad Shah, Dept. of CSE, IUST


REFERENCE
Morris Mano, Computer System Architecture,
Prentice-Hall of India.

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