SW Development for Altera SoC

Devices Workshop
 Altera SW SoC Workshop Series

SW Workshop #1 – Altera SoC SW Development Overview

SW Workshop #2 – Introduction to Linux on Altera SoC
SW Workshop #3 – Developing Drivers for Altera SoC Linux

2
Welcome. Here’s What You Can Expect Today

An SoC SW development quick-start to quickly evaluate the SoC tool flow

 SoCEDS tool suite and debug capbility
 Tool chain for bare metal development
 Hands-on lab to test drive the development tools
An overview of the SoC HW for SW developers
An overview the SoC SW ecosystem
A useful lead-in to the detailed SoC SW training
A Take-home lab where you will use the SoC SW development tools
 Agenda

Informational Resources
Overview of SoC Features
Software Development flow
Supported OS
Linux support overview
SD Card manipulation
System console.
LAB overview

4
 Information Resources

5
 Essential Altera Training

Designing with an ARM-based SoC

 Essential introduction for SoC HW development
 http://www.altera.com/education/training/courses/ISOC101

Developing Software for an ARM-based SoC

 Essential introduction for SoC SW development
Instructor-led Training
In-person interaction  http://www.altera.com/education/training/courses/ISOC102
1 day long
Introduction to the Qsys System Integration Tool
 ILT: http://www.altera.com/education/training/courses/IQSYS101
 OLT: http://www.altera.com/education/training/courses/OQSYS1000

Advanced Qsys System Integration Tool

Virtual Classes Methodologies
 ILT: http://www.altera.com/education/training/courses/IQSYS102
Live interaction over
Webex  OLT: http://www.altera.com/education/training/courses/OQSYS2000
½ day sessions
ILT: instructor-led training
OLT: free online training
6
 Learn More Through Technical Training

Instructor-Led Virtual Classroom Online

Training Training Training

With Altera's instructor-led

With Altera's online training
training courses, you can:
With Altera's virtual courses, you can:
 Learn from an experienced Altera technical classroom training:
training engineer (instructor)  Take a course at any time that is
 Get the best of both worlds! convenient for you
 Complete hands-on exercises with
guidance from an Altera instructor  All the benefits of a live,  Take a course from the comfort of your
instructor-led training class home or office (no need to travel as with
 Ask questions and receive real-time instructor-led courses)
from the comfort of your home
answers from an Altera instructor
or office  Each online course takes approximate
 Each instructor-led class is one or two days one to three hours to complete
in length (8 working hours per day)

http://www.altera.com/training
2 for 1 Training Special for Today’s Class

7
 Essential SoC Software Tools Online Videos

ARM DS-5 Altera Edition Toolchain

 https://youtu.be/HV6NHr6gLx0
DS-5 Altera Edition: Bare-metal Debug and Trace
 https://youtu.be/u_xKybPhcHI
DS-5 Altera Edition: FPGA-adaptive Linux Kernel Debug and Trace
 https://youtu.be/lrR-SfVZd18
Debugging Linux applications on the Altera SoC with ARM DS-5
 https://youtu.be/ZcGQEjkYWOc
FPGA-adaptive debug on the Altera SoC using ARM DS-5
 https://youtu.be/2NBcUv2TxbI
Streamline Profiling on Altera SoC FPGA. Part 1 - Setup
 https://youtu.be/X-k9lmXQTio
Streamline Profiling on Altera SoC FPGA. Part 2 - Running Streamline
 https://youtu.be/Tzbd7qldKqY

8
 Essential SoC Hardware Documentation Resources

Hard Processor System Technical Reference Manuals

 Available in Device Handbooks:
http://www.altera.com/literature/lit-cyclone-v.jsp
http://www.altera.com/literature/lit-arria-v.jsp
http://www.altera.com/literature/lit-arria-10.jsp
 Peripheral Functional Descriptions
 Control Register Address Map and Definitions

HPS SoC Boot Guide

 AN709 - HPS SoC Boot Guide

ARM Documentation Site

 Documentation available for all ARM IP
Cortex-A9 & A53 MP Cores, FPU, NEON, GIC, ARM Peripherals, etc.
 Requires free registration
 Refer to HPS TRM for IP core names and revision information
 http://infocenter.arm.com/help/index.jsp

9
 Essential SoC Software Documentation Resources

Altera SoC Embedded Design Software (SoCEDS) Tools

http://www.altera.com/literature/lit-soc.jsp
 User Guide:
Getting Started Guides: Preloader, Linux, Bare Metal, Debug, HW Library
Linux & Baremetal Software Development Tools Overview
HPS Preloader User Guide
HPS Flash Programmer User Guide
SD Card Boot Utility
http://www.altera.com/literature/ug/ug_soc_eds.pdf
 SoC HPS Release Notes
 SoC Abstraction Layer (SoCAL) API Reference
<SoC EDS install dir>/ip/altera/hps/altera_hps/doc/socal/html/index.html
 Hardware Manager API Reference
<SoC EDS install dir>/ip/altera/hps/altera_hps/doc/hwmgr/html/index.html
 GCC Documentation
<SoC EDS install dir>/ds-5/documents/gcc/getting_started.html

10
 SoC Device Overview

11
 Altera Investment in Embedded Technologies

Altera established Austin Technology Center (ATC) in 2011

Altera’s primary embedded engineering center

Austin provides access to one of the richest embedded

processing talent bases in the world

12
 Altera SoC Product Portfolio
LOW END SoCs MID RANGE SoCs HIGH END SoCs
(Lowest Power, Form Factor & Cost) (High Performance with Low Power, Form Factor & Cost) (Highest Performance & System Bandwidth)
HIGH PERFORMANCE

• 14nm Intel Tri-Gate

• 64-bit Quad ARM A53 MP
CoreTM
• Optimized for Max
Performance per Watt
• 20nm TSMC • Over 4000 KLE
• 1.5 GHz Dual ARM
CortexTM-A9 MPCoreTM
• 17G Transceivers
• 28nm TSMC • 1333 MHz DDR4
• 1.05 GHz Dual ARM • Up to 660 KLE
CortexTM-A9 MPCoreTM • Up to 3356 Multipliers
• 10G Transceivers (18x19)
LOW POWER

• 28nm TSMC • 533 MHz DDR3

• 925 MHz Dual ARM • Up to 462 KLE
CortexTM-A9 MPCoreTM • Up to 2136 Multipliers
• 5G Transceivers (18x19)
• 400 MHz DDR3
• 25 to 110 KLE
• Up to 224 Multipliers
(18x19)

DEVICE AVAILABILITY
SoC devices available across entire product portfolio …

13
ARM Public Processor Offering
Cortex-A57
Stratix 10
Cortex-A53

CORTEX-A Cortex-A17
Cortex-A15
Application Processor
Cortex-A12
Cortex-A9 Cyclone V, Arria V, Arria 10
Cortex-A8
Cortex-A5

CORTEX-R
Cortex-R7
Cortex-R5 Real-time control
Cortex-R4

CORTEX-M
Cortex-M4
Cortex-M3
Cortex-M1 Microcontroller
Cortex-M0+
Cortex-M0

SECURCORE SC000
SC100 Secure
SC300
 28nm SoC System Architecture
Processor
 Dual-core ARM® Cortex™-A9 MPCore™ processor
 Up to 5,250 MIPS (1050 MHz per core maximum)
 NEON coprocessor with double-precision FPU
 32-KB/32-KB L1 caches per core
 512-KB shared L2 cache
Multiport SDRAM controller
 DDR3, DDR3L, DDR2, LPDDR2
 Integrated ECC support
High-bandwidth on-chip interfaces
 > 125-Gbps HPS-to-FPGA interface
 > 125-Gbps FPGA-to-SDRAM interface
Cost- and power-optimized FPGA fabric
 Lowest power transceivers
 Up to 1,600 GMACS, 300 GFLOPS
 Up to 25Mb on-chip RAM
 More hard intellectual property (IP): PCIe® and
memory controllers

15
 Arria 10 HPS Block Diagram
ARM CORTEX™ – A9 MP QSPI FLASH SD / SDIO/ NAND Flash
ARM CoreSight ™ Multicore Debug/ Trace CNTRL MMC (1) (1) (2)
SECURITY
CORE 1 CORE 2
ARM Cortex – A9 ARM Cortex – A9 16550 UART SPI
I2C (X5)
MP Core MP Core (x2) (x2)
NEON SIMD FPU NEON SIMD FPU
EMAC with 8 Channel
32 KB I$/D$ w/ Parity 32 KB I$/D$ w/ Parity USB OTG (x2)
DMA (x3) DMA
POWER
MANAGEMENT 512 KB L2 CACHE (SHARED)
256 KB DEDICATED GP TIMERS
w/ ECC GPIO (17)
SCRATCH RAM (x7)
Accelerator Coherency

USER IO
Snoop Control Unit
Port
(Network SECURITY
Watch Dog
64-bit AXI Coherent Bus Interface L3 INTERCONNECT On Chip) ON CHIP
Timer (x4) MANAGER ROM

SDRAM (3)
HARD L3 INTERCONNECT (NETWORK ON CHIP)
INTERCONNECT
MEMORY
CONTROLLER FPGA to HPS SDRAM LW HPS TO CORE HPS to FPGA FPGA to HPS FPGA CONFIG
BRIDGE BRIDGE BRIDGE BRIDGE MANAGER

2 32/64/128 Port
AXI 32 AXI 32/64/128 AXI 32/64/128
1 32/64 bit Port
FPGA LOGIC
CONFIGURAT- PCIe Gen 3 X 8 Controller Hard IP
ION
PCS & FEC (Interlaaken PCS, 10G KR-FEC)
PHY
Notes:
(1) Integrated direct memory access (DMA)
(2) Integrated ECC
16
(3) DDR3/4 & LP DDR3 SDRAM Support fo HPS Memory
 High-Level Block Diagram
FPGA
HPS to FPGA Configuration
FPGA to HPS Control FPGA to SDRAM

EMAC FPGA
ARM Cortex-A9MPCore
...
HPS
(2) Config CPU0 CPU1
ARM Cortex-A9 ARM Cortex-A9
NEON/FPU NEON/FPU
USB 32 KB I$ 32 KB I$
OTG 32 KB D$ 32 KB D$
(2)

ACP
SCU
Flash
Control Multi-port
L2 Cache DDR
(512 KB) SDRAM
DMA
Interconnect Boot Controller
ROM

TMC On-chip
(Trace) RAM
64 KB

Debug
Port

Low Speed Peripherals

Timers, GPIO, UART, SPI, I2C, CAN

17
 A Comparison: Cyclone V SoC, Arria V SoC, & Arria 10 SoC
Metric Cyclone V SoC Arria V SoC Arria 10 SoC

Technology 28nm 28nm 20nm

Processor Performance 925 MHz 1.05 GHz 1.5 GHz
Total Power Dissipation 100% 100% 60% (40% Lower)
Max PCI Express Hard IP Gen 2 x4 Gen 2 x8 Gen 3 x8
DDR4/3, LPDDR2/3,
Memory Devices DDR2, DDR3, DDR2, DDR3,
QDRIV, RLDRAM III,
Supported DDR3L, LPDDR2 DDR3L, LPDDR2
Hybrid Memory Cube
Max. HPS DDR Data-
40-bit (32-bit + ECC) 40-bit (32-bit + ECC) 72-bit (64-bit + ECC)
Width
EMAC Cores EMAC x 2 EMAC x 2 EMAC x 3
NAND Device Supported 8-bit 8-bit 8-bit and 16-bit
SD/MMC devices SD/SDIO/MMC 4.5 with
SD/SDIO/MMC SD/SDIO/MMC
supported eMMC
FPGA Logic Density
25 - 110K 370 - 450K 160 - 660K
Range (LEs)
FPGA Core Performance 260 MHz 307 MHz 500 MHz

18
 Learn more about the HPS hardware

Overview
 http://www.altera.com/devices/processor/soc-fpga/overview/proc-soc-
fpga.html
SoC handbooks
 http://www.altera.com/devices/processor/soc-fpga/overview/soc-overview-
doc.html

19
Boot Process
 Altera SoC FPGA Boot & Configuration Options

SOC Device

Configuration Sources
FPGA HPS
Configuration Sources

QSPI

Boot Sources
PCIe
/SPI

QSPI CPU MMC

/SPI /SD
Boot code
(RAM/ROM)
Passive NAND
Serial Flash

Passive Config
Parallel Controller

Boot On-chip
ROM RAM
Boot User Specified I/F AXI

Source

21
 Boot Stages – Cyclone V & Arria V

General Boot Process

Reset BootROM Preloader Bootloader OS

OS or
Bare Metal
FPGA or
FLASH

22
 Boot Stages – Cyclone V & Arria V
DDR
1.Reset/boot SoC FPGA
Boot ROM

On-Chip
Pre-loader
RAM

HPS
System

Safe FPGA Image

User FPGA Image

OS &
Applications

User Bootloader

Pre-loader
Flash
23
 Boot Stages – Cyclone V & Arria V
DDR
1.Reset/boot SoC FPGA
2.Boot from ROM, Boot ROM
3.Set up boot source (BSEL pins)
On-Chip
Pre-loader
RAM

HPS
System

Safe FPGA Image

Boot
Select
User FPGA Image Pins

OS &
Applications

User Bootloader

Pre-loader
Flash
24
 Boot Stages – Cyclone V & Arria V
DDR
1.Reset/boot SoC FPGA
2.Boot from ROM, Boot ROM
3.Set up boot source
4.Copy Pre-loader to On-Chip
Pre-loader
Pre-loader
5.On-chip RAM RAM

HPS
System

Safe FPGA Image

User FPGA Image

OS &
Applications

User Bootloader

Pre-loader
Flash
25
 Boot Stages – Cyclone V & Arria V
DDR
1.Reset/boot SoC FPGA
2.Boot from ROM: Boot ROM
3.Set up boot source
4.Copy Pre-loader to On-Chip
Pre-loader
Pre-loader
5.On-chip RAM RAM
6.Run Pre-loader:
7.Set up HPS I/O and DDR HPS
System

Safe FPGA Image

User FPGA Image

OS &
Applications

User Bootloader

Pre-loader
Flash
26
 Boot Stages – Cyclone V & Arria V
DDR
1.Reset/boot SoC FPGA
2.Boot from ROM: Boot ROM
3.Set up boot source
4.Copy Pre-loader to On-Chip
Pre-loader
Pre-loader FPGA
5.On-chip RAM RAM
Config-
6.Run Pre-loader:
uration
7.Set up HPS I/O and DDR HPS
8.Configure FPGA (optional) System

Safe FPGA Image

User FPGA Image

OS &
Applications

User Bootloader

Pre-loader
Flash
27
 Boot Stages – Cyclone V & Arria V
DDR
1.Reset/boot SoC FPGA
2.Boot from ROM: Boot ROM
3.Set up boot source
4.Copy Pre-loader to On-Chip
Pre-loader
Pre-loader FPGA
5.On-chip RAM RAM
Config-
6.Run Pre-loader:
uration
7.Set up HPS I/O and DDR HPS
8.Configure FPGA (optional) System
9.Copy User Bootloader (i.e User Bootloader*
Uboot) or BM Application to
DDR Safe FPGA Image

User FPGA Image

OS &
Applications

User Bootloader

Pre-loader
Flash
28
 Boot Stages – Cyclone V & Arria V
DDR
1.Reset/boot SoC FPGA
2.Boot from ROM: Boot ROM
3.Set up boot source
4.Copy Pre-loader to On-Chip
Pre-loader FPGA
5.On-chip RAM RAM
Config-
6.Run Pre-loader:
uration
7.Set up HPS I/O and DDR HPS
8.Configure FPGA (optional) System
9.Copy User Bootloader to User Bootloader*
DDR
10.Run UserBootloader,
Safe FPGA Image
11.Configure FPGA (optional)

User FPGA Image

OS &
Applications

User Bootloader

Pre-loader
Flash
29
 Boot Stages – Cyclone V & Arria V
DDR
1.Reset/boot SoC FPGA
2.Boot from ROM: Boot ROM
3.Set up boot source
4.Copy Pre-loader to On-Chip
Pre-loader FPGA
5.On-chip RAM RAM
Config-
6.Run Pre-loader:
OS & uration
7.Set up HPS I/O and DDR Applications HPS
8.Configure FPGA (optional) System
9.Copy User Bootloader to User Bootloader*
DDR
10.Run UserBootloader,
Safe FPGA Image
11.Configure FPGA (optional)
12.Copy OS to DDR User FPGA Image

OS &
Applications

User Bootloader

Pre-loader
Flash
30
 Boot Stages – Cyclone V & Arria V
DDR
1.Reset/boot SoC FPGA
2.Boot from ROM: Dynamic Boot ROM
3.Set up boot source Memory
4.Copy Pre-loader to On-Chip
Pre-loader FPGA
5.On-chip RAM RAM
Config-
6.Run Pre-loader:
OS & uration
7.Set up HPS I/O and DDR Applications HPS
8.Configure FPGA (optional) System
9.Copy User Bootloader to User Bootloader*
DDR
10.Run UserBootloader,
Safe FPGA Image
11.Configure FPGA
(optional) User FPGA Image
12.Copy OS to DDR
13.Run OS OS &
14.Run applications Applications

User Bootloader

Pre-loader
Flash
31
 Boot Stages – Cyclone V & Arria V
DDR
1.Reset/boot SoC FPGA
2.Boot from ROM: Dynamic Boot ROM
3.Set up boot source Memory
4.Copy Pre-loader to On-Chip
Pre-loader FPGA
5.On-chip RAM RAM
Config-
6.Run Pre-loader:
OS & uration
7.Set up HPS I/O and DDR Applications HPS
8.Configure FPGA (optional) System
9.Copy User Bootloader to User Bootloader*
DDR
10.Run UserBootloader,
Safe FPGA Image
11.Configure FPGA
(optional) User FPGA Image
12.Copy OS to DDR
13.Run OS OS & *User Bootloader is
14.Run applications Applications optional. Steps 9-12
15.Configure FPGA User Bootloader optional
(optional)
Pre-loader
Flash
32
 Boot Stages – Cyclone V & Arria V

General Boot Process

Preloader
Reset BootROM SPL or Bootloader OS
MPL

OS or
Bare Metal
FPGA or
FLASH

33
 Non-Secure Boot Stages – Arria 10

General Boot Process for Non-Secure Boot Flow

 Arria 10 supports secure and non-secure boot flows

Bootloader
OS or
Reset BootROM U-Boot or
Bare Metal
UEFI

FPGA or
FLASH

Enabled by larger on-chip RAM

34
 Non-Secure Boot Stages – Arria 10
DDR
1.Reset/boot SoC FPGA
2.Boot from ROM, Boot ROM
3.Set up boot source (BSEL pins)
On-Chip
Pre-loader
RAM

HPS
System

Safe FPGA Image

Boot
Select
User FPGA Image Pins

OS &
Applications

Bootloader
U-Boot or UEFI

Flash
35
 Non-Secure Boot Stages – Arria 10
DDR
1.Reset/boot SoC FPGA
2.Boot from ROM, Boot ROM
3.Set up boot source
4.Copy Bootloader to On-Chip
Pre-loader
Bootloader
5.On-chip RAM RAM

HPS
System

Safe FPGA Image

User FPGA Image

OS &
Applications

Bootloader
U-Boot or UEFI

Flash
36
 Non-Secure Boot Stages – Arria 10
DDR
1.Reset/boot SoC FPGA
2.Boot from ROM: Boot ROM
3.Set up boot source
4.Copy Bootloader to On-Chip
Pre-loader
Bootloader
5.On-chip RAM RAM
6.Run Bootloader:
7.Set up HPS I/O and DDR HPS
System

Safe FPGA Image

User FPGA Image

OS &
Applications

Bootloader
U-Boot or UEFI

Flash
37
 Non-Secure Boot Stages – Arria 10
DDR
1.Reset/boot SoC FPGA
2.Boot from ROM: Boot ROM
3.Set up boot source
4.Copy Bootloader to On-Chip
Pre-loader
Bootloader FPGA
5.On-chip RAM RAM
Config-
6.Run Bootloader:
uration
7.Set up HPS I/O and DDR HPS
8.Configure FPGA (optional) System

Safe FPGA Image

User FPGA Image

OS &
Applications

Bootloader
U-Boot or UEFI

Flash
38
 Non-Secure Boot Stages – Arria 10
DDR
1.Reset/boot SoC FPGA
2.Boot from ROM: Boot ROM
3.Set up boot source
4.Copy Bootloader to On-Chip
Pre-loader
Pre-loader FPGA
5.On-chip RAM RAM
Config-
6.Run Bootloader:
OS & uration
7.Set up HPS I/O and DDR Applications HPS
8.Configure FPGA (optional) System
9.Copy OS to DDR

Safe FPGA Image

User FPGA Image

OS &
Applications

Bootloader
U-Boot or UEFI

Flash
39
 Non-Secure Boot Stages – Arria 10
DDR
1.Reset/boot SoC FPGA
2.Boot from ROM: Dynamic Boot ROM
3.Set up boot source Memory
4.Copy Bootloader to On-Chip
Pre-loader FPGA
5.On-chip RAM RAM
Config-
6.Run Bootloader:
OS & uration
7.Set up HPS I/O and DDR Applications HPS
8.Configure FPGA (optional) System
9.Copy OS to DDR
10.Run OS
11.Run applications
Safe FPGA Image

User FPGA Image

OS &
Applications

Bootloader
U-Boot or UEFI

Flash
40
 Non-Secure Boot Stages – Arria 10
DDR
1.Reset/boot SoC FPGA
2.Boot from ROM: Dynamic Boot ROM
3.Set up boot source Memory
4.Copy Bootloader to On-Chip
Pre-loader FPGA
5.On-chip RAM RAM
Config-
6.Run Bootloader:
OS & uration
7.Set up HPS I/O and DDR Applications HPS
8.Configure FPGA (optional) System
9.Copy OS to DDR
10.Run OS
11.Run applications
Safe FPGA Image
12.Configure FPGA
(optional) User FPGA Image

OS &
Applications

Bootloader
U-Boot or UEFI

Flash
41
 Learn more about boot and configuration process

Select the appropriate Handbook

 http://www.altera.com/devices/processor/soc-fpga/overview/soc-overview-
doc.html
 Appendix A

42
Development Flow & Tools
 Traditional System Development Flow
FPGA Design Flow Software Design Flow
Hardware Software
Development Development

• ARM Development Studio 5

• Quartus II design software
• GNU toolchain
• Qsys system integration tool HW/SW
Design Design • OS/BSP: Linux, VxWorks
• Standard RTL flow Handoff • Hardware Libraries
• Altera and partner IP
• Design Examples

• ModelSim, VCS, NCSim, etc.

• AMBA-AXI and Avalon bus Simulate Simulate • VirtualSoftware
Platform
functional models (BFMs)
Development
• SignalTap™ II logic analyzer • GNU, Lauterbach, DS5
• System Console
Debug Debug
FPGA-Adaptive
• Quartus II Programmer Debugging
Release Release • Flash Programmer
• In-system Update

44
So… what exactly is Qsys?

GUI based system integration tool for HW system design

using IP blocks.

Simplifies complex system development

Raises the level of design abstraction
Provides a standard platform:
 IP integration
 Custom IP authoring
 IP verification
Enables design re-use
Scales easily to meet the needs of end product
Reduces time to market
 Qsys System Integration Platform

High-Performance Interconnect

Hierarchy Design Reuse

Package as IP
Based on Network-on-a-Chip (NoC)
Architecture Design Add to
System Library

Automated Testbench Generation

Industry-Standard Interfaces

Avalon® Interfaces
Real-Time System Debug
®
AMBA AXI, APB, AHB
®

 Fastest way to build, modify, & optimize complex systems

 Flexibly optimize for performance or area
 Seamlessly integrate with Altera’s embedded solutions
46
 A GHRD Qsys system

 Qsys connects masters and slaves together

 And configures components
 Defines memory map
47
 Hard Processor System Component

48
 Learn more Qsys and HPS configuration

Avalon interface specification

 http://www.altera.com/literature/manual/mnl_avalon_spec.pdf

Qsys resource page

 http://www.altera.com/products/software/quartus-ii/subscription-
edition/qsys/qts-qsys.html
Configuring the HPS
 http://www.altera.com/devices/processor/soc-fpga/overview/soc-overview-
doc.html
 Choose family and “Introduction to the HPS Component” chapter

49
Software
 Traditional System Development Flow
FPGA Design Flow Software Design Flow
Hardware Software
Development Development

• ARM Development Studio 5

• Quartus II design software
• GNU toolchain
• Qsys system integration tool HW/SW
Design Design • OS/BSP: Linux, VxWorks
• Standard RTL flow Handoff • Hardware Libraries
• Altera and partner IP
• Design Examples

• ModelSim, VCS, NCSim, etc.

• AMBA-AXI and Avalon bus Simulate Simulate • VirtualSoftware
Platform
functional models (BFMs)
Development
• SignalTap™ II logic analyzer • GNU, Lauterbach, DS5
• System Console
Debug Debug
FPGA-Adaptive
• Quartus II Programmer Debugging
Release Release • Flash Programmer
• In-system Update

51
 Altera SoC Embedded Design Suite

Comprehensive Suite SW Dev Tools

Hardware / software handoff tools Hardware-to-
Software
Handoff
Bare-metal application development
 SoC Hardware Libraries

 Bare-metal compiler tools Linux

Application
Firmware
Development
Development
FPGA-adaptive debugging
 ARM DS-5 Altera Edition Toolkit

Linux application development FPGA-

Adaptive
Debugging
 Yocto Linux build environment

 Pre-built binaries for Linux / U-Boot

 Work in conjunction with the Community Portal – www.Rocketboards.org

Design examples

52
 Software Design Flow

Standard development environment HW

 ARM DS-5 and/or partner IDE Design Develop
Handoff

Standard software enablement Debug

 HWLIBs for use with or without OS
Release

Standard design flow

 No proprietary or additional tools required

Altera SoCs provide high

SW developer productivity

53
 Hardware-to-Software Handoff
Qsys system info, SDRAM calibration files,
ID / timestamp, HPS IOCSR data
Hardware

system.iswinfo system.sopcinfo
board info

Preloader Device Tree

Generator Generator

.c & .h
Linux
Software source files
Device Tree
(u-boot spl)

54
 Linux HW/SW Handoff – Arria 10 SoC

Device Tree
Generator:
sopc2dts
Board Info
Linux
DT Blob
Quartus II

Regenerate when HW project is

Hardware Handoff Different DTBs
Project Folder recompiled

Bootloader
Generator:
bsp-editor

DTC
Bootloader Bootloader
DT Source DT Blob
Board Info

mkpimage
Regenerate only when user options U-Boot
(boot source, etc.) change Image
Provided by Altera

Open Source Makefile

Input File
Make
Intermediate File
U-Boot U-Boot
Output File Src Code Binary
DS-5 Altera Edition
 ARM DS-5 Altera Edition Overview

ARM-Altera strategic partnership with

unique OEM arrangement

Low cost and included in many SoC

development kits

Complete multi-core debug and ARM

CoreSight compliant trace

Includes ARM Pro bare-metal compiler

and Altera GCC compiler

Industry-only FPGA-Adaptive debug

support

Uses USB-Blaster cable

57
 DS-5 Altera Edition- One Tool, Three Usages

1
• JTAG-Based Debugging
• Board Bring-up
• OS porting, Drivers Dev,

2 • Kernel Debug

• Application Debugging 3 • FPGA-Adaptive Debugging

• Linux User Space Code • System Integration
• RTOS App Code • System Debug

58
 One Device, Two Debugging Tools?

ARM® DS-5™ Toolkit Altera Quartus™ II Software

JTAG
DSTREAM™

 Dedicated JTAG connection JTAG

 Visualize & control CPU
 Dedicated JTAG connection
subsystem
 Visualize & control FPGA

59
 Industry First: FPGA-Adaptive Debugging

Altera
USB-Blaster™II
Connection

ARM® Development Studio 5 (DS-5™) Altera® Edition Toolkit

Removes debugging barrier between CPUs and FPGA
Exclusive OEM agreement between Altera and ARM
Result of innovation in silicon, software, and business model

60
 Visualization of SoC Peripherals

Register views assist the

debug of
FPGA peripherals
 File generated by FPGA tool flow
 Automatically imported in
DS-5 Debugger

Debug views for debug of

software drivers
 Self-documenting
 Grouped by peripheral,
register and bit-field

CMSIS

Peripheral register
descriptions
61
 FPGA-Adaptive, Unified Debugging
FPGA connected to debug and trace buses for non-
intrusive capture and visualization of signal events
Simultaneous debug
and trace connection to CPU cores
and compatible IP
Correlate
FPGA signal
events with
software events
and CPU
instruction
trace using
triggers and
timestamps

62
 Cross-Domain Debug 1

Trigger from software world to FPGA world

SOFTWARE TRIGGER

HARDWARE TRIGGER!

63
 Cross-Domain Debug 2

Trigger from FPGA world to software world

HARDWARE TRIGGER

EXECUTION STOP EXECUTION STOP

OR OR
HW TRACE TRIGGER SW TRACE TRIGGER

64
 Correlate HW and SW Events

Debug event trigger

point set from either: ARM® DS-5™ Toolkit

SignalTap™ II Logic
Analyzer
or
DS-5 debugger

Timestamp Correlated
Captured trace can
then be analyzed using SignalTap II Logic Analyzer
timestamp-correlated
events

65
 DS-5 Editions Summary
Web Subscription 30-Day
Component Key Feature
Edition Edition Evaluation
Hardware/Software
Preloader Image Generator x x x
Handoff Tools
Flash Image Creator x x x
Device Tree Generator (Linux) x x x
ARM DS-5 Altera
Eclipse IDE x x x
Edition
Debugging over Ethernet (Linux) x x x
Debugging over USB-Blaster II JTAG x x
Automatic FPGA Register Views x x
Hardware Cross-triggering x x
CPU/FPGA Event Correlation x x
Compiler Tool Chains Linaro Tool Chain (Linux) x x x
GCC EABI (Bare-metal) X x x
ARM Pro Compiler x
Hardware Libraries Bare-metal programming Support x x x
SoC Programming
Golden System Reference Design x x x
Examples

Everything needed for Linux development is free

66
 Learn more about DS-5

ARM
 http://ds.arm.com

Altera Edition
 http://www.altera.com/devices/processor/arm/cortex-a9/software/proc-arm-
development-suite-5.html
SOCEDS
 http://www.altera.com/literature/ug/ug_soc_eds.pdf

67
 SoC Physical Address Map

68
 Cyclone V & Arria V SoC HPS Physical Memory Map

L3 MPU FPGA
(Default) to SDRAM
4 GB
HPS Slaves H2F_LW HPS Slaves
0xFF20_0000 Slaves

H2F FPGA Slaves H2F FPGA Slaves

0xC000_0000 3 GB

ACP Window

0x8000_0000 SDRAM 2 GB

SDRAM SDRAM
Region Region

1 GB

Boot Region
RAM/SDRAM RAM/ROM/SDRAM
0x0000_0000 0 GB

Default remap to 0x0 Remaps as

RAM & ROM or SDRAM

69
 Arria 10 SoC HPS Physical Memory Map

L3 MPU FPGA
(Default) to SDRAM
4 GB
HPS Slaves H2F_LW HPS Slaves
0xFF20_0000 Slaves

H2F FPGA Slaves H2F FPGA Slaves

0xC000_0000 3 GB

0x8000_0000 SDRAM 2 GB

SDRAM SDRAM
Region Region

1 GB

Boot Region
RAM/SDRAM RAM/ROM/SDRAM
0x0000_0000 0 GB

Remaps as
RAM & ROM or SDRAM

70
 Arria 10 SoC HPS Physical Memory Map

FPGA to MPU FPGA

HPS Bridge to SDRAM
4 GB
HPS Slaves H2F_LW HPS Slaves
0xFF20_0000 Slaves

H2F FPGA Slaves H2F FPGA Slaves

0xC000_0000 3 GB

0x8000_0000 SDRAM 2 GB
ACP Window
SDRAM SDRAM
or
Region
SDRAM direct Region

1 GB

Boot Region
Boot Region RAM/ROM/SDRAM
0x0000_0000 0 GB

ACP/SDRAM selected
by AxCACHE
71
 Physical Address Mapping

72
 Physical Address Mapping

FPGA Masters have 4 GB

access to full 4GB of
SDRAM address space
 Subject to MPFE MPU 3 GB
restrictions
 No coherency
 No virtual addressing
SDRAM 2 GB

1 GB

0 GB

73
 Physical Address Mapping

MPU can access only lower 3

HPS Slaves
GBytes of SDRAM
H2F FPGA Slaves

3 GB

2 GB

SDRAM
Region

1 GB

0 GB

74
 Physical Address Mapping

MPU can access 960 MBytes

HPS Slaves
of FPGA address space via
HPS to FPGA Bridge H2F FPGA Slaves

MPU can access 2 MB of

FPGA address space via HPS
to FPGA Lightweight bridge
Developing Linux Drivers for
Custom Peripherals Workshop SDRAM
Region

75
 Physical Address Mapping

FPGA to HPS (F2H) HPS Slaves

masters see 4 GByte
address space H2F FPGA Slaves

F2H bandwidth to
SDRAM limited vs. ACP Window
FPGA to SDRAM bridge

SDRAM
Region

76
 Cyclone V SoC Dev. Kit Memory Map Example
LED PIO

77
 Golden Hardware Reference Design (GHRD)

Complete hardware design

 Most BSP use this design
 Simple custom logic design in
FPGA
 All source code and Quartus II /
Qsys design files for reference
 Includes JTAG Master(s) for
System Console access.
 Similar for each Board

HPS2FPGA LED PIO in FPGA

LW Bridge
78
 Cyclone V SoC Dev. Kit Memory Map Example

FPGA F2H MPU FPGA

Master to SDRAM
4 GB
HPS Slaves HPS Slaves
0xFF20_0000 H2F_LW
Slaves

H2F FPGA Slaves H2F FPGA Slaves

3 GB

ACP Window Undecoded

Undecoded 2 GB

Undecoded

1 GB

SDRAM SDRAM
Region SDRAM
Region

0 GB

Default remap to 0x0

79
 Memory Map through Qsys

led_pio is at Address 0x0001_0040 in Qsys

80
 Memory Map through Qsys

It is connected to 3 Masters

81
 Memory Map through Qsys

Each master sees the slave at a different address

 HPS master addresses offset from base location of bridge slave in HPS

ARM sees LED through the H2F

bridge
ARM
H2F sees
bridgeLED through the LW
0xC000_0000
bridge
+
H2F bridge
LED_PIO base 0xff20_0000
0x0001_0040
+
= 0xC001_0040
LED_PIO base 0x0001_0040
= 0xff21_0040

JTAG Master sees LED H2F

LED_PIO base 0x0001_0040
= 0x0001_0040

82
Altera SoC
Bare-Metal Software Development
 Software For Bare-Metal Programming

Hardware Libs (HWLIBs)

 SoC Abstraction Layer (SoCAL) – Low-Level HAL
Header files
Documentation
 Hardware Manager (HWMgr)
Adds C and some assembly language
#includes SoCAL header files

SoC Embedded Development Suite (EDS)

 IDE for development/debug of bare-metal application
 Includes tools for flash programming, boot-image generation, and
configuring and generating Preloader (Initial Program Loader)

Bare-Metal Compilers
 Altera GCC EABI Compiler
 ARM Pro compiler (also included as of SoC EDS 14.0.2)

84
 Hardware Libs Usage

NO O/S (or BM App)

 Simple executive Operating BM
 Polling Loop System
 Can use Bare-Metal tools
App
SoCAL, HW Mgr, Compiler
Low-Level O/S HW Mgr
 No device driver model
 i.e. ThreadX, uC/OS
 Can use some Bare-Metal
SoCAL, HW Mgr SoCAL
High-Level O/S
 Device Driver Model
 e.g. Linux, VxWorks
 Can use some BM tools: Processor Core
SoCAL, HW Mgr

85
 SoCAL Overview

Logical interface abstraction to a physical device or registers

Low-level HAL
 API closest to actual hardware
Decouples software from hardware
 Isolates client software from hardware changes
Designed to be used with or without an OS
Generated code
 Preprocessor macros, enum, and struct declarations
 Commented inline
Targets C and assembly language programmers
Defines programmatic access to hardware:
 HPS address space
 Hard IP components
 Peripheral registers
 Register fields
Tested with GCC and ARM Pro bare-metal compiler tool-sets

86
 Hardware Manager (HWMgr) Overview

Functional APIs that implement more complex

configuration and operational control over SoC hardware
resources
 Satisfy specific timing constraints
 Error checking through parameter constraints and validation checks
 Provides a level of precondition assertion checking
For example, checking that the FPGA is powered on and in USER mode prior
to initializing an FPGA bridge
 Provides a level of post condition assurance
For example, if the configuration of a scan chain fails

Designed to be used with or without an OS

 Open source BSD license (non GPL)
 No namespace clash
 Thread-safe

87
 APIs in HWLIBs HWMgr

MPU Subsystem Timers Cache/MMU Serial

Cache Mgmt

Memory Map Cntl Watchdog Cache Mgmt UART

Address Filters General Purpose MMU Mgmt SPI

Mem Coherence I2C

Bridge Management Flash Memory
CAN
FPGA2HPS QSPI
FPGA Manager
HPS2FPGA NAND Minimal Preloader
Full Configuration
LWHPS2FPGA SD/MMC Interrupt Ctrl

Pin I/O Cnf Mgmt

Clock Manager System Manager GPIO ECC Mgmt
Reset Manager SDRAM Ctrl DMA Parity Mgmt

SoCAL Layer (non ARM IP)

Current Future rel.

88
 Software Delivery

HWLIBs and Bare-Metal application development

components are included with SoC Embedded
Development Suite (SoC EDS)

SoC EDS is distributed through the Altera Download

Center

Updates for HWLIBs are also be available between SoC

EDS releases
 See Altera.com -> Download Center -> “SoC RTOS and HWLIBs Support”

89
 HWLIB Examples

Hello World
UART/Interrupt processing
FPGA Programming
Error Correction Code (ECC)
Web Server/Ethernet LWIP (through codetime.com)
Minimal Preloader (MPL) – Non-GPL Preloader
Many more examples available to download
http://www.altera.com/support/examples/soc/soc.html

90
 HWLIB Examples – Minimal Preloader (MPL)

Non-GPL bootloader for Cyclone V and Arria V

Replaces default GPL Preloader
UEFI-based preloader will be available for Arria 10

Runs in Preloader boot stage

First programmable image loaded by bootrom

Loads the next stage bootloader or executable image

Typically loads a bootloader or IPL (Initial Program Loader)
Can load image from QSPI Flash or SD/MMC Flash
Boot from FPGA option coming soon.

Configures clocks, PLLs, memory controller, IOCSR

Distributed as HWLIBs example starting in SoC EDS
14.0.1

91
 Learn More

SOCEDS
 http://www.altera.com/literature/ug/ug_soc_eds.pdf
 Bare metal compilers
 Hardware libraries
 http://www.altera.com/devices/processor/soc-fpga/overview/soc-overview-
sw.html

HWLIBS
 https://www.altera.com/download/soc-eds/rtos-tools.jsp

HWLIBS examples
 http://www.altera.com/support/examples/soc/soc.html

92
Altera SoC Linux Overview
 Linux for Altera SoCs

High Quality Linux Support

Modern release strategy

Multiple Kernel Versions

Community Enablement

94
 Altera SOC Linux Provides Customers Kernel Choices

2014 2015 2016

Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar

Altera SoC Linux supports the latest stable kernel

3 mos 3 mos 3 mos 3 mos 3 mos 3 mos

NEW – Altera SoC Linux also supports LTSI kernel

LTSi
v3.10
24 months

LTSI kernel available with or without Preempt Real Time Patches

95
 Industry-leading Linux support

Altera keeps up with the Linux community

 Kernel is upgraded every 3 months against every new kernel.org release
 Altera is the maintainer for the SoCFPGA architecture folder (mach-socfpga)
Altera maintains the LTSI kernel
 Altera SOC Linux LTSI v3.10, more stable code base for 24 months
 Fixes, improvements and new features back-ported from latest kernel
 Seamless transition to commercial Linux vendors, Wind River, etc.
Altera’s SoC drivers have high quality
 Altera SoC Hard IP acquired from EDA vendors, use community Linux drivers
 Altera SoC Linux drivers used by many SOC vendors, therefore drivers have
more support and higher quality
 Altera upstreams fixes and improvements to code to the kernel and U-boot
Altera supports a modern release strategy
 Updates Public GIT trees every 2 weeks – complete transparency
 Published on community site: See git.rocketboards.org
 See the NEWS section of RocketBoards.org latest updates

96
 Altera SoC Linux Support Model

Rocketboards.org
 SoC & Nios II Linux documentation
 SoC & Nios II SoC Linux reference & example designs

Rocketboards.org RFI & Linux Community

 Kernel/RFS/u-boot questions
 SoC/Nios II subsystem and driver questions

Altera.com and Rocketboards.org

 SoCEDS & Quartus/QSys documentation and questions
 SoC Preloader questions
 SoC HPS implementation specific questions
 Use myAltera for service requests

Support from Altera is focused on SoCFPGA and NiosII

Linux Board Support Package
Altera enables Linux development on SoCFPGA & Nios II

97
 Linux Resources

98
 Linux Documentation Resources

GIT
 Distributed revision control system to enable distributed collaboration
 On-line documentation & training:
http://git-scm.com/doc
https://training.github.com

Denx U-Boot Manual

 Complete documentation from the folks who wrote Das U-Boot
http://www.denx.de/wiki/U-Boot/Documentation

Free-Electrons:
 Complete training materials posted free
http://free-electrons.com/docs/

Device Tree for Dummies

 http://events.linuxfoundation.org/sites/events/files/slides/petazzoni-device-tree-
dummies.pdf

99
 Linux Documentation Resources

Yocto Project
 https://www.yoctoproject.org/documentation

Angstrom Distribution
 http://www.angstrom-distribution.org/

Open Embedded
 http://www.openembedded.org/wiki/Main_Page

100
 The Two Best Sources for Linux Development Information

Linux Kernel Documentation

 The most complete and most essential Linux kernel documentation
 Included with the Linux kernel source code
<local GIT repo>/Documentation

101
 The Two Best Sources for Linux Development Information

An open source OS breeds open source information

102
 RocketBoards.org – Altera SoC Linux Community Portal

The source for SoC FPGA Linux info

 Golden System Reference Design (GSRD)
 Updates on latest releases
 Step-by-step getting started guides
SoC FPGA Mailing List - RFI
 Active community participation in answering SoC FPGA and
Linux questions
Example Projects, Applications, and Designs
 From Altera and the SoC community
Enables the SoC community to support Linux

103
 Learn More about SoCFPGA Linux

SW Workshop #1 – Altera SoC SW Development Overview

SW Workshop #2 – Introduction to Linux on Altera SoC
SW Workshop #3 – Developing Drivers for Altera SoC
Linux

104
Altera SoC
Operating System Support
 Embedded OS Availability

Development
Vendor OS/RTOS Available From
Tools
Open Source Linux (current and 3.10 LTSI) Linaro compiler rocketboards.org
Wind River Systems VxWorks 6.9.3 and 7.0 Wind River Workbench Wind River
Micriµm µC/OS-II, µC/OS-III GNU compiler Micriµm
Enea OSE 5.5.3 Optima 2.6 ENEA
Express Logic ThreadX G5.5.5.0 GNU compiler Express Logic
Wind River Systems Wind River Linux 5 and 7 Workbench/GNU Wind River
QNX QNX/Neutrino 6.5.3 and 6.6 Momentics QNX
Fujisoft Android GNU compiler Fujisoft
Green Hills INTEGRITY Multi/Green Hills Green Hills
DDC-I Deos DDC-I DDC-I
Code Time Multicore Abassi ARMCC/GCC Code Time
Mentor Nucleus GCC Mentor
eCosCentric ECOSPRO (eCos) GCC eCosCentric

106
 Embedded OS Availability (page 2)

Development
Vendor OS/RTOS Available From
Tools
MRA Digital Android GCC MRA Digital
FreeRTOS RTE ARM DS-5 and GCC Freertos.org
Monta Vista CGE7 Linux Monta Vista/GCC Monta Vista
AUTOSAR AUTOSAR 4.0.3 MCAL Elektrobit Tresos Studio Altera
Microsoft Windows Embedded 7 Microsoft/Studio Coming
Quadros RTXC GCC Coming
rtems.org RTEMS GCC Coming

107
 Embedded SW Operating System Ecosystem (Japan)

Development
Vendor OS/RTOS Availability
Tools
eSOL eT-Kernel (uITRON4.0) eBinder eSOL
eForce uC3 (uITRON 4.0) ARMCC/SoCEDS eForce
Toppers Toppers (uITRON extended) EDS/Toppers Toppers
Mispro NORTi(uITRON 4.0 standard) ARMCC Mispro

108
 Broad JTAG Debugging Tools Support

Company Debugger
Altera USB Blaster II
Lauterbach Trace32
ARM DSTREAM
Wind River ICE II, Probe
Green Hills Probe
Yokogawa Digital Computer AdviceLUNA
Kyoto Microcomputer Partner-Jet
Computex PALMiCE3
Segger J-Link
iSystem Coming Soon
Ronetix PEEDI

109
 OS support

List
 http://www.altera.com/devices/processor/dev-tools/support/os-support.html

110
Preloader Generation

For Cyclone V and Arria V SoC

 Preloader

Runs after the bootloader

Configures the HPS IO.
Configures and Calibrates the DDR controller
Optionally loads the FPGA image
 http://www.rocketboards.org/foswiki/Documentation/GSRD131Programmin
gFPGA
Is just a small version of Uboot or Uboot-SPL

112
 Generating the preloader

GUI and Command line options

 http://www.rocketboards.org/foswiki/Documentation/GSRD131Preloader

Launch in embedded shell

 bsp-editor&

Choose File -> New

Select the folder under the handoff folder

113
 Bsp-editor - Choose Soc System

Select OK

114
 Bsp-editor - Choose Next Boot location

Choose the Device

that contains the
next executable.
Note: Only select
one

115
 Preloader - Advanced settings

Choose the advanced

settings you may want.

I.e. You may not want

watchdog for bare
metal system.

Select Generate
Then at the embedded
prompt cd to the
directory and type
“make”

116
 Build Preloader from the command line
bsp-create-settings \
--bsp-dir "./qspi_preloader" \
--preloader-settings-dir "$(SOCEDS_ROOT)/examples/hardware/cv_soc_devkit_ghrd/hps_isw_handoff/soc_system_hps_0" \
--settings "./qspi_preloader/settings.bsp" \
--type spl \
--set spl.CROSS_COMPILE arm-altera-eabi- \
--set spl.PRELOADER_TGZ "$(SOCEDS_ROOT)/host_tools/altera/preloader/uboot-socfpga.tar.gz" \
--set spl.boot.BOOTROM_HANDSHAKE_CFGIO 1 \
--set spl.boot.BOOT_FROM_QSPI 10\
--set spl.boot.BOOT_FROM_RAM 0 \
--set spl.boot.BOOT_FROM_SDMMC 1 \
--set spl.boot.CHECKSUM_NEXT_IMAGE 1 \
--set spl.boot.EXE_ON_FPGA 0 \
--set spl.boot.FPGA_DATA_BASE 0xffff0000 \
--set spl.boot.FPGA_DATA_MAX_SIZE 0x10000 \
--set spl.boot.FPGA_MAX_SIZE 0x10000 \
--set spl.boot.QSPI_NEXT_BOOT_IMAGE 0x60000 \
--set spl.boot.SDMMC_NEXT_BOOT_IMAGE 0x40000 \
--set spl.boot.STATE_REG_ENABLE 1 \
--set spl.boot.WARMRST_SKIP_CFGIO 1 \
--set spl.boot.WATCHDOG_ENABLE 0 \
--set spl.debug.DEBUG_MEMORY_ADDR 0xfffffd00 \
--set spl.debug.DEBUG_MEMORY_SIZE 0x200 \
--set spl.debug.DEBUG_MEMORY_WRITE 0 \
--set spl.debug.HARDWARE_DIAGNOSTIC 0 \
--set spl.debug.SEMIHOSTING 0 \
--set spl.debug.SKIP_SDRAM 0 \
--set spl.performance.SERIAL_SUPPORT 1 \
--set spl.reset_assert.DMA 0 \
--set spl.reset_assert.GPIO0 0 \
--set spl.reset_assert.GPIO1 0 \
--set spl.reset_assert.GPIO2 0 \
--set spl.reset_assert.L4WD1 0 \
--set spl.reset_assert.OSC1TIMER1 0 \
--set spl.reset_assert.SDR 0 \
--set spl.reset_assert.SPTIMER0 0 \
--set spl.reset_assert.SPTIMER1 0 \
--set spl.warm_reset_handshake.ETR 1 \
--set spl.warm_reset_handshake.FPGA 1 \
--set spl.warm_reset_handshake.SDRAM 0 \
--set spl.boot.SDRAM_SCRUBBING 1 \
--set spl.boot.SDRAM_SCRUB_BOOT_REGION_START 0x1000000 \
--set spl.boot.SDRAM_SCRUB_BOOT_REGION_END 0x3000000 \
--set spl.boot.SDRAM_SCRUB_REMAIN_REGION 1
make -C $(PRELOADER_DIR)
117
 Preloader more info

SOC EDS Users guide

Chapter 7
 http://www.altera.com/literature/ug/ug_soc_eds.pdf

Rocketboards
 http://www.rocketboards.org/foswiki/Documentation/PreloaderUbootCusto
mization131
 http://www.rocketboards.org/foswiki/Documentation/GSRD141Preloader

118
Uboot Generation
 u-boot

Linux workshop
Altera SOC 2 day training.
u-boot can be downloaded from GitHub.org…
 https://github.com/altera-opensource
 http://www.rocketboards.org/foswiki/Documentation/GitGettingSTarted

…or built along with the preloader

 Type “make uboot” in the preloader directory and u-boot will be created.

120
Working With SD cards
 Creating an SD card from GSRD Linux

The steps required to create the SD card for the Cyclone V

Development board are:
1. Download the GSRD release binaries
 http://releases.rocketboards.org/release/2014.12/gsrd/bin
2. Extract the compressed Linux SD card image from archive
 $ tar -xzf linux-socfpga-gsrd-14.1-cv-bin.tar.gz
3. Expand the compressed Linux SD card image
 $ gunzip linux-socfpga-gsrd-14.1-cv-bin/sd_image_cyclone5.bin.gz
4. Determine the device associated with the SD card on the host by
running the following command before and after inserting the card in
the reader:
 $ cat /proc/partitions
Let's assume it is
 /dev/sdx.
5. Use dd utility to write the SD image to the SD card:
 $ sudo dd if=linux-socfpga-gsrd-14.1-cv-bin/sd_image_cyclone5.bin of=/dev/sdx bs=1M
Note we are using sudo to be able to write to the card.

122
 Creating an SD card from GSRD Windows

Download and unzip the sd-image

Downlaod Win32DiskImager from
http://sourceforge.net/projects/win32diskimager/
Insert an micro-SD card in a microSD->USB adapter
a new drive letter will show up, assuming F:
run Win32DiskImager
select the GSRD sd_image for you board
click 'write'and confirm 'yes'
wait for the completion
eject the micro-SD card

123
 http://www.rocketboards.org/foswiki/Documentation/GSRD
141SdCard Location File Name Description
Device Tree Blob
socfpga.dtb
file
FPGA
soc_system.rbf
configuration file
U-boot script for
Partition 1
u-boot.scr configuring
FPGA
Compressed
zImage Linux kernel
image file
Linux root
Partition 2 various
filesystem
n/a Preloader image
Partition 3
n/a U-boot image

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 Updating an SD Card Linux
The following table presents how each item can be updated individually:Replace in
the above command "sdx" with the device name of the SD card on your host system.
You can find out the device name by running $ cat /proc/partitions before and after
plugging in the card reader into the host.
File Update Procedure
zImage Mount /dev/sdx1 (FAT) on the host
soc_system.rbf machine and update files accordingly:
$ sudo mkdir sdcard
soc_system.dtb $ sudo mount /dev/sdx1 sdcard/
u-boot.scr $ sudo cp <file_name> sdcard/
$ sudo umount sdcard
preloader-mkpimage.bin $ sudo dd if=preloader-mkpimage.bin
of=/dev/sdx3 bs=64k seek=0
u-boot-socfpga_cyclone5.img $ sudo dd if=u-boot-
socfpga_cyclone5.img of=/dev/sdx3
bs=64k seek=4
root filesystem Mount /dev/sdx2 (ext3 FS) on the host
machine and updatefiles accordingly
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 Updating an SD Card Windows

SD Card Boot Utility

 Useful for updating an existing sd card image
 http://www.altera.com/literature/ug/ug_soc_eds.pdf
 Chapter 11

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System Console
System Console
Provides direct system access at
runtime from TCL command line
interface
No processor code to write
 Access via Nios® II processor, JTAG bridge,
JTAG UART or custom Agent
 Supports an Avalon-MM or Avalon-ST Master
 Use for board bring-up, debug, diagnostics,
system profiling and configuration

FPGA
QSys Builder System
IP IP Nios II OCI System
USB Blaster Nios II IDE
Sys. Interconnect Console
SLD
IP Bridge JTAG
Hub
What is System Console?

Quick system-level debug of Qsys systems

 Interactive Tcl Console
Opens as a separate window
Opens in the Embedded Command Shell
Dashboard components available.
 Debug over various communication channels
JTAG or TCP/IP
 Read from or write to memory mapped components
 No processor required
Usage Examples

System-level debug
 Board bring-up and interface testing
 System clock, reset and JTAG chain validity testing
 Qsys component functionality testing
 Loopback testing of Avalon Streaming interfaces
 Provide test vectors, return responses
 Poke and Peek at the address map.
System Console Interfaces

System Console on Host

Through JTAG and Virtual JTAG Hub

Nios II Processor JTAG to Avalon JTAG UART Avalon-ST JTAG

Master Bridge Interface

Avalon-MM Avalon-MM Avalon-MM Avalon-ST

Master Master Slave Source and Sink

Avalon-MM Avalon-ST
Qsys Slave Source or Sink
Interconnect
User Component User Component
Usage Flow – Summary

1. Add required component to Qsys

2. Connect board and program FPGA

3. Launch System Console Complete master write

and read example script
set m_path [lindex \
4. Locate and open service path [get_service_paths master] 0]
open_service master $m_path

5. Perform desired operation(s) with master_write_memory $m_path 0x2000 \

[list 0x01 0x02]
the service master_read_memory $m_path 0x2000 2

6. Close the service close_service master $m_path

 JTAG Masters in GHRD

GHRD has
multiple JTAG
Masters
 To HPS
 FPGA slaves
 To SDRAM
(optional)

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 System Console Resources

System Console home page

 http://www.altera.com/products/software/quartus-ii/subscription-
edition/qsys/systems/qts-systems-console.html
On alterawiki.com
 http://www.alterawiki.com/wiki/System_Console

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Creating FPGA specific header
files
 Creating FPGA-Specific Header Files

sopc-create-header-files <project>.sopcinfo
Creates a header file for each master in the qsys system.
Use in your software to keep everything up to date.
Call from an embedded command shell or in your own
make file.

136
Labs Overview
 LABs Overview

FPGA hardware already built

 Based on GHRD
 Added FFT megacore
 Added 2 SGDMA to move the data in and out of the FFT
 Added on chip memory to make transfers easy.
 Self contained in its own qsys subsystem.
 LW bridge and JTAG Master connect to all FFT slaves

Need Quartus 14.1, Cyclone V devices and SOCEDS 14.1

loaded on your machine.
No licenses are required for these LABs

*If you recompile the hardware in quartus you will need a full Quartus license or 60 day
eval license.

138
 FFT Component is Composed of two items
 The FFTmega core
 An adapter to make it look standard Avalon-ST

Inputs are 16 bit real and 16 bit imaginary so it would make

a nice 32 bit word.
 They could be larger then you would just make the real and imaginary it’s
own words.
Output is 24 bits of real and 24 bits of imaginary data
 So map it into 64 bits ( 2 32 bit words);

139
 FFT Flow

HPS
1- Processor Writes LW Bridge
wave form to Onchip
Memory Onchip Memory

SGDMA to FFT

FFT

SGDMA from FFT

JTAG only Master

140
 FFT Flow

HPS
1- Processor Writes LW Bridge
wave form to Onchip
Memory Onchip Memory
2- Processor Writes
Descriptor to SGDMAs
to start data flowing
SGDMA to FFT

FFT

SGDMA from FFT

JTAG only Master

141
 FFT Flow

HPS
1- Processor Writes LW Bridge
wave form to Onchip
Memory Onchip Memory
2- Processor Writes
Descriptor to SGDMAs
to start data flowing
3-SGDMAs move data SGDMA to FFT
through the FFT.

FFT

SGDMA from FFT

JTAG only Master

142
 FFT Flow

HPS
JTAG Master also has LW Bridge
access to all theses
peripherals so System Onchip Memory
Console can run the
FFT

SGDMA to FFT

FFT

SGDMA from FFT

JTAG only Master

143
 FFT Flow

HPS
1- Processor Writes LW Bridge
wave form to Onchip
Memory Onchip Memory
2- Processor Writes
Descriptor to SGDMAs
to start data flowing
3-SGDMAs move data SGDMA to FFT
through the FFT.
4-Processor reads the
FFT data back.
FFT

SGDMA from FFT

JTAG only Master

144
 LABs

1- Preloader Creation for FFT project

2- System Console FFT test
3- BareMetal FFT
4- Linux FFT App
5- Websever FFT

145
 Lab 1 - preloader

Load SD card with a Default image.

Build Preloader from Prebuilt hardware.
Load new prloader into SD Card

146
 Lab 2 - System Console FFT test

Uses the FPGA JTAG Master to load the waveforms and

test the SGDMAs and FFT ( not processor)
Open system_console
Discover the masters
Verify fpga only master is number “0”
Run fft script
Check wavefrom looks ok.
This validates the hardware.

147
 3- BareMetal FFT

Review code
Use the alt_read_word, alt_write_word to insure the code
does not get stuck in caches.
Compile in a embedded_command window
 Paths to the hwlibs/socal and compilers

Load code onto SDCARD and run

148
 Lab 4- Linux FFT App

Linux requires that a driver must be present to talk to

hardware
There are at least three drivers that can be used.
 /dev/mem
 Uio driver
 Custom written driver

Not a linux class so we use the simplest /dev/mem

Linux also uses the MMU so all address are virtual
Linux drivers discussed in detail in Developing Linux
Drivers for Custom Peripherals Workshop

149
 Lab 5 - Web Server FFT Background

In our standard Linux embedded

‘distribution’ we include lighttpd as
The web server application

… Also included is the whole protocol

TCP/IP stack in the Linux Kernel

150
Lab 4 – Web Server

Two files fft.sh and MyGraphTest1_2.js

fft.sh initial script that is run when you type the below in
your browser window
 <ipaddress>/fft.sh

MyGraphTest1_2.js is a JavaScript which plots the real

output and run on the browser.
When fpga_fft is run it produces a file with the values of
the fft.
This code reads it in and plots the graph.
 Thank You

152