DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

ACADEMIC YEAR-2024-25

AS PER ANNA UNIVERSITY SYLLABUS 2021 REGULATION

EE3412 – LINEAR AND DIGITAL CIRCUITS LABORATORY

PREPARED BY: MrS. E. SUJATHA, AP/ECE

VERIFIED BY: Dr.A.SARAVANAN, HOD/ECE

pg. 1
 DEPARTMENT OF ELECTRICAL AND ELECTRONICS
ENGINEERING

VISION OF THE INSTITUTE:

To nurture innovative future leaders in technology, entrepreneurship and

management who create wealth for our nation and develop a fulfilling global society.

MISSION OF THE INSTITUTE:

To create a model educational institution contributing to innovation,

entrepreneurship & technology management for our country.

VISION OF THE DEPARTMENT:

To develop prominent Electrical and Electronics Engineers with
interdisciplinary knowledge in innovation, creativity, research and ethical values to
serve the Society.

MISSION OF THE DEPARTMENT:

M1: To impart fundamental and advanced education in Electrical, Electronics
and Inter disciplinary disciplines, suitable for emerging industrial needs through
quality infrastructure and resources.

M2: To provide innovative solutions pertaining to electrical and electronics

engineering to emerging industrial and societal problems.

M3: To inculcate the habit of leadership, ethics and lifelong learning for
betterment of society.

pg. 2
PROGRAM OUTCOMES (POs):

PO1: Engineering knowledge

Apply the knowledge of mathematics, science, engineering fundamentals, and an

engineering specialization to the solution of complex engineering problems.
PO2: Problem analysis

Identify, formulate, review research literature, and analyze complex engineering

problems reaching substantiated conclusions using first principles of mathematics, natural
sciences, and engineering sciences.
PO3: Design/development of solutions

Design solutions for complex engineering problems and design system components or
processes that meet the specified needs with appropriate consideration for the public health and
safety, and the cultural, societal, and environmental considerations.
PO4: Conduct investigations of complex problems

Use research-based knowledge and research methods including design of experiments,

analysis and interpretation of data, and synthesis of the information to provide valid conclusions.
PO5: Modern tool usage

Create, select, and apply appropriate techniques, resources, and modern engineering and
IT tools including prediction and modeling to complex engineering activities with an
understanding of the limitations.
PO6: The engineer and society

Apply reasoning informed by the contextual knowledge to assess societal, health, safety,
legal and cultural issues and the consequent responsibilities relevant to the professional
engineering practice.
PO7: Environment and sustainability

Understand the impact of the professional engineering solutions in societal and

environmental contexts, and demonstrate the knowledge of, and need for sustainable
development.

pg. 3
PO8: Ethics

Apply ethical principles and commit to professional ethics and responsibilities and norms
of the engineering practice.
PO9: Individual and team work

Function effectively as an individual, and as a member or leader in diverse teams, and in

multidisciplinary settings.
PO10: Communication

Communicate effectively on complex engineering activities with the engineering

community and with society at large, such as, being able to comprehend and write effective
reports and design documentation, make effective presentations, and give and receive clear
instructions.
PO11: Project management and finance

Demonstrate knowledge and understanding of the engineering and management

principles and apply these to one’s own work, as a member and leader in a team, to manage
projects and in multidisciplinary environments.
PO12: Life-long learning

Recognize the need for, and have the preparation and ability to engage in independent
and life-long learning in the broadest context of technological change.

PROGRAM SPECIFIC OUTCOME:

PSO1: Solve various real time problems of Electrical Machines, Electronics applications, Control
System, Instrumentation System, Power system and Power Electronic & drives.

PSO2: Identify conventional and renewable energy systems for Power generation and distribution with
suitable recent technologies.

PSO3: Develop innovative solutions pertaining to industry and Society by using Electrical and
Electronics systems.

pg. 4
 EE3412 – LINEAR AND DIGITAL CIRCUITS LABORATORY

(R2021)

SYLLABUS
COURSE OBJECTIVES:

 To learn design, testing and characterizing of circuit behaviour with digital and analogy IC’s.

LIST OF EXPERIMENTS:
1. Implementation of Boolean Functions, Adder and Subtractor circuits.
2. Code converters: Excess-3 to BCD and Binary to Gray code converter and vice- versa
3. Parity generator and parity checking
4. Encoders and Decoders
5. Counters: Design and implementation of 3-bit modulo counters as synchronous and Asynchronous
types using FF IC’s and specific counter IC.
6. Shift Registers: Design and implementation of 4-bit shift registers in SISO, SIPO, PISO, PIPO modes
using suitability IC’s.
7. Study of multiplexer and de multiplexer
8. Timer IC application: Study of NE/SE 555 timer in A stability, Mono stability operation.
9. Application of Op-Amp: inverting and non-inverting amplifier, Adder, comparator, Integrator and
Differentiator.
10. Voltage to frequency characteristics of NE/ SE 566 IC.
11. Variability Voltage Regulator using IC LM317.
TOTAL: 45 PERIODS
COURSE OUTCOMES:
At the end of the course, the students will be able to:
CO1: Implement Boolean function using logic gates
CO2: Design and implementation of combinational circuits.
CO3: Design and implementation of sequential circuits like counters, registers.
CO4: Design and implement applications of Op-Amp.

pg. 5
CO-PO Mapping Matrix:
Course PO1 PO1 PO1 PSO PSO PSO
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9
Outcome 0 1 2 1 2 3
CO1 2 1 1 2 2 2 2 2 2 1 2 1
CO2 1 3 3 3 2 2 2 2 2 1 2 1
CO3 1 1 2 2 2 2 2 2 1 1 2 1
CO4 2 1 3 3 2 2 2 2 2 2
1.
AVG. 1.5 2.2 2.5 1.5 - - - 2.0 2 2.0 1.7 1.2 1.5 1.2
5

EVALUATION OF LAB REPORT:

Marks Marks
Evaluation Parameters
Allotted Awarded
Aim & Hardware / Software Required: 10
Design & Circuit Diagram / Algorithm &
30
Flowchart:
Observation & Calculation / Program: 30
Graph / Output & Result: 20
Viva Voce: 10
Total: 100

pg. 6
EE3412 LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY
Exp. Pg.
INDEX
No. No.

1 STUDY OF LOGIC GATES

2 DESIGN AND IMPLEMENTATION OD ADDER AND SUBTRACTOR

3 DESIGN AND IMPLEMENTATION OF CODE CONVERTORS

DESIGN AND IMPLEMENTATION OF PARITY GENERATOR AND

4
PARITY CHECKER

DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER

5
USING LOGIC DIAGRAM

DESIGN AND IMPLEMENTATION OF 4-BIT SHIFT REGISTERS IN

6
SISO, SIPO, PIPO AND PISO

DESIGN AND IMPLEMENTATION OF 3-BIT SYNCHRONOUS

7
MODULO COUNTER

DESIGN AND IMPLEMENTATION OF 4-BIT BINARY

8
ASYNCHRONOUS UP AND DOWN COUNTER

9 STUDY OF MULTIPLEXER AND DE-MULTIPLEXER

10 DESIGN OF ASTABLE AND MONOSTABLE USING IC 555

DESIGN OF INVERTING AND NON-INVERTING AMPLIFIER,

11
ADDER, COMPARATOR, INTEGRATOR, AND DIFFERENTIATOR

VOLTAGE TO FREQUENCY CHARACTERISTICS OF NE/ SE 566

12
IC.

13 VARIABILITY VOLTAGE REGULATOR USING IC LM317

CONTENT BEYOND SYLLBUS

14 DESIGN A SCHMITT TRIGGER USING IC 741.

15 STUDY OF SMPS

pg. 7
 ANDGATE

LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7408:

TRUTH TABLE:
INPUT OUTPUT
S. No
A B Y = A. B
1. 0 0 0
2. 0 1 0
3. 1 0 0
4. 1 1 1

OR GATE

LOGIC DIAGRAM:

pg. 8
 EX.NO:1 STUDY OF LOGIC GATES
AIM:
To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR, EX-OR gates.

APPARATUS REQUIRED:
S. Name of the Apparatus Range Quantity
No
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

THEORY:

AND gate:
An AND gate is the physical realization of logical multiplication operation. It is an
electronic circuit which generates an output signal of ‘1’ only if all the input signals are ‘1’.
OR gate:
An OR gate is the physical realization of the logical addition operation. It is an electronic
circuit which generates an output signal of ‘1’ if any of the input signal is ‘1’.
NOT gate:
A NOT gate is the physical realization of the complementation operation. It is an electronic
circuit which generates an output signal which is the reverse of the input signal. A NOT gate is
also known as an inverter because it inverts the input.
NAND gate:
A NAND gate is a complemented AND gate. The output of the NAND gate willbe ‘0’
if all the input signals are ‘1’ and will be ‘1’ if any one of the input signals is ‘0’.

pg. 9
PIN DIAGRAM OF IC 7432:

TRUTH TABLE:
INPUT OUTPUT
S. No
A B Y=A+B
1. 0 0 0
2. 0 1 1
3. 1 0 1
4. 1 1 1

NOT GATE

LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7404 :

TRUTH TABLE:
INPUT OUTPUT
S. No
A Y = A’
1. 0 1
2. 1 0
pg. 10
 NOR gate
A NOR gate is a complemented OR gate. The output of the OR gate will be ‘1’ if all the
inputs are ‘0’ and will be ‘0’ if any one of the input signals is ‘1’.

EX-OR gate:
An Ex-OR gate performs the following Boolean function,
A B = (A B’) + (A’B)
It is similar to OR gate but excludes the combination of both A and B being equal to one.
The exclusive OR is a function that give an output signal ‘0’ when the two input signals are equal
either ‘0’ or ‘1’.
PROCEDURE:
1. Connections are given as per the circuit diagram

2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and verify the truth table for all gates.

pg. 11
NANDGATE

LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7400:

TRUTH TABLE:

INPUT OUTPUT
S. No
A B Y = (A. B)’
1. 0 0 1
2. 0 1 1
3. 1 0 1
4. 1 1 0

NORGATE

LOGIC DIAGRAM:

pg. 12
PIN DIAGRAM OF IC 7402:

TRUTH TABLE:
INPUT OUTPUT
S. No
A B Y = (A +
B)’
1. 0 0 1
2. 0 1 0
3. 1 0 0
4. 1 1 0

EX-ORGATE

LOGIC DIAGRAM:

pg. 13
PIN DIAGRAM OF IC 7486:

TRUTH TABLE:

INPUT OUTPUT
S. No
A B Y=A B
1. 0 0 0
2. 0 1 1
3. 1 0 1
4. 1 1 0

pg. 14
RESULT:
The truth tables of all the basic digital ICs were verified.

pg. 15
HALF ADDER
TRUTH TABLE
INPUT OUTPUT
S. No
A B S C
1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 0 1

LOGIC DIAGRAM:

FULL ADDER TRUTH TABLE:

INPUT OUTPUT
S. No
A B C SU CARR
M Y
1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1

pg. 16
 EXP.NO:2 DESIGN AND IMPLEMENTATION OF ADDER /
SUBTRACTOR
AIM:
To design and construct half adder, full adder, half subtractor and full subtractor circuits

and verify the truth table using logic gates.

APPARATUS REQUIRED:

S. No Name of the Specification Quantity

Apparatus
1. IC 7432(OR), 7408(AND),
Each 1
7486(EX-OR), 7404(NOT)
2. Digital IC Trainer Kit 1

3. Patch chords -

THEORY:

The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
0+0=0
0+1=1
1+0=1
1 + 1 = 10
The first three operations produce a sum of whose length is one digit, but when the last
operation is performed the sum is two digits. The higher significant bit of this result is called a
carry and lower significant bit is called the sum.
HALFADDER:

A combinational circuit which performs the addition of two bits is called half adder. The
input variables designate the augend and the addend bit, whereas the output variables produce the
sum and carry bits.

pg. 17
LOGIC DIAGRAM:

SUM

CARRY

CARRY = AB + AC + BC

HALF SUBTRACTOR
TRUTH TABLE:
INPUT OUTPUT
S. No
A B DIFF BOR
R
1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0

pg. 18
FULLADDER:

A combinational circuit which performs the arithmetic sum of three input bits is called full
adder. The three input bits include two significant bits and a previous carry bit. A full adder circuit
can be implemented with two half adders and one OR gate.

DESIGN:
From the truth table the expression for sum and carry bits of the output can be obtained as,
Sum, S=A B ; Carry, C = A . B

DESIGN:
From the truth table the expression for sum and carry bits of the output can be obtained as, SUM
= A’B’C + A’BC’ + AB’C’ + ABC; CARRY = A’BC + AB’C +ABC’ +ABC
Using Karnaugh maps the reduced expression for the output bits can be obtained as,

HALF SUBTRACTOR
DESIGN:
From the truth table the expression for difference and borrow bits of the output can be obtained
as,
Difference, DIFF = A B; Borrow, BORR = A’. B
FULL SUBTRACTOR

DESIGN:

From the truth table the expression for difference and borrow bits of the output can be obtained
as,
Difference, DIFF= A’B’C + A’BC’ + AB’C’+ABC
Borrow, BORR = A’BC +AB’C + ABC’+ABC
Using Karnaugh maps the reduced expression for the output bits can be obtained as,

pg. 19
LOGIC DIAGRAM:

FULL SUBTRACTOR
INPUT OUTPUT
S. No
A B C DIFF BOR
R
1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
LOGIC DIAGRAM:

pg. 20
HALF SUBTRACTOR:
A combinational circuit which performs the subtraction of two bits is called half subtractor.
The input variables designate the minuend and the subtrahend bit, whereas the output variables
produce the difference andborrow bits.

FULL SUBTRACTOR:

A combinational circuit which performs the subtraction of three input bits is called full
subtractor. The three input bits include two significant bits and a previous borrow bit. A full subtractor
circuit can be implemented with two half subtractors and one OR gate.

PROCEDURE:

 The connections are given as per the circuit diagram.

 Two 4 – bit numbers added or subtracted depend upon the control input and the
output is obtained.
 Apply the inputs and verify the truth table for the half adder or s subtractor and full
adder or subtractor circuit

DIFFERENCE

A’B’C + A’BC’ + AB’C’ + ABC = A B C

BORROW

BORROW = A’B + A’C + BC

pg. 21
pg. 22
RESULT:
Thus, the half adder, full adder, half subtractor and full subtractor circuits were designed and the
truth table was verified.
pg. 23
 BINARY TO GRAY:
LOGIC DIAGRAM

pg. 24
EXP.NO:3 DESIGN AND IMPLEMENTATION OF CODE CONVERTOS
AIM:

To construct and verify the performance of binary to gray and gray to binary and vice versa.

APPARATUS REQUIRED:

Name of the
S. No Specification Quantity
apparatus
1. IC 7404(NOT), 7486(EX-OR),
Each 1
7408(AND), 7432(OR)
2. Digital IC Trainer Kit 1

3. Connecting wires -

THEORY:

BINARY TO GRAY:

The MSB of the binary code alone remains unchanged in the gray code. The remaining bits in
the gray are obtained by EX-OR in the corresponding gray code bit and previous bit in the binary code.
The gray code is often used in digital systems because it has the advantage that only one bit in the
numerical representation changes between successive numbers.
GRAY TO BINARY:

The MSB of the Gray code remains unchanged in the binary code the remaining bits are obtained
by EX – OR in the corresponding gray code bit and the previous output binary bit.
PROCEDURE:

 Connections are given as per the logic diagram.

 The given truth tables are verified.

pg. 25
BINARY TO GRAY:
TRUTH TABLE
Decimal Binary code Gray code
D C B A Z Y X W
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0

W X

pg. 26
GRAY TO BINARY
TRUTH TABLE
Decimal Gray code Binary code
Z Y X W D C B A
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
3 0 0 1 1 0 0 1 0
2 0 0 1 0 0 0 1 1
6 0 1 1 0 0 1 0 0
7 0 1 1 1 0 1 0 1
5 0 1 0 1 0 1 1 0
4 0 1 0 0 0 1 1 1
12 1 1 0 0 1 0 0 0
13 1 1 0 1 1 0 0 1
15 1 1 1 1 1 0 1 0
14 1 1 1 0 1 0 1 1
10 1 0 1 0 1 1 0 0
11 1 0 1 1 1 1 0 1
9 1 0 0 1 1 1 1 0
8 1 0 0 0 1 1 1 1

pg. 27
 LOGIC DIAGRAM

pg. 28
EXCESS-3 TO BCD TRUTH TABLE

pg. 29
LOGIC DIAGRAM

K-Map for D K-Map for C

pg. 30
K-Map for B K-Map for A

pg. 31
BCD TO EXCESS 3 TRUTH TABLE

LOGIC DIAGRAM

pg. 32
RESULT:

The design of the three bits Binary to Gray code converter &vice versa and BCD to Excess-3 code
converter & vice versa were done and its truth table were verified.

pg. 33
PARITYGENERATOR

CIRCUIT DIAGRAM:
ODD PARITY GENERATOR

EVENPARITYGENERATOR

ODD PARITYCHECKER

pg. 34
 EXP.NO: 4 DESIGN AND IMPLEMENTATION OF PARITY
GENERATOR AND PARITY CHECKER
AIM:
To design and verify the truth table of a three-bit Odd Parity generator and checker & Even Parity
Generator and Checker.

APPARATUS REQUIRED:
S. Name of the Apparatus Range Quantity
No
1. Digital IC trainer kit 1
2. EX-OR gate IC 7486 1
3. NOT gate IC 7404 1
4. Connecting wires As
required
THEORY:

A parity bit is used for the purpose of detecting errors during transmission of binary information.
A parity bit is an extra bit included with a binary message to make the number of 1’s either odd or even.
The message including the parity bit is transmitted and then checked at the receiving end for errors. An
error is detected if the checked parity does not correspond with the one transmitted. The circuit that
generates the parity bit in the transmitter is called a parity generator and the circuit that checks the parity
in the receiver is called a parity checker.
In even parity the added parity bit will make the total number of 1’s an even amount and in
odd parity the added parity bit will make the total number of 1’s an odd amount. In a three-bit odd parity
generator the three bits in the message together with the parity bit are transmitted to their destination,
where they are applied to the parity checker circuit. The parity checker circuit checks for possible errors
in the transmission.
Since the information was transmitted with odd parity the four bits received must have an odd
number of 1’s. An error occurs during the transmission if the four bits received have an even number
of 1’s, indicating that one bit has changed during transmission. The output of the parity checker is
denoted by PEC (parity error check) and it will be equal to 1 if an error occurs, i.e., if the four bits
received has an even number of 1’s.

pg. 35
PARITY GENERATOR

TRUTH TABLE:

INPUT
(Three- OUTPUT OUTPUT
S. No bit (Odd Parity (Even Parity

message bit) bit)

)
A B C P P
1. 0 0 0 1 0
2. 0 0 1 0 1
3. 0 1 0 0 1
4. 0 1 1 1 0
5. 1 0 0 0 1
6. 1 0 1 1 0
7. 1 1 0 1 0
8. 1 1 1 0 1

From the truth table the expression for the output parity bit is, P (A, B, C) = Σ (0,
3, 5, 6)Also written as, P = A’B’C’ + A’BC + AB’C + ABC’ = (A B C) ‘

EVEN PARITYCHECKER

pg. 36
PROCEDURE:

1. Connections are given as per the circuit diagrams.

2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the Parity generator and
checker.

RESULT:

The design of the three-bit odd Parity generator and checker & Even Parity Generator and Checker
circuits was done and their truth tables were verified.

pg. 37
ENCODER TRUTH TABLE

LOGIC DIAGRAM:

pg. 38
EXP.NO:5 DESIGN AND IMPLEMENTATION OF ENCODER AND
DECODER USING LOGIC DIAGRAM

AIM:

To design and implement encoder and decoder using logic gates.

APPARATUS REQUIRED:

S. No Name of the Specification Quantity

apparatus
1. IC 7432(OR) 3
2. IC 7408(AND), 7404(NOT) Each 1

3. Digital IC Trainer Kit 1

4. Connecting wires -

THEORY:

An encoder is digital circuit that has 2n input lines and n output lines. The output lines generate
a binary code corresponding to the input values 8 – 3 encoder circuit has 8 inputs, one for each of the
octal digits and three outputs that generate the corresponding binary number. Enable inputs E1 should
be connected to ground and Eo should be connected to VCC

A decoder is a combinational circuit that converts binary information from n input lines to 2n
unique output lines. In 2-4line decoder the three inputs are decoded into right outputsin which each
output representing one of the min terms of 2 input variables.
PROCEDURE:
 Connections are given as per the logic diagram.
 The truth table is verified by varying the inputs

pg. 39
DECODER

TRUTH TABLE

INPUT OUTPU
T
S1 S0 D3 D2 D1 D0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

LOGIC DIAGRAM:

S1 S0

- D0

D1

D2

D3

pg. 40
RESULT:

Thus, the encoder and decoder circuits were designed and implemented.

pg. 41
D Flip flop IC 7474 - Pin diagram

SHIFT REGISTER: SISO:

Truth table:
Data input = 1001
Clock Serial input Serial output
1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1

pg. 42
 EXP.NO:6 DESIGN AND IMPLEMENTATION OF 4-BIT SHIFT
REGISTERS IN SISO,SIPO ,PIPO AND PISO
AIM:
To implement the following shift register using flip flop

(i) SIPO (ii) SISO (iii) PISO (iv) PIPO

APPARATUS REQUIRED:

S. No Name of the apparatus Specification Quantity

1. IC 7474, 7432 (OR) 2

2. Digital IC Trainer Kit 1

3. Connecting wires -

THEORY:

A register is used to move digital data. A shift register is a memory in which information is
shifted from one position in to another position at a line when one clock pulse is applied. The data can
be shifted either left or right direction towards right or towards left.
A shift register can be used in four ways depending upon the input in which the data are entered
in to and takes out of it. The four configurations are given as
 Serial input – Serial output (SISO)

 Parallel input – Serial output (PISO)

 Serial input – Parallel output (SIPO)

 Parallel input – Parallel output (PIPO)

D flip flop is used for constructing shift register.

PROCEDURE:

1. Give the connections as per the circuit

2. Set or Reset at the pin 2 which it’s the MSB of serial data.
3. Apply a single clock Set or Reset second digital input at pin 2.
4. Repeat step 2 until all 4-bit data are taken away.

pg. 43
SIPO:

Truth table

No of clk Serial input Parallel output

pulse Din Q3 Q2 Q Q
1 0
0 0 0 0 0 0
1 1 0 0 0 1
2 1 0 0 1 1
3 0 0 1 1 0
4 1 1 1 0 1
5 0 1 0 1 0
6 0 0 1 0 0
7 0 1 0 0 0
8 0 0 0 0 0

pg. 44
PIPO

Truth table (PIPO)

Clock Parallel input Parallel output

D D1 D2 D3 Q0 Q1 Q2 Q3
0
0 0 0 0 0 0 0 0 0

PISO

pg. 45
Truth table

Clock
PARALLEL
OUTPU
INPUT
T
Q4 Q3 Q2 Q1
1 1 0 0 1 1
2 X X X X 0
3 X X X X 0
4 X X X X 1

pg. 46
RESULT:

Thus, the SISO, SIPO, PISO, PIPO shift registers were designed and implemented.

pg. 47
Logic Diagram:

pg. 48
 EXP.NO:7 DESIGN AND IMPLEMENTATION OF 3-BIT
SYNCHRONOUS MODULO COUNTER
AIM:
To design and implement the three-bit synchronous Mod Counter using JK Flip-flop.
APPARATUS REQUIRED:

S. No Name of the apparatus Specification Quantity

1. IC 7473 2
2. Digital IC Trainer Kit 1

3. Connecting wires -

THEORY:

Counter are a group of flip flop connected together to perform counting operation.
According to the way the flip flop is clocked there are two types of flip flops,

Asynchronous counter

Synchronous counter

PROCEDURE:
 Connections are given as per the logic diagram.
 Connect IC’s 7th pin to ground and 14th pin to +5V power supply.
 Verify the truth table by applying clock pulse for all logical input and observe the
output.

RESULT:

Thus, the implementation and design the three-bit synchronous modulus counter was
verified.

pg. 49
UP COUNTER:

TRUTH TABLE:

pg. 50
 EXP.NO: 8 DESIGN AND IMPLEMENTATION OF 4-BIT BINARY
ASYNCHRONOUS UP AND DOWN COUNTER
AIM:
To design and verify asynchronous 4 bit binary up and down counter using JK Flip Flop.
APPARATUS REQUIRED:

S. No Name of the apparatus Specification Quantity

1. IC 7473 2
2. Digital IC Trainer Kit 1

3. Connecting wires -

THEORY:

Counter are a group of flip flop connected together to perform counting operation.
According to the way the flip flop is clocked there are two types of flip flops,

Asynchronous counter

Synchronous counter

PROCEDURE:
 Connections are given as per the logic diagram.
 Connect IC’s 7th pin to ground and 14th pin to +5V power supply.
 Verify the truth table by applying clock pulse for all logical input and observe the
output.

pg. 51
DOWN COUNTER:

TRUTH TABLE:

pg. 52
RESULT:

Thus, the implementation and design the Four bit binary Up and Down counter of
asynchronous counter was verified.

pg. 53
BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

LOGIC DIAGRAM: (4 x 1)

pg. 54
 EXP.NO:9 STUDY OF MULTIPLEXER AND DE-MULTIPLEXER
AIM:
To study the truth table of a 4X1 Multiplexer & 1X4 Demultiplexer.

APPARATUS REQUIRED:

S. Name of the Apparatus Range Quantity

No
1. Digital IC trainer kit 1
2. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. AND gate (three input) IC 7411 2
5. Connecting wires As
required

THEORY:

Multiplexer is a digital switch which allows digital information from several sources
to be routed onto a single output line. The basic multiplexer has several data input lines
and a single output line. The selection of a particular input line is controlled by a set of selection

lines. Normally, there are 2n input lines and n selector lines whose bit combinations determine
which input is selected. Therefore, multiplexer is ‘many into one’ and it provides the digital
equivalent of an analog selector switch.
A Demultiplexer is a circuit that receives information on a single line and transmits this

information on one of 2n possible output lines. The selection of specific output line is controlled
by the values of n selection lines.

PROCEDURE:

1. Connections are given as per the circuit diagrams.

2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the multiplexer & demultiplexer.

pg. 55
1X4 DEMULTIPLEXER
LOGIC SYMBOL:

LOGIC DIAGRAM:

pg. 56
1X4 DEMULTIPLEXER TRUTH TABLE:

INPUT OUTPUT
S. No
S1 S2 Din Y0 Y1 Y2 Y3

1. 0 0 0 0 0 0 0

2. 0 0 1 1 0 0 0

3. 0 1 0 0 0 0 0

4. 0 1 1 0 1 0 0

5. 1 0 0 0 0 0 0

6. 1 0 1 0 0 1 0

7. 1 1 0 0 0 0 0

8. 1 1 1 0 0 0 1

FUNCTION TABLE (4 x 1)

X Y OUTPUTS (Y)

0 0 D0 D0 X’ Y’

0 1 D1 D1 X’ Y

1 0 D2 D2 X Y’

1 1 D3 D3 X Y

Y = D0 X’ Y’ + D1 X’ Y + D2 X Y’ + D3 X Y

RESULT:

The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth
tables were verified.

pg. 57
PIN DIAGRAM:

CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR:

pg. 58
 EXP.NO: 10 DESIGNS OF ASTABLE AND MONOSTABLE USING
IC 555
AIM:
To design an astable and monostable multivibrator circuit for the given specifications using
555 Timer IC.
APPARATUS REQUIRED:
S. No Name of the Apparatus Range Quantity
1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Timer IC IC 555 1
5. Bread Board 1
6. Resistors 7.5KΩ, 3.9 KΩ, 10 KΩ Each 1
7. Capacitors 0.01µF, 0.1µF 2
8. Connecting wires and probes As required

THEORY:

An astable multivibrator, often called a free-running multivibrator, is a rectangular-wave-

generating circuit. This circuit do not require an external trigger to change the state of the output. The
time during which the output is either high or low isdetermined by two resistors and a capacitor, which
are connected externally to the 555 timers. The time during which the capacitor charges from 1/3 Vcc
to 2/3 Vcc is equal to the time the output is high and is given by,
tc = 0.69 (R1 + R2) C
Similarly, the time during which the capacitor discharges from 2/3 Vcc to 1/3 Vcc is equal to the time
the output is low and is given by,
td = 0.69 (R2) C
Thus, the total time period of the output waveform is,
T = tc + td = 0.69 (R1 + 2 R2) C

pg. 59
MODEL GRAPH:

Vc
voltage
O/p

T
2/3

pg. 60
 The term duty cycle is often used in conjunction with the astable multivibrator. The duty cycle
is the ratio of the time tc during which the output is high to the total time period T. It is generally expressed
in percentage. In equation form,
% duty cycle = [ R2 / (R1 + 2 R2)] x 100% or td / tc x 100%
A monostable multivibrator often called a one-shot multivibrator is a pulse generating circuit
in which the duration of the pulse is determined by the RC network connected externally to the
555 timers. In a stable or stand-by state the output of the circuit is approximately zero or at logic
low level. When an external trigger pulse is applied, the output is forced to go high (approx. Vcc).
The time during whichthe output remains high is given by,
tp = 1.1 R1 C
At the end of the timing interval, the output automatically reverts back to its logic low state.
The output stays low until a trigger pulse is applied again. Then thecycle repeats. Thus, the monostable
state has only one stable state hence the name monostable.
PROCEDURE:
1. Connections are given as per the circuit diagram.
2. + 5V supply is given to the + Vcc terminal of the timer IC.
3. At pin 3 the output waveform is observed with the help of a CRO
4. At pin 6 the capacitor voltage is obtained in the CRO and the V0 and Vc voltage
waveforms are plotted in a graph sheet.
5. For monostable a negative trigger pulse of 5V, 2 KHz is applied to pin 2 of the 555 IC
6. At pin 3 the output waveform is observed with the help of a CRO
7. At pin 6 the capacitor voltage is obtained in the CRO and the V0 and Vc voltage
waveforms are plotted in a graph sheet.

DESIGN:

Given f= 11.11 KHz and duty cycle = 23% Therefore, Total time period, T =1/f = 90 x 10-6 s
We know, duty cycle = td / T

23 / 100 = td / 90 x 10-6, td = 0.23 x 90 x 10-6

Therefore, td = 20.7 x 10-6 sand tc = T – td = 90 x 10-6 - 20.7 x 10-6 = 69.3 x 10-6 s

We also know for an astable multivibrator td = 0.69 (R2) C

pg. 61
 CIRCUIT DIAGRAM OF MONOSTABLE MULTIVIBRATOR:

pg. 62
 Assume C = 0.01 x 10-6 F,

R2 = td / (0.69 x C) = 20.7 x 10-6 / (0.69 x 0.01 x 10-6)

R1 = (tc / (0.69 x C)) – R2

R1 = (69.3 x 10-6 / (0.69 x 0.01 x 10-6)) - 3000

Therefore, R1 = 7 KΩ ≈ 6.8 KΩ ≈ 7.5 KΩ

OBSERVATIONS:
Time period
Amplitude
(No. of div x
(No. of div x
S. Waveforms Time per div)
Volts per div)
No tc td

8V 6 Micro Sec 6 Micro Sec

1. Output Voltage, Vo

4V 6 Micro Sec 6 Micro Sec

2. Capacitor voltage, Vc

MONOSTABLE MULTIVIBRATOR
DESIGN:

Given tp = 0.1ms, tp= 1.1 R1 C Assume C= 0.01 x 10-6 F,

Therefore, R1 = 9.09 KΩ ≈ 9.1 KΩ ≈ 10 KΩ
OBSERVATIONS:

Amplitude Time period

S. No (No. of div x (No. of div x
Waveforms
Volts per div) Time per div)
ton toff

0.22 V 0.45 0.45

1. Output Voltage

pg. 63
MODEL GRAPH:

pg. 64
RESULT:

The design of the Astable and Monostable multivibrator circuit was doneand the input and
output waveforms were obtained.

pg. 65
PIN DIAGRAM:

CIRCUIT DIAGRAM OF INVERTING AMPLIFIER:

pg. 66
 EXP.NO: 11 DESIGNS OF INVERTING AND NON-INVERTING
AMPLIFIER, ADDER, COMPARATOR AND DIFFERENTIATOR
AIM:
To design an Inverting, Non-Inverting Amplifier, adder, comparator, integrator and
differentiator forthe given specifications using Op-Amp IC 741.
APPARATUS REQUIRED:
S. Name of the Apparatus Range Quantity
No
1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC 741 1
5. Bread Board 1KΩ, 15KΩ Each 1
6. Resistors As required
7. Connecting wires and probes As required

THEORY:

INVERTING AMPLIFIER
The input signal Vi is applied to the inverting input terminal through R1 and the non-
inverting input terminal of the op-amp is grounded. The output voltage Vo is fed back to the
inverting input terminal through the Rf - R1 network, where Rf is the feedback resistor. The output
voltage is given as,
Vo = - ACL Vi

Here the negative sign indicates that the output voltage is 1800 out of phase with the input signal.
NON-INVERTING AMPLIFIER
The input signal Vi is applied to the non - inverting input terminal of the op-amp. This
circuit amplifies the signal without inverting the input signal. It is also called negative feedback
system since the output is feedback to the inverting input terminals. The differential voltage V d at
the inverting input terminal of the op-amp is zero ideally and the output voltage is given as,
Vo = ACL Vi
Here the output voltage is in phase with the input signal.

pg. 67
INVERTINGAMPLIFIER:

INPUT SIGNAL:

Amplitude

Time Period

OUTPUT SIGNAL:

pg. 68
ADDER
Op-Amp may be used to design a circuit whose output is the sum of several input signals such
as circuit is called a summing amplifier or summer. We can obtain either inverting or non-
invertingsummer.
The circuit diagrams show a two-input inverting summing amplifier. It has two input
voltages V1and V2, two input resistors R1, R2 and a feedback resistor Rf.
V1/R1 +V2/R2 +V0/Rf =0

Thus, output is inverted and sum of input.

COMPARATOR
A comparator is a circuit which compares a signal voltage applied at one input of an op-amp with
a known reference voltage at the other input. It is basically an open loop op-amp with output
±Vsat as in the ideal transfer characteristics
DIFFERENTIATOR
The differentiator circuit performs the mathematical operation of differentiation; that is,
the output waveform is the derivative of the input waveform. The differentiator may be
constructed from a basic inverting amplifier if an input resistor R 1 is replaced by a capacitor C1.
The expression for the output voltage is given as, Vo = - Rf C1 (dVi /dt)

Here the negative sign indicates that the output voltage is 180 0 out of phase with
theinput signal. A resistor Rcomp = Rf is normally connected to the non-inverting input terminal
of the op-amp to compensate for the input bias current. A workable differentiator can be designed
by implementing the following steps:
1. Select fa equal to the highest frequency of the input signal to be differentiated. Then,
assuming a value of C1 < 1 µF, calculate the value of Rf.
2. Choose fb = 10 fa and calculate the values of R1 and Cf so that R1C1 = Rf Cf.
3. The differentiator is most commonly used in wave shaping circuits to detect high
frequency components in an input signal and also as a rate–of–change detector in FM
modulators.

pg. 69
 NON INVERITNG AMPLIFIER
PIN DIAGRAM:

CIRCUIT DIAGRAM OF NON INVERITNG AMPLIFIER:

pg. 70
INTEGRATOR
A circuit in which the output voltage waveform is the integral of the input voltage
waveform is the integrator. Such a circuit is obtained by using a basic inverting amplifier
configuration if the feedback resistor Rf is replaced by a capacitor Cf . The expression for the
output voltage is given as,
Vo = - (1/Rf C1) ∫ Vi dt

Here the negative sign indicates that the output voltage is 180 0 out of phase with
theinput signal. Normally between fa and fb the circuit acts as an integrator. Generally, the value
offa > fb . The input signal will be integrated properly if the Time period T of the signal is larger
than or equal to Rf Cf. That is,
T ≥ Rf Cf
The integrator is most commonly used in analog computers and ADC and signal-wave
shaping circuits.
INVERTING AMPLIFIER:

PROCEDURE:

1. Connections are given as per the circuit diagram.

2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator, appropriate
input voltage is applied to the inverting input terminal of the Op-Amp.
The output voltage is obtained in the CRO and the input and output voltage waveforms are
plottedin a graph sheet
DESIGN:
We know for an inverting Amplifier ACL = RF / R1Assume R1 (approx. 10 KΩ) and find
Rf
Hence VO (theoretical) = - ACL VI
OBSERVATIONS:
S. No. Parameter Input Output

1 Amplitude 0.75 V 0.9 V

2 Time Period 1.76 ms 1.76 ms

pg. 71
 MODEL GRAPH:NON-INVERTINGAMPLIFIER:

INPUT SIGNAL:

Amplitude

OUTPUT SIGNAL:
Amplitude

pg. 72
NON - INVERTING AMPLIFIER:
PROCEDURE:

1. Connections are given as per the circuit diagram.

2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.

3. By adjusting the amplitude and frequency knobs of the function generator,

appropriateinput voltage is applied to the non - inverting input terminal of the Op-Amp.
4. The output voltage is obtained in the CRO and the input and output voltage waveforms
areplotted in a graph sheet
DESIGN:
We know for a Non-inverting Amplifier ACL = 1 + (RF / R1)Assume R1 (approx. 10 KΩ )
and find RfHence Vo = ACL Vi
OBSERVATIONS:
S. No. Amplitude Time period
(No. of div x Volts per div) (No. of div x Time per div)
Input 3.3 V 0.3.8 ms
Output 0.9 V 3.8 ms
Practical -
Comparator:

It is clear that the change in the output state takes place with an increment in input Vi of only 2mv.
This is the uncertainty region where output cannot be directly defined There arebasically 2 types of
comparators.
1. Non inverting comparator and. 2. Inverting comparator.
The applications of comparator are zero crossing detector, window detector, time marker generator
and phase meter.

pg. 73
ADDER CIRCUIT DIAGRAM:

COMPARATOR CIRCUIT DIAGRAM:

pg. 74
PROCEDURE:
ADDER:

1. connections are made as per the circuit diagram.

2. Apply input voltage 1) V1= 5v, V2=2v
2) V1= 5v, V2=5v 3) V1=
5v, V2=7v.
3. Using Millimetre measure the dc output voltage at the output terminal.
4. For different values of V1 and V2 measure the output voltage.

COMPARATOR:
1. Connections are made as per the circuit diagram.
2. Select the sine wave of 10V peak to peak, 1K Hz frequency.
3. Apply the reference voltage 2V and trace the input and output wave forms.
4. Superimpose input and output waveforms and measure sine wave amplitudewith reference to
Vref.
5. Repeat steps 3 and 4 with reference voltages as 2V, 4V, -2V, -4V and observe the
waveforms.
6. Replace sine wave input with 5V dc voltage and Vref= 0V.
7. Observe dc voltage at output using CRO.
8. Slowly increase Vref voltage and observe the change in saturation voltage.

DIFFERENTIATOR:
DESIGN:

Given fa = 1KHz
We know the frequency at which the gain is 0 dB, fa = 1 / (2π Rf C1)Let us assume C1 = 0.01 µF; then

Rf = 1/(2π(1 x 103)( 0.01 x 10-6) )= 15.9KΩ ≈ 15KΩ

Since fb = 10 fa, fb = 10 KHz

We know that the gain limiting frequency fb = 1 / (2π R1 C1) Hence R1 = 1 /(2π(10 x 103)( 0.01 x 10-
6) ) = 1.59 KΩ ≈ 1.5KΩ Also since R1C1 = Rf Cf ; Cf = R1C1 / Rf

Cf = (1.5 x103 x 0.01 x 10-6) / (15 x 103 ) = 0.001 µF

pg. 75
CIRCUIT DIAGRAM OF DIFFERENTIATOR:

MODEL GRAPH:
DIFFERENTIATOR:
INPUT SIGNAL:

Time
Period

OUTPUT SIGNAL:
Amplitude

Time Period

pg. 76
OBSERVATIONS:
Input - Sine wave
S. No. Amplitude Time period
(No. of div x Volts per div) (No. of div x Time per div)
Input 0.8 V 10.6 ms
Output 1.6 V 1.6 ms

PROCEDURE:
1. Connections are given as per the circuit diagram.
2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator,
appropriateinput voltage is applied to the inverting input terminal of the Op-Amp.
4. The output voltage is obtained in the CRO and the input and output voltage
waveformsare plotted in a graph sheet.

INTEGRATOR:
PROCEDURE:
1. Connections are given as per the circuit diagram.
2. +Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator,
appropriateinput voltage is applied to the inverting input terminal of the Op-Amp.
4. The output voltage is obtained in the CRO and the input and output voltage wave
forms are plotted in a graph sheet.
Design:

Rf = 1 / (2π (1000)(0.01 x 10-6) =15.9 KΩ ≈ 15KΩ

R1=1/ (2 π (10000) (0.01 x 10-6) =1.59 KΩ ≈ 1.5KΩ

OBSERVATIONS:
S.No. Amplitude Time period
(No. of div x Volts per div) (No. of div x Time per div)
Input 2.8 V 0.8 ms
Output 6V 0.8 ms
5.

pg. 77
INTEGRATOR PIN DIAGRAM:

CIRCUIT DIAGRAM OF INTEGRATOR:

MODEL GRAPH INTEGRATOR:

INPUT SIGNAL:
Amplitude

Time
Period

OUTPUT SIGNAL

pg. 78
RESULT:
Thus, the design of the Inverting and Non-Inverting Amplifier, Adder, Comparator,
Integrator, And Differentiator circuit was done and the input and output wave forms were
obtained.

pg. 79
CIRCUIT DIAGRAM:

Tabulation:

Vin Variable Resistor Vout

28 1K Ohm 9.1

28 2K Ohm 10

28 3K Ohm 11

28 4K Ohm 12

pg. 80
EXP.NO: 12 -VOLTAGE TO FREQUENCY CHARACTERISTICS OF
NE/ SE 566 IC
AIM:
To design and test the DC power supply using LM 317.
APPARATUS REQUIRED:

S. Name of the Apparatus Range Quantity

No
1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. IC LM314 1
5. Bread Board 1KΩ, 15KΩ Each 1
6. Resistors As required -
7 Capacitors As required -
8. Connecting wires and probes As required -

THEORY:

The LM317 is a three terminal adjustable positive voltage regulator capable of supplying in
excess of 1.5 amps over an output range 1.25 to 37 V. Output voltage is set by voltage across R1 and R2
connected as shown in Fig. The terminal current is a R1 is constant 1.25 V and the adjustable terminal
current is less than 100 Micro amps. The output voltage can be closely approximately from
Vout=1.25[1+(r2/R1)] which ignore the adjustable terminal current but will be close if the current through
R1 and R2.

PROCEDURE:

1. Connections are made as per the circuit diagram.

2. To vary the unregulated power supply from (0-3)V and note down the corresponding output
voltage across the load resistance R1.

3. Plot the graph between resistance Vin and Vout.

pg. 81
pg. 82
RESULT:

Thus, the design and test the DC power supply using LM317 was done and waveforms were
obtained.

pg. 83
PIN DIAGRAM:

CIRCUIT DIAGRAM:

TABULATION:

S.No. Parameter Triangular Wave Square Wave

1 Amplitude 0.6 14.6

2 Time Period 10.6 16

pg. 84
 EXP.NO: 13 VARIABILITY VOLTAGE REGULATOR USING IC
LM317
AIM:
To study the voltage to frequency characteristics of NE/SE 566.

THEORY:

A VCO is an electronic oscillator whose oscillation frequency is controlled by a voltage input.

The applied input voltage determines the instantaneous oscillation frequency. Consequently, a VCO can
be used for frequency modulation (FM) or phase modulation (PM) by applying a modulating signal to
the control input. A VCO is also an integral part of a phase-locked loop. VCOs are used in synthesizers to
generate a waveform whose pitch can be adjusted by a voltage determined by a musical keyboard or
other input.

A voltage-to-frequency converter (VFC) is a special type of VCO designed to be very linear in frequency
control over a wide range of input control voltages. VCOs are used in analog applications such
as frequency modulation and frequency-shift keying. The functional relationship between the control
voltage and the output frequency for a VCO (especially those used at radio frequency) may not be linear,
but over small ranges, the relationship is approximately linear, and linear control theory can be used. A
voltage-to-frequency converter (VFC) is a special type of VCO designed to be very linear over a wide
range of input voltages.

Modeling for VCOs is often not concerned with the amplitude or shape (sinewave, triangle wave,
sawtooth) but rather its instantaneous phase. In effect, the focus is not on the time-domain
signal A sin(ωt+θ0) but rather the argument of the sine function (the phase). Consequently, modeling is
often done in the phase domain.

The instantaneous frequency of a VCO is often modeled as a linear relationship with its instantaneous
control voltage. The output phase of the oscillator is the integral of the instantaneous frequency.

RESULT:

Thus, the voltage to frequency characteristics of NE/SE 566 has been verified.

pg. 85
CIRCUIT DIAGRAM:

TABULATION:
S. No Parameter Input Output
1 Amplitude 2V 2V
2 Time Period 12 ms 12 ms

pg. 86
 CONTENT BEYOND SYLLABUS

EXP.NO: 14 DESIGN A SCHMIT TRIGGER USING IC 741

AIM:
To design and construct a Schmitt trigger using IC 741 OP-AMP.
APPARATUS REQUIRED:

S. Name of the Apparatus Range Quantity

No
1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. IC 741 1
5. Bread Board 1KΩ, 15KΩ Each 1
6. Resistors As required -
8. Connecting wires and probes As required -

THEORY:

A Schmitt trigger a comparator circuit with hysteresis implemented by applying positive

feedback to the non-inverting input of a comparator or differential amplifier. It is an active
circuit which converts an analogy input signal to a digital output signal. The circuit is named
a trigger because the output retains its value until the input changes sufficiently to trigger a change.
In the non-inverting configuration, when the input is higher than a chosen threshold, the output is
high. When the input is below a different (lower) chosen threshold, the output is low, and when the
input is between the two levels the output retains its value. This dual threshold action is
called hysteresis and implies that the Schmitt trigger possesses memory and can act as a bistable
multivibrator (latch or flip-flop). There is a close relation between the two kinds of circuits: a Schmitt
trigger can be converted into a latch and a latch can be converted into a Schmitt trigger.

pg. 87
pg. 88
 PROCEDURE:
1. Initially set VCC=12 V and VCC=-12V
2. Measure all resistor that are used in the amplifier circuit using the multimeter and record these
values.
3. As shown in the fig., Connect the circuit for Schmitt trigger on a bread board.
4. Apply the input sine wave using FG.
5. Connect the channel 1 CRO at the input terminal and Channel 2 at the output terminal.
6. Observe the output square wave corresponding to input sine wave.

RESULT:

Thus, the output of Schmitt trigger using IC 741 is observed.

pg. 89
BLOCK DIAGRAM:

pg. 90
 EXP.NO: 15 STUDY OF SMPS
AIM:
To study the Switched Mode Power Supply.
THEORY:

The full form of SMPS is Switched Mode Power Supply also known as Switching Mode Power
Supply. SMPS is an electronic power supply system that makes use of a switching regulator to transfer
electrical power effectively. It is a PSU (power supply unit) and is usually used in computers to change
the voltage to the appropriate range for the computer.

An SMPS adjusts output voltage and current between different electrical configurations by
switching the basics of typically lossless storage such as capacitors and inductors. Ideal switching
concepts determined by transistors controlled outside of their active state that have no resistance when
‘on’ and carry no current when ‘off.’ It is the idea why switches with an ideal function will operate with
100 per cent output, that is, all input energy is provided to the load; no power is wasted as dissipated
heating. In fact, such ideal systems do not exist, which is why a switching power source can not be 100
per cent proficient, but it is still a vital improvement in effectiveness over a linear regulator.

Working principles of SMPS

In the SMPS device, the switching regulators are used which switches on and off the load current to
maintain and regulate the voltage output. Suitable power generation for a system is the mean voltage
between off and on. Unlike the linear power supply, the SMPS carry transistor switches among low
dissipation, full-on and full-off phase, and spend much less time in high dissipation cycles, which
decreases depleted strength.

Benefits of SMPS

 The switch-mode power source is small in scale.

 The SMPS is very lightweight.

 SMPS power consumption is typically 60 to 70 per cent, which is ideal for use.

 SMPS is strongly anti-interference.

 The SMPS production range is large.

pg. 91
pg. 92
 Limitations of SMPS

 The complexity of SMPS is very large.

 The production reflection is high and its control is weak in the case of SMPS.

 Use of SMPS can only be a step-down regulator.

 In SMPS, the voltage output is just one.

RESULT:

Thus, the operation of SMPS controlled IC SG3524 is studied.

pg. 93
pg. 94