0% found this document useful (0 votes)
2 views

3_Verilog_assignment_sequential_ckts

The document outlines a Verilog assignment from eInfochips Training and Research Academy focused on modeling various sequential circuits. It includes tasks such as designing different types of latches, flip-flops, registers, and counters, along with specific functionalities like asynchronous resets and enables. The assignment emphasizes verification through testbenches and waveforms.

Uploaded by

Ruturaj Nakum
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
2 views

3_Verilog_assignment_sequential_ckts

The document outlines a Verilog assignment from eInfochips Training and Research Academy focused on modeling various sequential circuits. It includes tasks such as designing different types of latches, flip-flops, registers, and counters, along with specific functionalities like asynchronous resets and enables. The assignment emphasizes verification through testbenches and waveforms.

Uploaded by

Ruturaj Nakum
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

SEQUENTIAL CIRCUITS

eInfochips Training and Research Academy [eiTRA]


Verilog assignment
Sequential Circuits

Model following sequential circuits using Verilog. Verify its functional behavior with help of
testbench and waveforms.

Q1. D-Latch
Q2. SR-Latch
Q3. JK-Latch
Q4. D-Flipflop
(a) with asynchronous active low reset
(b) Synchronous reset
Q5. T-Flipflop
Q6. SR-Flipflop
Q7. JK-Flipflop
Q8. JK latch with enable and using the same create MS-JK Flipflop
Q9. JK-FF with asynchronous control signals like preset, clear
Q10. TFF using DFF Registers
Q11. An n-bit register with asynchronous clear and enable.
Q12. An n-bit shift register with asynchronous reset
Q13. Universal shift register
Q14. Serial In Parallel Out (SISO)
Q15. Serial In Parallel Out (SIPO)
Q.16 Parallel in Serial Out (PISO)
Q.17 Parallel In Parallel Out (PIPO)

1
SEQUENTIAL CIRCUITS

Counters
Q.18 Design an n-bit up/down counter with parallel load.
Q.19 A modulo-N up counter with synchronous reset. (N can be any number)
Q.20 following counters:
(a) 4-bit Johnson Counter
(b) 4-bit Ring Counter
(c) Gray counter
(d) Universal
Counter
(e) BCD counter
Q.21 Frequency divider by 2
Q.22 3-bit linear feedback shift register [LFSR].
Q.23 Following shift register.

You might also like