3_Verilog_assignment_sequential_ckts
3_Verilog_assignment_sequential_ckts
Model following sequential circuits using Verilog. Verify its functional behavior with help of
testbench and waveforms.
Q1. D-Latch
Q2. SR-Latch
Q3. JK-Latch
Q4. D-Flipflop
(a) with asynchronous active low reset
(b) Synchronous reset
Q5. T-Flipflop
Q6. SR-Flipflop
Q7. JK-Flipflop
Q8. JK latch with enable and using the same create MS-JK Flipflop
Q9. JK-FF with asynchronous control signals like preset, clear
Q10. TFF using DFF Registers
Q11. An n-bit register with asynchronous clear and enable.
Q12. An n-bit shift register with asynchronous reset
Q13. Universal shift register
Q14. Serial In Parallel Out (SISO)
Q15. Serial In Parallel Out (SIPO)
Q.16 Parallel in Serial Out (PISO)
Q.17 Parallel In Parallel Out (PIPO)
1
SEQUENTIAL CIRCUITS
Counters
Q.18 Design an n-bit up/down counter with parallel load.
Q.19 A modulo-N up counter with synchronous reset. (N can be any number)
Q.20 following counters:
(a) 4-bit Johnson Counter
(b) 4-bit Ring Counter
(c) Gray counter
(d) Universal
Counter
(e) BCD counter
Q.21 Frequency divider by 2
Q.22 3-bit linear feedback shift register [LFSR].
Q.23 Following shift register.