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0 Verilog Assignment Operators Level 1 (1)

The document is an assignment from eInfochips Training Research Academy focused on Verilog operators. It includes tasks such as writing Verilog code for specific equations and functions, designing a 4-to-1 multiplexer, and analyzing a simple adder module. The assignment emphasizes implementing circuits with minimal complexity and verifying designs with testbenches.

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Ruturaj Nakum
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10 views2 pages

0 Verilog Assignment Operators Level 1 (1)

The document is an assignment from eInfochips Training Research Academy focused on Verilog operators. It includes tasks such as writing Verilog code for specific equations and functions, designing a 4-to-1 multiplexer, and analyzing a simple adder module. The assignment emphasizes implementing circuits with minimal complexity and verifying designs with testbenches.

Uploaded by

Ruturaj Nakum
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VERILOG OPERATORS

eInfochips Training Research Academy [eiTRA]


Verilog Assignment
Operators: Level 1
Q1. Write Verilog code for given circuits.
(a)

(b)

Q2. (a) Write Verilog code for given Equation F = x1x3’ + x2x3’ + x3’x4’ + x1x2 + x1x4’
(b) Write Verilog code for given Equation F = (x1+x3’).(x1+x2+x4’).(x2+x3’+x4’)

1
VERILOG OPERATORS

Q3. (a) Write Verilog code to implement the function


f(x1, x2, x3, x4) = ∑ m (0,1,2,4,5,7,8,9,11,12,14,15)
Ensure that the resulting circuit is as simple as possible.

(b) Write Verilog code to implement the function


f(x1, x2, x3, x4) = ∑ m (1,4,7,14,15) + D(0,5,9)
Ensure that the resulting circuit is as simple as possible.

(c) Write Verilog code to implement the function


f(x1, x2, x3, x4) = π M(6,8,9,12,13)
Ensure that the resulting circuit is as simple as possible.

(d) Write Verilog code to implement the function


f(x1, x2, x3, x4) = π M (3, 11, 14) + D(0,2,10,12)
Ensure that the resulting circuit is as simple as possible.

Q4. Design a 4*1 Multiplexer using conditional operator and verify it with testbench and
waveform.
Q5. Consider the following program:
module adder sign (X, Y, S, S2s);
input [3:0] X, Y;
output [7:0] S, S2s;
assign S = X + Y,
S2s = {{4{X[3]}}, X} + {{4{Y[3]}}, Y};
endmodule

(a) if X = 0011 and Y = 1101, What will be the value of S and S2s?
(b) What operation is assigned for S2s in the given program.

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